1 #ifndef __ASM_ARCH_MXC_MX51_H__
2 #define __ASM_ARCH_MXC_MX51_H__
9 * ---------------------------------------------------------------------------
10 * FA3E0000 1FFE0000 128K IRAM (SCCv2 RAM)
13 * FA200000 60000000 1M DEBUG
14 * FB100000 70000000 1M SPBA 0
15 * FB000000 73F00000 1M AIPS 1
16 * FB200000 83F00000 1M AIPS 2
17 * FA100000 8FFFC000 16K TZIC (interrupt controller)
18 * 90000000 256M CSD0 SDRAM/DDR
19 * A0000000 256M CSD1 SDRAM/DDR
20 * B0000000 128M CS0 Flash
21 * B8000000 128M CS1 Flash
22 * C0000000 128M CS2 Flash
23 * C8000000 64M CS3 Flash
24 * CC000000 32M CS4 SRAM
25 * CE000000 32M CS5 SRAM
26 * F9000000 CFFF0000 64K NFC (NAND Flash AXI)
33 #define MX51_IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */
34 #define MX51_IRAM_BASE_ADDR_VIRT 0xFA3E0000
35 #define MX51_IRAM_PARTITIONS 16
36 #define MX51_IRAM_PARTITIONS_TO1 12
37 #define MX51_IRAM_SIZE (MX51_IRAM_PARTITIONS * SZ_8K) /* 128KB */
42 #define MX51_NFC_AXI_BASE_ADDR 0xCFFF0000 /* NAND flash AXI */
43 #define MX51_NFC_AXI_BASE_ADDR_VIRT 0xF9000000
44 #define MX51_NFC_AXI_SIZE SZ_64K
47 * Graphics Memory of GPU
49 #define MX51_GPU_BASE_ADDR 0x20000000
50 #define MX51_GPU2D_BASE_ADDR 0xD0000000
52 #define MX51_TZIC_BASE_ADDR 0x8FFFC000
53 #define MX51_TZIC_BASE_ADDR_VIRT 0xFA100000
54 #define MX51_TZIC_SIZE SZ_16K
56 #define MX51_DEBUG_BASE_ADDR 0x60000000
57 #define MX51_DEBUG_BASE_ADDR_VIRT 0xFA200000
58 #define MX51_DEBUG_SIZE SZ_1M
59 #define MX51_ETB_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00001000)
60 #define MX51_ETM_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00002000)
61 #define MX51_TPIU_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00003000)
62 #define MX51_CTI0_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00004000)
63 #define MX51_CTI1_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00005000)
64 #define MX51_CTI2_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00006000)
65 #define MX51_CTI3_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00007000)
66 #define MX51_CORTEX_DBG_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00008000)
69 * SPBA global module enabled #0
71 #define MX51_SPBA0_BASE_ADDR 0x70000000
72 #define MX51_SPBA0_BASE_ADDR_VIRT 0xFB100000
73 #define MX51_SPBA0_SIZE SZ_1M
75 #define MX51_MMC_SDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00004000)
76 #define MX51_MMC_SDHC2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00008000)
77 #define MX51_UART3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0000C000)
78 #define MX51_CSPI1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00010000)
79 #define MX51_SSI2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00014000)
80 #define MX51_MMC_SDHC3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00020000)
81 #define MX51_MMC_SDHC4_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00024000)
82 #define MX51_SPDIF_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00028000)
83 #define MX51_ATA_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00030000)
84 #define MX51_SLIM_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00034000)
85 #define MX51_HSI2C_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00038000)
86 #define MX51_SPBA_CTRL_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0003C000)
89 * defines for SPBA modules
91 #define MX51_SPBA_SDHC1 0x04
92 #define MX51_SPBA_SDHC2 0x08
93 #define MX51_SPBA_UART3 0x0C
94 #define MX51_SPBA_CSPI1 0x10
95 #define MX51_SPBA_SSI2 0x14
96 #define MX51_SPBA_SDHC3 0x20
97 #define MX51_SPBA_SDHC4 0x24
98 #define MX51_SPBA_SPDIF 0x28
99 #define MX51_SPBA_ATA 0x30
100 #define MX51_SPBA_SLIM 0x34
101 #define MX51_SPBA_HSI2C 0x38
102 #define MX51_SPBA_CTRL 0x3C
107 #define MX51_AIPS1_BASE_ADDR 0x73F00000
108 #define MX51_AIPS1_BASE_ADDR_VIRT 0xFB000000
109 #define MX51_AIPS1_SIZE SZ_1M
111 #define MX51_OTG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00080000)
112 #define MX51_GPIO1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00084000)
113 #define MX51_GPIO2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00088000)
114 #define MX51_GPIO3_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x0008C000)
115 #define MX51_GPIO4_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00090000)
116 #define MX51_KPP_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00094000)
117 #define MX51_WDOG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00098000)
118 #define MX51_WDOG2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x0009C000)
119 #define MX51_GPT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000A0000)
120 #define MX51_SRTC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000A4000)
121 #define MX51_IOMUXC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000A8000)
122 #define MX51_EPIT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000AC000)
123 #define MX51_EPIT2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000B0000)
124 #define MX51_PWM1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000B4000)
125 #define MX51_PWM2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000B8000)
126 #define MX51_UART1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000BC000)
127 #define MX51_UART2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000C0000)
128 #define MX51_SRC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000D0000)
129 #define MX51_CCM_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000D4000)
130 #define MX51_GPC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000D8000)
133 * Defines for modules using static and dynamic DMA channels
135 #define MX51_MXC_DMA_CHANNEL_IRAM 30
136 #define MX51_MXC_DMA_CHANNEL_SPDIF_TX MXC_DMA_DYNAMIC_CHANNEL
137 #define MX51_MXC_DMA_CHANNEL_UART1_RX MXC_DMA_DYNAMIC_CHANNEL
138 #define MX51_MXC_DMA_CHANNEL_UART1_TX MXC_DMA_DYNAMIC_CHANNEL
139 #define MX51_MXC_DMA_CHANNEL_UART2_RX MXC_DMA_DYNAMIC_CHANNEL
140 #define MX51_MXC_DMA_CHANNEL_UART2_TX MXC_DMA_DYNAMIC_CHANNEL
141 #define MX51_MXC_DMA_CHANNEL_UART3_RX MXC_DMA_DYNAMIC_CHANNEL
142 #define MX51_MXC_DMA_CHANNEL_UART3_TX MXC_DMA_DYNAMIC_CHANNEL
143 #define MX51_MXC_DMA_CHANNEL_MMC1 MXC_DMA_DYNAMIC_CHANNEL
144 #define MX51_MXC_DMA_CHANNEL_MMC2 MXC_DMA_DYNAMIC_CHANNEL
145 #define MX51_MXC_DMA_CHANNEL_SSI1_RX MXC_DMA_DYNAMIC_CHANNEL
146 #define MX51_MXC_DMA_CHANNEL_SSI1_TX MXC_DMA_DYNAMIC_CHANNEL
147 #define MX51_MXC_DMA_CHANNEL_SSI2_RX MXC_DMA_DYNAMIC_CHANNEL
148 #ifdef CONFIG_SDMA_IRAM
149 #define MX51_MXC_DMA_CHANNEL_SSI2_TX (MX51_MXC_DMA_CHANNEL_IRAM + 1)
150 #else /*CONFIG_SDMA_IRAM */
151 #define MX51_MXC_DMA_CHANNEL_SSI2_TX MXC_DMA_DYNAMIC_CHANNEL
152 #endif /*CONFIG_SDMA_IRAM */
153 #define MX51_MXC_DMA_CHANNEL_CSPI1_RX MXC_DMA_DYNAMIC_CHANNEL
154 #define MX51_MXC_DMA_CHANNEL_CSPI1_TX MXC_DMA_DYNAMIC_CHANNEL
155 #define MX51_MXC_DMA_CHANNEL_CSPI2_RX MXC_DMA_DYNAMIC_CHANNEL
156 #define MX51_MXC_DMA_CHANNEL_CSPI2_TX MXC_DMA_DYNAMIC_CHANNEL
157 #define MX51_MXC_DMA_CHANNEL_CSPI3_RX MXC_DMA_DYNAMIC_CHANNEL
158 #define MX51_MXC_DMA_CHANNEL_CSPI3_TX MXC_DMA_DYNAMIC_CHANNEL
159 #define MX51_MXC_DMA_CHANNEL_ATA_RX MXC_DMA_DYNAMIC_CHANNEL
160 #define MX51_MXC_DMA_CHANNEL_ATA_TX MXC_DMA_DYNAMIC_CHANNEL
161 #define MX51_MXC_DMA_CHANNEL_MEMORY MXC_DMA_DYNAMIC_CHANNEL
166 #define MX51_AIPS2_BASE_ADDR 0x83F00000
167 #define MX51_AIPS2_BASE_ADDR_VIRT 0xFB200000
168 #define MX51_AIPS2_SIZE SZ_1M
170 #define MX51_PLL1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00080000)
171 #define MX51_PLL2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00084000)
172 #define MX51_PLL3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00088000)
173 #define MX51_AHBMAX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00094000)
174 #define MX51_IIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00098000)
175 #define MX51_CSU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x0009C000)
176 #define MX51_ARM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A0000)
177 #define MX51_OWIRE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A4000)
178 #define MX51_FIRI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A8000)
179 #define MX51_CSPI2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000AC000)
180 #define MX51_SDMA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B0000)
181 #define MX51_SCC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B4000)
182 #define MX51_ROMCP_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B8000)
183 #define MX51_RTIC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000BC000)
184 #define MX51_CSPI3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C0000)
185 #define MX51_I2C2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C4000)
186 #define MX51_I2C1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C8000)
187 #define MX51_SSI1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000CC000)
188 #define MX51_AUDMUX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000D0000)
189 #define MX51_M4IF_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000D8000)
190 #define MX51_ESDCTL_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000D9000)
191 #define MX51_WEIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DA000)
192 #define MX51_NFC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DB000)
193 #define MX51_EMI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DBF00)
194 #define MX51_MIPI_HSC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DC000)
195 #define MX51_ATA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000E0000)
196 #define MX51_SIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000E4000)
197 #define MX51_SSI3BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000E8000)
198 #define MX51_MXC_FEC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000EC000)
199 #define MX51_TVE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F0000)
200 #define MX51_VPU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F4000)
201 #define MX51_SAHARA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F8000)
204 * Memory regions and CS
206 #define MX51_GPU_CTRL_BASE_ADDR 0x30000000
207 #define MX51_IPU_CTRL_BASE_ADDR 0x40000000
208 #define MX51_CSD0_BASE_ADDR 0x90000000
209 #define MX51_CSD1_BASE_ADDR 0xA0000000
210 #define MX51_CS0_BASE_ADDR 0xB0000000
211 #define MX51_CS1_BASE_ADDR 0xB8000000
212 #define MX51_CS2_BASE_ADDR 0xC0000000
213 #define MX51_CS3_BASE_ADDR 0xC8000000
214 #define MX51_CS4_BASE_ADDR 0xCC000000
215 #define MX51_CS5_BASE_ADDR 0xCE000000
217 /* Does given address belongs to the specified memory region? */
218 #define ADDRESS_IN_REGION(addr, start, size) \
219 (((addr) >= (start)) && ((addr) < (start)+(size)))
221 /* Does given address belongs to the specified named `module'? */
222 #define MX51_IS_MODULE(addr, module) \
223 ADDRESS_IN_REGION(addr, MX51_ ## module ## _BASE_ADDR, \
224 MX51_ ## module ## _SIZE)
226 * This macro defines the physical to virtual address mapping for all the
227 * peripheral modules. It is used by passing in the physical address as x
228 * and returning the virtual address. If the physical address is not mapped,
229 * it returns 0xDEADBEEF
232 #define MX51_IO_ADDRESS(x) \
234 (MX51_IS_MODULE(x, IRAM) ? MX51_IRAM_IO_ADDRESS(x) : \
235 MX51_IS_MODULE(x, TZIC) ? MX51_TZIC_IO_ADDRESS(x) : \
236 MX51_IS_MODULE(x, DEBUG) ? MX51_DEBUG_IO_ADDRESS(x) : \
237 MX51_IS_MODULE(x, SPBA0) ? MX51_SPBA0_IO_ADDRESS(x) : \
238 MX51_IS_MODULE(x, AIPS1) ? MX51_AIPS1_IO_ADDRESS(x) : \
239 MX51_IS_MODULE(x, AIPS2) ? MX51_AIPS2_IO_ADDRESS(x) : \
240 MX51_IS_MODULE(x, NFC_AXI) ? MX51_NFC_AXI_IO_ADDRESS(x) : \
244 * define the address mapping macros: in physical address order
246 #define MX51_IRAM_IO_ADDRESS(x) \
247 (((x) - MX51_IRAM_BASE_ADDR) + MX51_IRAM_BASE_ADDR_VIRT)
249 #define MX51_TZIC_IO_ADDRESS(x) \
250 (((x) - MX51_TZIC_BASE_ADDR) + MX51_TZIC_BASE_ADDR_VIRT)
252 #define MX51_DEBUG_IO_ADDRESS(x) \
253 (((x) - MX51_DEBUG_BASE_ADDR) + MX51_DEBUG_BASE_ADDR_VIRT)
255 #define MX51_SPBA0_IO_ADDRESS(x) \
256 (((x) - MX51_SPBA0_BASE_ADDR) + MX51_SPBA0_BASE_ADDR_VIRT)
258 #define MX51_AIPS1_IO_ADDRESS(x) \
259 (((x) - MX51_AIPS1_BASE_ADDR) + MX51_AIPS1_BASE_ADDR_VIRT)
261 #define MX51_AIPS2_IO_ADDRESS(x) \
262 (((x) - MX51_AIPS2_BASE_ADDR) + MX51_AIPS2_BASE_ADDR_VIRT)
264 #define MX51_NFC_AXI_IO_ADDRESS(x) \
265 (((x) - MX51_NFC_AXI_BASE_ADDR) + MX51_NFC_AXI_BASE_ADDR_VIRT)
267 #define MX51_IS_MEM_DEVICE_NONSHARED(x) 0
270 * DMA request assignments
272 #define MX51_DMA_REQ_SSI3_TX1 47
273 #define MX51_DMA_REQ_SSI3_RX1 46
274 #define MX51_DMA_REQ_SPDIF 45
275 #define MX51_DMA_REQ_UART3_TX 44
276 #define MX51_DMA_REQ_UART3_RX 43
277 #define MX51_DMA_REQ_SLIM_B_TX 42
278 #define MX51_DMA_REQ_SDHC4 41
279 #define MX51_DMA_REQ_SDHC3 40
280 #define MX51_DMA_REQ_CSPI_TX 39
281 #define MX51_DMA_REQ_CSPI_RX 38
282 #define MX51_DMA_REQ_SSI3_TX2 37
283 #define MX51_DMA_REQ_IPU 36
284 #define MX51_DMA_REQ_SSI3_RX2 35
285 #define MX51_DMA_REQ_EPIT2 34
286 #define MX51_DMA_REQ_CTI2_1 33
287 #define MX51_DMA_REQ_EMI_WR 32
288 #define MX51_DMA_REQ_CTI2_0 31
289 #define MX51_DMA_REQ_EMI_RD 30
290 #define MX51_DMA_REQ_SSI1_TX1 29
291 #define MX51_DMA_REQ_SSI1_RX1 28
292 #define MX51_DMA_REQ_SSI1_TX2 27
293 #define MX51_DMA_REQ_SSI1_RX2 26
294 #define MX51_DMA_REQ_SSI2_TX1 25
295 #define MX51_DMA_REQ_SSI2_RX1 24
296 #define MX51_DMA_REQ_SSI2_TX2 23
297 #define MX51_DMA_REQ_SSI2_RX2 22
298 #define MX51_DMA_REQ_SDHC2 21
299 #define MX51_DMA_REQ_SDHC1 20
300 #define MX51_DMA_REQ_UART1_TX 19
301 #define MX51_DMA_REQ_UART1_RX 18
302 #define MX51_DMA_REQ_UART2_TX 17
303 #define MX51_DMA_REQ_UART2_RX 16
304 #define MX51_DMA_REQ_GPU 15
305 #define MX51_DMA_REQ_EXTREQ1 14
306 #define MX51_DMA_REQ_FIRI_TX 13
307 #define MX51_DMA_REQ_FIRI_RX 12
308 #define MX51_DMA_REQ_HS_I2C_RX 11
309 #define MX51_DMA_REQ_HS_I2C_TX 10
310 #define MX51_DMA_REQ_CSPI2_TX 9
311 #define MX51_DMA_REQ_CSPI2_RX 8
312 #define MX51_DMA_REQ_CSPI1_TX 7
313 #define MX51_DMA_REQ_CSPI1_RX 6
314 #define MX51_DMA_REQ_SLIM_B 5
315 #define MX51_DMA_REQ_ATA_TX_END 4
316 #define MX51_DMA_REQ_ATA_TX 3
317 #define MX51_DMA_REQ_ATA_RX 2
318 #define MX51_DMA_REQ_GPC 1
319 #define MX51_DMA_REQ_VPU 0
324 #define MX51_MXC_INT_BASE 0
325 #define MX51_MXC_INT_RESV0 0
326 #define MX51_MXC_INT_MMC_SDHC1 1
327 #define MX51_MXC_INT_MMC_SDHC2 2
328 #define MX51_MXC_INT_MMC_SDHC3 3
329 #define MX51_MXC_INT_MMC_SDHC4 4
330 #define MX51_MXC_INT_RESV5 5
331 #define MX51_MXC_INT_SDMA 6
332 #define MX51_MXC_INT_IOMUX 7
333 #define MX51_MXC_INT_NFC 8
334 #define MX51_MXC_INT_VPU 9
335 #define MX51_MXC_INT_IPU_ERR 10
336 #define MX51_MXC_INT_IPU_SYN 11
337 #define MX51_MXC_INT_GPU 12
338 #define MX51_MXC_INT_RESV13 13
339 #define MX51_MXC_INT_USB_H1 14
340 #define MX51_MXC_INT_EMI 15
341 #define MX51_MXC_INT_USB_H2 16
342 #define MX51_MXC_INT_USB_H3 17
343 #define MX51_MXC_INT_USB_OTG 18
344 #define MX51_MXC_INT_SAHARA_H0 19
345 #define MX51_MXC_INT_SAHARA_H1 20
346 #define MX51_MXC_INT_SCC_SMN 21
347 #define MX51_MXC_INT_SCC_STZ 22
348 #define MX51_MXC_INT_SCC_SCM 23
349 #define MX51_MXC_INT_SRTC_NTZ 24
350 #define MX51_MXC_INT_SRTC_TZ 25
351 #define MX51_MXC_INT_RTIC 26
352 #define MX51_MXC_INT_CSU 27
353 #define MX51_MXC_INT_SLIM_B 28
354 #define MX51_MXC_INT_SSI1 29
355 #define MX51_MXC_INT_SSI2 30
356 #define MX51_MXC_INT_UART1 31
357 #define MX51_MXC_INT_UART2 32
358 #define MX51_MXC_INT_UART3 33
359 #define MX51_MXC_INT_RESV34 34
360 #define MX51_MXC_INT_RESV35 35
361 #define MX51_MXC_INT_CSPI1 36
362 #define MX51_MXC_INT_CSPI2 37
363 #define MX51_MXC_INT_CSPI 38
364 #define MX51_MXC_INT_GPT 39
365 #define MX51_MXC_INT_EPIT1 40
366 #define MX51_MXC_INT_EPIT2 41
367 #define MX51_MXC_INT_GPIO1_INT7 42
368 #define MX51_MXC_INT_GPIO1_INT6 43
369 #define MX51_MXC_INT_GPIO1_INT5 44
370 #define MX51_MXC_INT_GPIO1_INT4 45
371 #define MX51_MXC_INT_GPIO1_INT3 46
372 #define MX51_MXC_INT_GPIO1_INT2 47
373 #define MX51_MXC_INT_GPIO1_INT1 48
374 #define MX51_MXC_INT_GPIO1_INT0 49
375 #define MX51_MXC_INT_GPIO1_LOW 50
376 #define MX51_MXC_INT_GPIO1_HIGH 51
377 #define MX51_MXC_INT_GPIO2_LOW 52
378 #define MX51_MXC_INT_GPIO2_HIGH 53
379 #define MX51_MXC_INT_GPIO3_LOW 54
380 #define MX51_MXC_INT_GPIO3_HIGH 55
381 #define MX51_MXC_INT_GPIO4_LOW 56
382 #define MX51_MXC_INT_GPIO4_HIGH 57
383 #define MX51_MXC_INT_WDOG1 58
384 #define MX51_MXC_INT_WDOG2 59
385 #define MX51_MXC_INT_KPP 60
386 #define MX51_MXC_INT_PWM1 61
387 #define MX51_MXC_INT_I2C1 62
388 #define MX51_MXC_INT_I2C2 63
389 #define MX51_MXC_INT_HS_I2C 64
390 #define MX51_MXC_INT_RESV65 65
391 #define MX51_MXC_INT_RESV66 66
392 #define MX51_MXC_INT_SIM_IPB 67
393 #define MX51_MXC_INT_SIM_DAT 68
394 #define MX51_MXC_INT_IIM 69
395 #define MX51_MXC_INT_ATA 70
396 #define MX51_MXC_INT_CCM1 71
397 #define MX51_MXC_INT_CCM2 72
398 #define MX51_MXC_INT_GPC1 73
399 #define MX51_MXC_INT_GPC2 74
400 #define MX51_MXC_INT_SRC 75
401 #define MX51_MXC_INT_NM 76
402 #define MX51_MXC_INT_PMU 77
403 #define MX51_MXC_INT_CTI_IRQ 78
404 #define MX51_MXC_INT_CTI1_TG0 79
405 #define MX51_MXC_INT_CTI1_TG1 80
406 #define MX51_MXC_INT_MCG_ERR 81
407 #define MX51_MXC_INT_MCG_TMR 82
408 #define MX51_MXC_INT_MCG_FUNC 83
409 #define MX51_MXC_INT_GPU2_IRQ 84
410 #define MX51_MXC_INT_GPU2_BUSY 85
411 #define MX51_MXC_INT_RESV86 86
412 #define MX51_MXC_INT_FEC 87
413 #define MX51_MXC_INT_OWIRE 88
414 #define MX51_MXC_INT_CTI1_TG2 89
415 #define MX51_MXC_INT_SJC 90
416 #define MX51_MXC_INT_SPDIF 91
417 #define MX51_MXC_INT_TVE 92
418 #define MX51_MXC_INT_FIRI 93
419 #define MX51_MXC_INT_PWM2 94
420 #define MX51_MXC_INT_SLIM_EXP 95
421 #define MX51_MXC_INT_SSI3 96
422 #define MX51_MXC_INT_EMI_BOOT 97
423 #define MX51_MXC_INT_CTI1_TG3 98
424 #define MX51_MXC_INT_SMC_RX 99
425 #define MX51_MXC_INT_VPU_IDLE 100
426 #define MX51_MXC_INT_EMI_NFC 101
427 #define MX51_MXC_INT_GPU_IDLE 102
429 /* silicon revisions specific to i.MX51 */
430 #define MX51_CHIP_REV_1_0 0x10
431 #define MX51_CHIP_REV_1_1 0x11
432 #define MX51_CHIP_REV_1_2 0x12
433 #define MX51_CHIP_REV_1_3 0x13
434 #define MX51_CHIP_REV_2_0 0x20
435 #define MX51_CHIP_REV_2_1 0x21
436 #define MX51_CHIP_REV_2_2 0x22
437 #define MX51_CHIP_REV_2_3 0x23
438 #define MX51_CHIP_REV_3_0 0x30
439 #define MX51_CHIP_REV_3_1 0x31
440 #define MX51_CHIP_REV_3_2 0x32
442 /* Mandatory defines used globally */
444 #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
446 extern unsigned int system_rev;
448 static inline unsigned int mx51_revision(void)
454 #endif /* __ASM_ARCH_MXC_MX51_H__ */