1 #ifndef __MACH_MX31_H__
2 #define __MACH_MX31_H__
11 #define MX31_IRAM_BASE_ADDR 0x1ffc0000 /* internal ram */
12 #define MX31_IRAM_SIZE SZ_16K
14 #define MX31_L2CC_BASE_ADDR 0x30000000
15 #define MX31_L2CC_SIZE SZ_1M
17 #define MX31_AIPS1_BASE_ADDR 0x43f00000
18 #define MX31_AIPS1_BASE_ADDR_VIRT 0xfc000000
19 #define MX31_AIPS1_SIZE SZ_1M
20 #define MX31_MAX_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x04000)
21 #define MX31_EVTMON_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x08000)
22 #define MX31_CLKCTL_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x0c000)
23 #define MX31_ETB_SLOT4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x10000)
24 #define MX31_ETB_SLOT5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x14000)
25 #define MX31_ECT_CTIO_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x18000)
26 #define MX31_I2C1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x80000)
27 #define MX31_I2C3_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x84000)
28 #define MX31_OTG_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000)
29 #define MX31_ATA_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x8c000)
30 #define MX31_UART1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x90000)
31 #define MX31_UART2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x94000)
32 #define MX31_I2C2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x98000)
33 #define MX31_OWIRE_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x9c000)
34 #define MX31_SSI1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa0000)
35 #define MX31_CSPI1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa4000)
36 #define MX31_KPP_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa8000)
37 #define MX31_IOMUXC_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xac000)
38 #define MX31_UART4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb0000)
39 #define MX31_UART5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb4000)
40 #define MX31_ECT_IP1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb8000)
41 #define MX31_ECT_IP2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xbc000)
43 #define MX31_SPBA0_BASE_ADDR 0x50000000
44 #define MX31_SPBA0_BASE_ADDR_VIRT 0xfc100000
45 #define MX31_SPBA0_SIZE SZ_1M
46 #define MX31_MMC_SDHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x04000)
47 #define MX31_MMC_SDHC2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x08000)
48 #define MX31_UART3_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x0c000)
49 #define MX31_CSPI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x10000)
50 #define MX31_SSI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x14000)
51 #define MX31_SIM1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x18000)
52 #define MX31_IIM_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x1c000)
53 #define MX31_ATA_DMA_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x20000)
54 #define MX31_MSHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x24000)
55 #define MX31_SPBA_CTRL_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x3c000)
57 #define MX31_AIPS2_BASE_ADDR 0x53f00000
58 #define MX31_AIPS2_BASE_ADDR_VIRT 0xfc200000
59 #define MX31_AIPS2_SIZE SZ_1M
60 #define MX31_CCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x80000)
61 #define MX31_CSPI3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x84000)
62 #define MX31_FIRI_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x8c000)
63 #define MX31_GPT1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x90000)
64 #define MX31_EPIT1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x94000)
65 #define MX31_EPIT2_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x98000)
66 #define MX31_GPIO3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xa4000)
67 #define MX31_SCC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xac000)
68 #define MX31_SCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xae000)
69 #define MX31_SMN_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xaf000)
70 #define MX31_RNGA_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xb0000)
71 #define MX31_IPU_CTRL_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc0000)
72 #define MX31_AUDMUX_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc4000)
73 #define MX31_MPEG4_ENC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc8000)
74 #define MX31_GPIO1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xcc000)
75 #define MX31_GPIO2_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd0000)
76 #define MX31_SDMA_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd4000)
77 #define MX31_RTC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd8000)
78 #define MX31_WDOG_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xdc000)
79 #define MX31_PWM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xe0000)
80 #define MX31_RTIC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xec000)
82 #define MX31_ROMP_BASE_ADDR 0x60000000
83 #define MX31_ROMP_BASE_ADDR_VIRT 0xfc500000
84 #define MX31_ROMP_SIZE SZ_1M
86 #define MX31_AVIC_BASE_ADDR 0x68000000
87 #define MX31_AVIC_BASE_ADDR_VIRT 0xfc400000
88 #define MX31_AVIC_SIZE SZ_1M
90 #define MX31_IPU_MEM_BASE_ADDR 0x70000000
91 #define MX31_CSD0_BASE_ADDR 0x80000000
92 #define MX31_CSD1_BASE_ADDR 0x90000000
94 #define MX31_CS0_BASE_ADDR 0xa0000000
95 #define MX31_CS1_BASE_ADDR 0xa8000000
96 #define MX31_CS2_BASE_ADDR 0xb0000000
97 #define MX31_CS3_BASE_ADDR 0xb2000000
99 #define MX31_CS4_BASE_ADDR 0xb4000000
100 #define MX31_CS4_BASE_ADDR_VIRT 0xf4000000
101 #define MX31_CS4_SIZE SZ_32M
103 #define MX31_CS5_BASE_ADDR 0xb6000000
104 #define MX31_CS5_BASE_ADDR_VIRT 0xf6000000
105 #define MX31_CS5_SIZE SZ_32M
107 #define MX31_X_MEMC_BASE_ADDR 0xb8000000
108 #define MX31_X_MEMC_BASE_ADDR_VIRT 0xfc320000
109 #define MX31_X_MEMC_SIZE SZ_64K
110 #define MX31_NFC_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x0000)
111 #define MX31_ESDCTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x1000)
112 #define MX31_WEIM_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x2000)
113 #define MX31_M3IF_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x3000)
114 #define MX31_EMI_CTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x4000)
115 #define MX31_PCMCIA_CTL_BASE_ADDR MX31_EMI_CTL_BASE_ADDR
117 #define MX31_WEIM_CSCRx_BASE_ADDR(cs) (MX31_WEIM_BASE_ADDR + (cs) * 0x10)
118 #define MX31_WEIM_CSCRxU(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs))
119 #define MX31_WEIM_CSCRxL(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x4)
120 #define MX31_WEIM_CSCRxA(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x8)
122 #define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000
124 #define MX31_IO_ADDRESS(x) ( \
125 IMX_IO_ADDRESS(x, MX31_AIPS1) ?: \
126 IMX_IO_ADDRESS(x, MX31_AIPS2) ?: \
127 IMX_IO_ADDRESS(x, MX31_AVIC) ?: \
128 IMX_IO_ADDRESS(x, MX31_X_MEMC) ?: \
129 IMX_IO_ADDRESS(x, MX31_SPBA0))
131 #ifndef __ASSEMBLER__
132 static inline void mx31_setup_weimcs(size_t cs,
133 unsigned upper, unsigned lower, unsigned addional)
135 __raw_writel(upper, MX31_IO_ADDRESS(MX31_WEIM_CSCRxU(cs)));
136 __raw_writel(lower, MX31_IO_ADDRESS(MX31_WEIM_CSCRxL(cs)));
137 __raw_writel(addional, MX31_IO_ADDRESS(MX31_WEIM_CSCRxA(cs)));
141 #define MX31_INT_I2C3 3
142 #define MX31_INT_I2C2 4
143 #define MX31_INT_MPEG4_ENCODER 5
144 #define MX31_INT_RTIC 6
145 #define MX31_INT_FIRI 7
146 #define MX31_INT_MMC_SDHC2 8
147 #define MX31_INT_MMC_SDHC1 9
148 #define MX31_INT_I2C1 10
149 #define MX31_INT_SSI2 11
150 #define MX31_INT_SSI1 12
151 #define MX31_INT_CSPI2 13
152 #define MX31_INT_CSPI1 14
153 #define MX31_INT_ATA 15
154 #define MX31_INT_MBX 16
155 #define MX31_INT_CSPI3 17
156 #define MX31_INT_UART3 18
157 #define MX31_INT_IIM 19
158 #define MX31_INT_SIM2 20
159 #define MX31_INT_SIM1 21
160 #define MX31_INT_RNGA 22
161 #define MX31_INT_EVTMON 23
162 #define MX31_INT_KPP 24
163 #define MX31_INT_RTC 25
164 #define MX31_INT_PWM 26
165 #define MX31_INT_EPIT2 27
166 #define MX31_INT_EPIT1 28
167 #define MX31_INT_GPT 29
168 #define MX31_INT_POWER_FAIL 30
169 #define MX31_INT_CCM_DVFS 31
170 #define MX31_INT_UART2 32
171 #define MX31_INT_NANDFC 33
172 #define MX31_INT_SDMA 34
173 #define MX31_INT_USB1 35
174 #define MX31_INT_USB2 36
175 #define MX31_INT_USB3 37
176 #define MX31_INT_USB4 38
177 #define MX31_INT_MSHC1 39
178 #define MX31_INT_MSHC2 40
179 #define MX31_INT_IPU_ERR 41
180 #define MX31_INT_IPU_SYN 42
181 #define MX31_INT_UART1 45
182 #define MX31_INT_UART4 46
183 #define MX31_INT_UART5 47
184 #define MX31_INT_ECT 48
185 #define MX31_INT_SCC_SCM 49
186 #define MX31_INT_SCC_SMN 50
187 #define MX31_INT_GPIO2 51
188 #define MX31_INT_GPIO1 52
189 #define MX31_INT_CCM 53
190 #define MX31_INT_PCMCIA 54
191 #define MX31_INT_WDOG 55
192 #define MX31_INT_GPIO3 56
193 #define MX31_INT_EXT_POWER 58
194 #define MX31_INT_EXT_TEMPER 59
195 #define MX31_INT_EXT_SENSOR60 60
196 #define MX31_INT_EXT_SENSOR61 61
197 #define MX31_INT_EXT_WDOG 62
198 #define MX31_INT_EXT_TV 63
200 #define MX31_PROD_SIGNATURE 0x1 /* For MX31 */
202 /* silicon revisions specific to i.MX31 */
203 #define MX31_CHIP_REV_1_0 0x10
204 #define MX31_CHIP_REV_1_1 0x11
205 #define MX31_CHIP_REV_1_2 0x12
206 #define MX31_CHIP_REV_1_3 0x13
207 #define MX31_CHIP_REV_2_0 0x20
208 #define MX31_CHIP_REV_2_1 0x21
209 #define MX31_CHIP_REV_2_2 0x22
210 #define MX31_CHIP_REV_2_3 0x23
211 #define MX31_CHIP_REV_3_0 0x30
212 #define MX31_CHIP_REV_3_1 0x31
213 #define MX31_CHIP_REV_3_2 0x32
215 #define MX31_SYSTEM_REV_MIN MX31_CHIP_REV_1_0
216 #define MX31_SYSTEM_REV_NUM 3
218 #ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
219 /* these should go away */
220 #define ATA_BASE_ADDR MX31_ATA_BASE_ADDR
221 #define UART4_BASE_ADDR MX31_UART4_BASE_ADDR
222 #define UART5_BASE_ADDR MX31_UART5_BASE_ADDR
223 #define MMC_SDHC1_BASE_ADDR MX31_MMC_SDHC1_BASE_ADDR
224 #define MMC_SDHC2_BASE_ADDR MX31_MMC_SDHC2_BASE_ADDR
225 #define SIM1_BASE_ADDR MX31_SIM1_BASE_ADDR
226 #define IIM_BASE_ADDR MX31_IIM_BASE_ADDR
227 #define CSPI3_BASE_ADDR MX31_CSPI3_BASE_ADDR
228 #define FIRI_BASE_ADDR MX31_FIRI_BASE_ADDR
229 #define SCM_BASE_ADDR MX31_SCM_BASE_ADDR
230 #define SMN_BASE_ADDR MX31_SMN_BASE_ADDR
231 #define MPEG4_ENC_BASE_ADDR MX31_MPEG4_ENC_BASE_ADDR
232 #define MXC_INT_MPEG4_ENCODER MX31_INT_MPEG4_ENCODER
233 #define MXC_INT_FIRI MX31_INT_FIRI
234 #define MXC_INT_MMC_SDHC1 MX31_INT_MMC_SDHC1
235 #define MXC_INT_MBX MX31_INT_MBX
236 #define MXC_INT_CSPI3 MX31_INT_CSPI3
237 #define MXC_INT_SIM2 MX31_INT_SIM2
238 #define MXC_INT_SIM1 MX31_INT_SIM1
239 #define MXC_INT_CCM_DVFS MX31_INT_CCM_DVFS
240 #define MXC_INT_USB1 MX31_INT_USB1
241 #define MXC_INT_USB2 MX31_INT_USB2
242 #define MXC_INT_USB3 MX31_INT_USB3
243 #define MXC_INT_USB4 MX31_INT_USB4
244 #define MXC_INT_MSHC2 MX31_INT_MSHC2
245 #define MXC_INT_UART4 MX31_INT_UART4
246 #define MXC_INT_UART5 MX31_INT_UART5
247 #define MXC_INT_CCM MX31_INT_CCM
248 #define MXC_INT_PCMCIA MX31_INT_PCMCIA
251 #endif /* ifndef __MACH_MX31_H__ */