2 * Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org>
3 * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <mach/hardware.h>
14 #define AVIC_NIMASK 0x04
16 @ this macro disables fast irq (not implemented)
20 .macro get_irqnr_preamble, base, tmp
21 #ifndef CONFIG_MXC_TZIC
24 #ifdef CONFIG_MXC_IRQ_PRIOR
25 ldr r4, [\base, #AVIC_NIMASK]
27 #elif defined CONFIG_MXC_TZIC
30 #endif /* CONFIG_MXC_TZIC */
33 .macro arch_ret_to_user, tmp1, tmp2
36 @ this macro checks which interrupt occured
37 @ and returns its number in irqnr
38 @ and returns if an interrupt occured in irqstat
39 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
40 #ifndef CONFIG_MXC_TZIC
41 @ Load offset & priority of the highest priority
42 @ interrupt pending from AVIC_NIVECSR
43 ldr \irqstat, [\base, #0x40]
44 @ Shift to get the decoded IRQ number, using ASR so
45 @ 'no interrupt pending' becomes 0xffffffff
46 mov \irqnr, \irqstat, asr #16
47 @ set zero flag if IRQ + 1 == 0
49 #ifdef CONFIG_MXC_IRQ_PRIOR
50 bicne \tmp, \irqstat, #0xFFFFFFE0
51 strne \tmp, [\base, #AVIC_NIMASK]
52 streq r4, [\base, #AVIC_NIMASK]
54 #elif defined CONFIG_MXC_TZIC
55 @ Load offset & priority of the highest priority
57 @ 0xD80 is HIPND0 register
61 ldr \tmp, [\irqstat, \base]
64 addeq \irqnr, \irqnr, #32
65 addeq \irqstat, \irqstat, #4
69 1001: mov \irqstat, #1
70 1002: tst \tmp, \irqstat
72 movs \tmp, \tmp, lsr #1
73 addne \irqnr, \irqnr, #1
82 @ irq priority table (not used)