2 * platform device definitions for the iop3xx dma/xor engines
3 * Copyright © 2006, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 #include <linux/platform_device.h>
20 #include <asm/hardware/iop3xx.h>
21 #include <linux/dma-mapping.h>
22 #include <mach/adma.h>
23 #include <asm/hardware/iop_adma.h>
25 #ifdef CONFIG_ARCH_IOP32X
26 #define IRQ_DMA0_EOT IRQ_IOP32X_DMA0_EOT
27 #define IRQ_DMA0_EOC IRQ_IOP32X_DMA0_EOC
28 #define IRQ_DMA0_ERR IRQ_IOP32X_DMA0_ERR
30 #define IRQ_DMA1_EOT IRQ_IOP32X_DMA1_EOT
31 #define IRQ_DMA1_EOC IRQ_IOP32X_DMA1_EOC
32 #define IRQ_DMA1_ERR IRQ_IOP32X_DMA1_ERR
34 #define IRQ_AA_EOT IRQ_IOP32X_AA_EOT
35 #define IRQ_AA_EOC IRQ_IOP32X_AA_EOC
36 #define IRQ_AA_ERR IRQ_IOP32X_AA_ERR
38 #ifdef CONFIG_ARCH_IOP33X
39 #define IRQ_DMA0_EOT IRQ_IOP33X_DMA0_EOT
40 #define IRQ_DMA0_EOC IRQ_IOP33X_DMA0_EOC
41 #define IRQ_DMA0_ERR IRQ_IOP33X_DMA0_ERR
43 #define IRQ_DMA1_EOT IRQ_IOP33X_DMA1_EOT
44 #define IRQ_DMA1_EOC IRQ_IOP33X_DMA1_EOC
45 #define IRQ_DMA1_ERR IRQ_IOP33X_DMA1_ERR
47 #define IRQ_AA_EOT IRQ_IOP33X_AA_EOT
48 #define IRQ_AA_EOC IRQ_IOP33X_AA_EOC
49 #define IRQ_AA_ERR IRQ_IOP33X_AA_ERR
51 /* AAU and DMA Channels */
52 static struct resource iop3xx_dma_0_resources[] = {
54 .start = IOP3XX_DMA_PHYS_BASE(0),
55 .end = IOP3XX_DMA_UPPER_PA(0),
56 .flags = IORESOURCE_MEM,
59 .start = IRQ_DMA0_EOT,
61 .flags = IORESOURCE_IRQ
64 .start = IRQ_DMA0_EOC,
66 .flags = IORESOURCE_IRQ
69 .start = IRQ_DMA0_ERR,
71 .flags = IORESOURCE_IRQ
75 static struct resource iop3xx_dma_1_resources[] = {
77 .start = IOP3XX_DMA_PHYS_BASE(1),
78 .end = IOP3XX_DMA_UPPER_PA(1),
79 .flags = IORESOURCE_MEM,
82 .start = IRQ_DMA1_EOT,
84 .flags = IORESOURCE_IRQ
87 .start = IRQ_DMA1_EOC,
89 .flags = IORESOURCE_IRQ
92 .start = IRQ_DMA1_ERR,
94 .flags = IORESOURCE_IRQ
99 static struct resource iop3xx_aau_resources[] = {
101 .start = IOP3XX_AAU_PHYS_BASE,
102 .end = IOP3XX_AAU_UPPER_PA,
103 .flags = IORESOURCE_MEM,
108 .flags = IORESOURCE_IRQ
113 .flags = IORESOURCE_IRQ
118 .flags = IORESOURCE_IRQ
122 static u64 iop3xx_adma_dmamask = DMA_BIT_MASK(32);
124 static struct iop_adma_platform_data iop3xx_dma_0_data = {
126 .pool_size = PAGE_SIZE,
129 static struct iop_adma_platform_data iop3xx_dma_1_data = {
131 .pool_size = PAGE_SIZE,
134 static struct iop_adma_platform_data iop3xx_aau_data = {
136 .pool_size = 3 * PAGE_SIZE,
139 struct platform_device iop3xx_dma_0_channel = {
143 .resource = iop3xx_dma_0_resources,
145 .dma_mask = &iop3xx_adma_dmamask,
146 .coherent_dma_mask = DMA_BIT_MASK(64),
147 .platform_data = (void *) &iop3xx_dma_0_data,
151 struct platform_device iop3xx_dma_1_channel = {
155 .resource = iop3xx_dma_1_resources,
157 .dma_mask = &iop3xx_adma_dmamask,
158 .coherent_dma_mask = DMA_BIT_MASK(64),
159 .platform_data = (void *) &iop3xx_dma_1_data,
163 struct platform_device iop3xx_aau_channel = {
167 .resource = iop3xx_aau_resources,
169 .dma_mask = &iop3xx_adma_dmamask,
170 .coherent_dma_mask = DMA_BIT_MASK(64),
171 .platform_data = (void *) &iop3xx_aau_data,
175 static int __init iop3xx_adma_cap_init(void)
177 #ifdef CONFIG_ARCH_IOP32X /* the 32x DMA does not perform CRC32C */
178 dma_cap_set(DMA_MEMCPY, iop3xx_dma_0_data.cap_mask);
179 dma_cap_set(DMA_INTERRUPT, iop3xx_dma_0_data.cap_mask);
181 dma_cap_set(DMA_MEMCPY, iop3xx_dma_0_data.cap_mask);
182 dma_cap_set(DMA_INTERRUPT, iop3xx_dma_0_data.cap_mask);
185 #ifdef CONFIG_ARCH_IOP32X /* the 32x DMA does not perform CRC32C */
186 dma_cap_set(DMA_MEMCPY, iop3xx_dma_1_data.cap_mask);
187 dma_cap_set(DMA_INTERRUPT, iop3xx_dma_1_data.cap_mask);
189 dma_cap_set(DMA_MEMCPY, iop3xx_dma_1_data.cap_mask);
190 dma_cap_set(DMA_INTERRUPT, iop3xx_dma_1_data.cap_mask);
193 #ifdef CONFIG_ARCH_IOP32X /* the 32x AAU does not perform zero sum */
194 dma_cap_set(DMA_XOR, iop3xx_aau_data.cap_mask);
195 dma_cap_set(DMA_MEMSET, iop3xx_aau_data.cap_mask);
196 dma_cap_set(DMA_INTERRUPT, iop3xx_aau_data.cap_mask);
198 dma_cap_set(DMA_XOR, iop3xx_aau_data.cap_mask);
199 dma_cap_set(DMA_XOR_VAL, iop3xx_aau_data.cap_mask);
200 dma_cap_set(DMA_MEMSET, iop3xx_aau_data.cap_mask);
201 dma_cap_set(DMA_INTERRUPT, iop3xx_aau_data.cap_mask);
207 arch_initcall(iop3xx_adma_cap_init);