2 * linux/arch/arm/mm/proc-v7.S
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This is the "shell" of the ARMv7 processor support.
12 #include <linux/init.h>
13 #include <linux/linkage.h>
14 #include <asm/assembler.h>
15 #include <asm/asm-offsets.h>
16 #include <asm/hwcap.h>
17 #include <asm/pgtable-hwdef.h>
18 #include <asm/pgtable.h>
20 #include "proc-macros.S"
22 #define TTB_S (1 << 1)
23 #define TTB_RGN_NC (0 << 3)
24 #define TTB_RGN_OC_WBWA (1 << 3)
25 #define TTB_RGN_OC_WT (2 << 3)
26 #define TTB_RGN_OC_WB (3 << 3)
27 #define TTB_NOS (1 << 5)
28 #define TTB_IRGN_NC ((0 << 0) | (0 << 6))
29 #define TTB_IRGN_WBWA ((0 << 0) | (1 << 6))
30 #define TTB_IRGN_WT ((1 << 0) | (0 << 6))
31 #define TTB_IRGN_WB ((1 << 0) | (1 << 6))
34 /* PTWs cacheable, inner WB not shareable, outer WB not shareable */
35 #define TTB_FLAGS TTB_IRGN_WB|TTB_RGN_OC_WB
37 /* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
38 #define TTB_FLAGS TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
41 ENTRY(cpu_v7_proc_init)
43 ENDPROC(cpu_v7_proc_init)
45 ENTRY(cpu_v7_proc_fin)
47 ENDPROC(cpu_v7_proc_fin)
52 * Perform a soft reset of the system. Put the CPU into the
53 * same state as it would be if it had been reset, and branch
54 * to what would be the reset vector.
56 * - loc - location to jump to for soft reset
68 * Idle the processor (eg, wait for interrupt).
70 * IRQs are already disabled.
73 dsb @ WFI may enter a low-power mode
76 ENDPROC(cpu_v7_do_idle)
78 ENTRY(cpu_v7_dcache_clean_area)
79 #ifndef TLB_CAN_READ_FROM_L1_CACHE
80 dcache_line_size r2, r3
81 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
88 ENDPROC(cpu_v7_dcache_clean_area)
91 * cpu_v7_switch_mm(pgd_phys, tsk)
93 * Set the translation table base pointer to be pgd_phys
95 * - pgd_phys - physical address of new TTB
98 * - we are not using split page tables
100 ENTRY(cpu_v7_switch_mm)
103 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
104 orr r0, r0, #TTB_FLAGS
105 #ifdef CONFIG_ARM_ERRATA_430973
106 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
108 mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID
110 1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
112 mcr p15, 0, r1, c13, c0, 1 @ set context ID
116 ENDPROC(cpu_v7_switch_mm)
119 * cpu_v7_set_pte_ext(ptep, pte)
121 * Set a level 2 translation table entry.
123 * - ptep - pointer to level 2 translation table entry
124 * (hardware version is stored at -1024 bytes)
125 * - pte - PTE value to store
126 * - ext - value for extended PTE bits
128 ENTRY(cpu_v7_set_pte_ext)
130 str r1, [r0], #-2048 @ linux version
132 bic r3, r1, #0x000003f0
133 bic r3, r3, #PTE_TYPE_MASK
135 orr r3, r3, #PTE_EXT_AP0 | 2
138 orrne r3, r3, #PTE_EXT_TEX(1)
141 tstne r1, #L_PTE_DIRTY
142 orreq r3, r3, #PTE_EXT_APX
145 orrne r3, r3, #PTE_EXT_AP1
146 tstne r3, #PTE_EXT_APX
147 bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
150 orreq r3, r3, #PTE_EXT_XN
153 tstne r1, #L_PTE_PRESENT
157 mcr p15, 0, r0, c7, c10, 1 @ flush_pte
160 ENDPROC(cpu_v7_set_pte_ext)
163 .ascii "ARMv7 Processor"
171 * Initialise TLB, Caches, and MMU state ready to switch the MMU
172 * on. Return in r0 the new CP15 C1 control register setting.
174 * We automatically detect if we have a Harvard cache, and use the
175 * Harvard cache control instructions insead of the unified cache
176 * control instructions.
178 * This should be able to cover all ARMv7 cores.
180 * It is assumed that:
181 * - cache type register is implemented
185 mrc p15, 0, r0, c1, c0, 1 @ Enable SMP/nAMP mode and
186 orr r0, r0, #(1 << 6) | (1 << 0) @ TLB ops broadcasting
187 mcr p15, 0, r0, c1, c0, 1
189 adr r12, __v7_setup_stack @ the local stack
190 stmia r12, {r0-r5, r7, r9, r11, lr}
191 bl v7_flush_dcache_all
192 ldmia r12, {r0-r5, r7, r9, r11, lr}
193 #ifdef CONFIG_ARM_ERRATA_430973
194 mrc p15, 0, r10, c1, c0, 1 @ read aux control register
195 orr r10, r10, #(1 << 6) @ set IBE to 1
196 mcr p15, 0, r10, c1, c0, 1 @ write aux control register
198 #ifdef CONFIG_ARM_ERRATA_458693
199 mrc p15, 0, r10, c1, c0, 1 @ read aux control register
200 orr r10, r10, #(1 << 5) @ set L1NEON to 1
201 orr r10, r10, #(1 << 9) @ set PLDNOP to 1
202 mcr p15, 0, r10, c1, c0, 1 @ write aux control register
204 #ifdef CONFIG_ARM_ERRATA_460075
205 mrc p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register
206 orr r10, r10, #(1 << 22) @ set the Write Allocate disable bit
207 mcr p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register
211 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
215 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
216 mcr p15, 0, r10, c2, c0, 2 @ TTB control register
217 orr r4, r4, #TTB_FLAGS
218 mcr p15, 0, r4, c2, c0, 1 @ load TTB1
219 mov r10, #0x1f @ domains 0, 1 = manager
220 mcr p15, 0, r10, c3, c0, 0 @ load domain access register
223 * Memory region attributes with SCTLR.TRE=1
226 * TR = PRRR[2n+1:2n] - memory type
227 * IR = NMRR[2n+1:2n] - inner cacheable property
228 * OR = NMRR[2n+17:2n+16] - outer cacheable property
232 * BUFFERABLE 001 10 00 00
233 * WRITETHROUGH 010 10 10 10
234 * WRITEBACK 011 10 11 11
236 * WRITEALLOC 111 10 01 01
238 * DEV_NONSHARED 100 01
244 * DS0 = PRRR[16] = 0 - device shareable property
245 * DS1 = PRRR[17] = 1 - device shareable property
246 * NS0 = PRRR[18] = 0 - normal shareable property
247 * NS1 = PRRR[19] = 1 - normal shareable property
248 * NOS = PRRR[24+n] = 1 - not outer shareable
250 ldr r5, =0xff0a81a8 @ PRRR
251 ldr r6, =0x40e040e0 @ NMRR
252 mcr p15, 0, r5, c10, c2, 0 @ write PRRR
253 mcr p15, 0, r6, c10, c2, 1 @ write NMRR
256 #ifdef CONFIG_CPU_ENDIAN_BE8
257 orr r6, r6, #1 << 25 @ big-endian page tables
259 mrc p15, 0, r0, c1, c0, 0 @ read control register
260 bic r0, r0, r5 @ clear bits them
261 orr r0, r0, r6 @ set them
262 mov pc, lr @ return to head.S:__ret
266 * TFR EV X F I D LR S
267 * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM
268 * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
269 * 1 0 110 0011 1100 .111 1101 < we want
271 .type v7_crval, #object
273 crval clear=0x0120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c
276 .space 4 * 11 @ 11 registers
278 .type v7_processor_functions, #object
279 ENTRY(v7_processor_functions)
282 .word cpu_v7_proc_init
283 .word cpu_v7_proc_fin
286 .word cpu_v7_dcache_clean_area
287 .word cpu_v7_switch_mm
288 .word cpu_v7_set_pte_ext
289 .size v7_processor_functions, . - v7_processor_functions
291 .type cpu_arch_name, #object
294 .size cpu_arch_name, . - cpu_arch_name
296 .type cpu_elf_name, #object
299 .size cpu_elf_name, . - cpu_elf_name
302 .section ".proc.info.init", #alloc, #execinstr
305 * Match any ARMv7 processor core.
307 .type __v7_proc_info, #object
309 .long 0x000f0000 @ Required ID value
310 .long 0x000f0000 @ Mask for ID
311 .long PMD_TYPE_SECT | \
312 PMD_SECT_BUFFERABLE | \
313 PMD_SECT_CACHEABLE | \
314 PMD_SECT_AP_WRITE | \
316 .long PMD_TYPE_SECT | \
318 PMD_SECT_AP_WRITE | \
323 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
325 .long v7_processor_functions
329 .size __v7_proc_info, . - __v7_proc_info