2 * linux/arch/arm/mm/proc-v6.S
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
5 * Modified by Catalin Marinas for noMMU support
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This is the "shell" of the ARMv6 processor support.
13 #include <linux/init.h>
14 #include <linux/linkage.h>
15 #include <asm/assembler.h>
16 #include <asm/asm-offsets.h>
17 #include <asm/hwcap.h>
18 #include <asm/pgtable-hwdef.h>
19 #include <asm/pgtable.h>
21 #include "proc-macros.S"
23 #define D_CACHE_LINE_SIZE 32
25 #define TTB_C (1 << 0)
26 #define TTB_S (1 << 1)
27 #define TTB_IMP (1 << 2)
28 #define TTB_RGN_NC (0 << 3)
29 #define TTB_RGN_WBWA (1 << 3)
30 #define TTB_RGN_WT (2 << 3)
31 #define TTB_RGN_WB (3 << 3)
33 #define TTB_FLAGS_UP TTB_RGN_WBWA
34 #define PMD_FLAGS_UP PMD_SECT_WB
35 #define TTB_FLAGS_SMP TTB_RGN_WBWA|TTB_S
36 #define PMD_FLAGS_SMP PMD_SECT_WBWA|PMD_SECT_S
38 ENTRY(cpu_v6_proc_init)
41 ENTRY(cpu_v6_proc_fin)
42 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
43 bic r0, r0, #0x1000 @ ...i............
44 bic r0, r0, #0x0006 @ .............ca.
45 mcr p15, 0, r0, c1, c0, 0 @ disable caches
51 * Perform a soft reset of the system. Put the CPU into the
52 * same state as it would be if it had been reset, and branch
53 * to what would be the reset vector.
55 * - loc - location to jump to for soft reset
64 * Idle the processor (eg, wait for interrupt).
66 * IRQs are already disabled.
70 mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode
71 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
74 ENTRY(cpu_v6_dcache_clean_area)
75 #ifndef TLB_CAN_READ_FROM_L1_CACHE
76 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
77 add r0, r0, #D_CACHE_LINE_SIZE
78 subs r1, r1, #D_CACHE_LINE_SIZE
84 * cpu_arm926_switch_mm(pgd_phys, tsk)
86 * Set the translation table base pointer to be pgd_phys
88 * - pgd_phys - physical address of new TTB
91 * - we are not using split page tables
93 ENTRY(cpu_v6_switch_mm)
96 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
97 ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP)
98 ALT_UP(orr r0, r0, #TTB_FLAGS_UP)
99 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
100 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
101 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
102 mcr p15, 0, r1, c13, c0, 1 @ set context ID
107 * cpu_v6_set_pte_ext(ptep, pte, ext)
109 * Set a level 2 translation table entry.
111 * - ptep - pointer to level 2 translation table entry
112 * (hardware version is stored at -1024 bytes)
113 * - pte - PTE value to store
114 * - ext - value for extended PTE bits
116 armv6_mt_table cpu_v6
118 ENTRY(cpu_v6_set_pte_ext)
120 armv6_set_pte_ext cpu_v6
126 .type cpu_v6_name, #object
128 .asciz "ARMv6-compatible processor"
129 .size cpu_v6_name, . - cpu_v6_name
131 .type cpu_pj4_name, #object
133 .asciz "Marvell PJ4 processor"
134 .size cpu_pj4_name, . - cpu_pj4_name
143 * Initialise TLB, Caches, and MMU state ready to switch the MMU
144 * on. Return in r0 the new CP15 C1 control register setting.
146 * We automatically detect if we have a Harvard cache, and use the
147 * Harvard cache control instructions insead of the unified cache
148 * control instructions.
150 * This should be able to cover all ARMv6 cores.
152 * It is assumed that:
153 * - cache type register is implemented
157 ALT_SMP(mrc p15, 0, r0, c1, c0, 1) @ Enable SMP/nAMP mode
160 ALT_SMP(mcr p15, 0, r0, c1, c0, 1)
165 mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache
166 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
167 mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache
168 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
170 mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
171 mcr p15, 0, r0, c2, c0, 2 @ TTB control register
172 ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP)
173 ALT_UP(orr r4, r4, #TTB_FLAGS_UP)
174 mcr p15, 0, r4, c2, c0, 1 @ load TTB1
175 #endif /* CONFIG_MMU */
178 #ifdef CONFIG_CPU_ENDIAN_BE8
179 orr r6, r6, #1 << 25 @ big-endian page tables
181 mrc p15, 0, r0, c1, c0, 0 @ read control register
182 bic r0, r0, r5 @ clear bits them
183 orr r0, r0, r6 @ set them
184 mov pc, lr @ return to head.S:__ret
188 * .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM
189 * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
190 * 0 110 0011 1.00 .111 1101 < we want
192 .type v6_crval, #object
194 crval clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c
198 .type v6_processor_functions, #object
199 ENTRY(v6_processor_functions)
202 .word cpu_v6_proc_init
203 .word cpu_v6_proc_fin
206 .word cpu_v6_dcache_clean_area
207 .word cpu_v6_switch_mm
208 .word cpu_v6_set_pte_ext
209 .size v6_processor_functions, . - v6_processor_functions
213 .type cpu_arch_name, #object
216 .size cpu_arch_name, . - cpu_arch_name
218 .type cpu_elf_name, #object
221 .size cpu_elf_name, . - cpu_elf_name
224 .section ".proc.info.init", #alloc, #execinstr
227 * Match any ARMv6 processor core.
229 .type __v6_proc_info, #object
235 PMD_SECT_AP_WRITE | \
240 PMD_SECT_AP_WRITE | \
243 .long PMD_TYPE_SECT | \
245 PMD_SECT_AP_WRITE | \
250 /* See also feat_v6_fixup() for HWCAP_TLS */
251 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA|HWCAP_TLS
253 .long v6_processor_functions
257 .size __v6_proc_info, . - __v6_proc_info
259 .type __pj4_v6_proc_info, #object
265 PMD_SECT_AP_WRITE | \
270 PMD_SECT_AP_WRITE | \
273 .long PMD_TYPE_SECT | \
275 PMD_SECT_AP_WRITE | \
280 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
282 .long v6_processor_functions
286 .size __pj4_v6_proc_info, . - __pj4_v6_proc_info