2 * linux/arch/arm/mm/proc-sa1100.S
4 * Copyright (C) 1997-2002 Russell King
5 * hacked for non-paged-MM by Hyok S. Choi, 2003.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * MMU functions for SA110
13 * These are the low level assembler for performing cache and TLB
14 * functions on the StrongARM-1100 and StrongARM-1110.
16 * Note that SA1100 and SA1110 share everything but their name and CPU ID.
18 * 12-jun-2000, Erik Mouw (J.A.K.Mouw@its.tudelft.nl):
19 * Flush the read buffer at context switches
21 #include <linux/linkage.h>
22 #include <linux/init.h>
23 #include <asm/assembler.h>
24 #include <asm/asm-offsets.h>
25 #include <asm/hwcap.h>
26 #include <mach/hardware.h>
27 #include <asm/pgtable-hwdef.h>
28 #include <asm/pgtable.h>
30 #include "proc-macros.S"
33 * the cache line size of the I and D cache
35 #define DCACHELINESIZE 32
40 * cpu_sa1100_proc_init()
42 ENTRY(cpu_sa1100_proc_init)
44 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
45 mcr p15, 0, r0, c9, c0, 5 @ Allow read-buffer operations from userland
49 * cpu_sa1100_proc_fin()
51 * Prepare the CPU for reset:
52 * - Disable interrupts
53 * - Clean and turn off caches.
55 ENTRY(cpu_sa1100_proc_fin)
56 mcr p15, 0, ip, c15, c2, 2 @ Disable clock switching
57 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
58 bic r0, r0, #0x1000 @ ...i............
59 bic r0, r0, #0x000e @ ............wca.
60 mcr p15, 0, r0, c1, c0, 0 @ disable caches
64 * cpu_sa1100_reset(loc)
66 * Perform a soft reset of the system. Put the CPU into the
67 * same state as it would be if it had been reset, and branch
68 * to what would be the reset vector.
70 * loc: location to jump to for soft reset
73 .pushsection .idmap.text, "ax"
74 ENTRY(cpu_sa1100_reset)
76 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
77 mcr p15, 0, ip, c7, c10, 4 @ drain WB
79 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
81 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
82 bic ip, ip, #0x000f @ ............wcam
83 bic ip, ip, #0x1100 @ ...i...s........
84 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
86 ENDPROC(cpu_sa1100_reset)
90 * cpu_sa1100_do_idle(type)
92 * Cause the processor to idle
97 * 2 = switch to slow processor clock
98 * 3 = switch to fast processor clock
101 ENTRY(cpu_sa1100_do_idle)
102 mov r0, r0 @ 4 nop padding
105 mov r0, r0 @ 4 nop padding
109 ldr r1, =UNCACHEABLE_ADDR @ ptr to uncacheable address
110 @ --- aligned to a cache line
111 mcr p15, 0, r0, c15, c2, 2 @ disable clock switching
112 ldr r1, [r1, #0] @ force switch to MCLK
113 mcr p15, 0, r0, c15, c8, 2 @ wait for interrupt
115 mcr p15, 0, r0, c15, c1, 2 @ enable clock switching
118 /* ================================= CACHE ================================ */
121 * cpu_sa1100_dcache_clean_area(addr,sz)
123 * Clean the specified entry of any caches such that the MMU
124 * translation fetches will obtain correct data.
126 * addr: cache-unaligned virtual address
129 ENTRY(cpu_sa1100_dcache_clean_area)
130 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
131 add r0, r0, #DCACHELINESIZE
132 subs r1, r1, #DCACHELINESIZE
136 /* =============================== PageTable ============================== */
139 * cpu_sa1100_switch_mm(pgd)
141 * Set the translation base pointer to be as described by pgd.
143 * pgd: new page tables
146 ENTRY(cpu_sa1100_switch_mm)
149 bl v4wb_flush_kern_cache_all @ clears IP
150 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB
151 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
152 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
159 * cpu_sa1100_set_pte_ext(ptep, pte, ext)
161 * Set a PTE and flush it out
164 ENTRY(cpu_sa1100_set_pte_ext)
166 armv3_set_pte_ext wc_disable=0
168 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
169 mcr p15, 0, r0, c7, c10, 4 @ drain WB
173 .globl cpu_sa1100_suspend_size
174 .equ cpu_sa1100_suspend_size, 4 * 3
175 #ifdef CONFIG_ARM_CPU_SUSPEND
176 ENTRY(cpu_sa1100_do_suspend)
177 stmfd sp!, {r4 - r6, lr}
178 mrc p15, 0, r4, c3, c0, 0 @ domain ID
179 mrc p15, 0, r5, c13, c0, 0 @ PID
180 mrc p15, 0, r6, c1, c0, 0 @ control reg
181 stmia r0, {r4 - r6} @ store cp regs
182 ldmfd sp!, {r4 - r6, pc}
183 ENDPROC(cpu_sa1100_do_suspend)
185 ENTRY(cpu_sa1100_do_resume)
186 ldmia r0, {r4 - r6} @ load cp regs
188 mcr p15, 0, ip, c8, c7, 0 @ flush I+D TLBs
189 mcr p15, 0, ip, c7, c7, 0 @ flush I&D cache
190 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB
191 mcr p15, 0, ip, c9, c0, 5 @ allow user space to use RB
193 mcr p15, 0, r4, c3, c0, 0 @ domain ID
194 mcr p15, 0, r1, c2, c0, 0 @ translation table base addr
195 mcr p15, 0, r5, c13, c0, 0 @ PID
196 mov r0, r6 @ control register
198 ENDPROC(cpu_sa1100_do_resume)
203 .type __sa1100_setup, #function
206 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
207 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
209 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
213 mrc p15, 0, r0, c1, c0 @ get control register v4
217 .size __sa1100_setup, . - __sa1100_setup
221 * .RVI ZFRS BLDP WCAM
222 * ..11 0001 ..11 1101
225 .type sa1100_crval, #object
227 crval clear=0x00003f3f, mmuset=0x0000313d, ucset=0x00001130
232 * SA1100 and SA1110 share the same function calls
235 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
236 define_processor_functions sa1100, dabort=v4_early_abort, pabort=legacy_pabort, suspend=1
240 string cpu_arch_name, "armv4"
241 string cpu_elf_name, "v4"
242 string cpu_sa1100_name, "StrongARM-1100"
243 string cpu_sa1110_name, "StrongARM-1110"
247 .section ".proc.info.init", #alloc, #execinstr
249 .macro sa1100_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req
250 .type __\name\()_proc_info,#object
251 __\name\()_proc_info:
254 .long PMD_TYPE_SECT | \
255 PMD_SECT_BUFFERABLE | \
256 PMD_SECT_CACHEABLE | \
257 PMD_SECT_AP_WRITE | \
259 .long PMD_TYPE_SECT | \
260 PMD_SECT_AP_WRITE | \
265 .long HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT | HWCAP_FAST_MULT
267 .long sa1100_processor_functions
271 .size __\name\()_proc_info, . - __\name\()_proc_info
274 sa1100_proc_info sa1100, 0x4401a110, 0xfffffff0, cpu_sa1100_name
275 sa1100_proc_info sa1110, 0x6901b110, 0xfffffff0, cpu_sa1110_name