2 * linux/arch/arm/mm/proc-sa1100.S
4 * Copyright (C) 1997-2002 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * MMU functions for SA110
12 * These are the low level assembler for performing cache and TLB
13 * functions on the StrongARM-1100 and StrongARM-1110.
15 * Note that SA1100 and SA1110 share everything but their name and CPU ID.
17 * 12-jun-2000, Erik Mouw (J.A.K.Mouw@its.tudelft.nl):
18 * Flush the read buffer at context switches
20 #include <linux/linkage.h>
21 #include <linux/init.h>
22 #include <asm/assembler.h>
23 #include <asm/asm-offsets.h>
24 #include <asm/procinfo.h>
25 #include <asm/hardware.h>
26 #include <asm/pgtable-hwdef.h>
27 #include <asm/pgtable.h>
30 * the cache line size of the I and D cache
32 #define DCACHELINESIZE 32
33 #define FLUSH_OFFSET 32768
35 .macro flush_1100_dcache rd, ra, re
38 eor \ra, \ra, #FLUSH_OFFSET
40 add \re, \ra, #8192 @ only necessary for 8k
41 1001: ldr \rd, [\ra], #DCACHELINESIZE
44 #ifdef FLUSH_BASE_MINICACHE
45 add \ra, \ra, #FLUSH_BASE_MINICACHE - FLUSH_BASE
46 add \re, \ra, #512 @ only 512 bytes
47 1002: ldr \rd, [\ra], #DCACHELINESIZE
61 * cpu_sa1100_proc_init()
63 ENTRY(cpu_sa1100_proc_init)
65 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
66 mcr p15, 0, r0, c9, c0, 5 @ Allow read-buffer operations from userland
72 * cpu_sa1100_proc_fin()
74 * Prepare the CPU for reset:
75 * - Disable interrupts
76 * - Clean and turn off caches.
78 ENTRY(cpu_sa1100_proc_fin)
80 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
82 flush_1100_dcache r0, r1, r2 @ clean caches
84 mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching
85 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
86 bic r0, r0, #0x1000 @ ...i............
87 bic r0, r0, #0x000e @ ............wca.
88 mcr p15, 0, r0, c1, c0, 0 @ disable caches
92 * cpu_sa1100_reset(loc)
94 * Perform a soft reset of the system. Put the CPU into the
95 * same state as it would be if it had been reset, and branch
96 * to what would be the reset vector.
98 * loc: location to jump to for soft reset
101 ENTRY(cpu_sa1100_reset)
103 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
104 mcr p15, 0, ip, c7, c10, 4 @ drain WB
105 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
106 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
107 bic ip, ip, #0x000f @ ............wcam
108 bic ip, ip, #0x1100 @ ...i...s........
109 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
113 * cpu_sa1100_do_idle(type)
115 * Cause the processor to idle
120 * 2 = switch to slow processor clock
121 * 3 = switch to fast processor clock
124 ENTRY(cpu_sa1100_do_idle)
125 mov r0, r0 @ 4 nop padding
128 mov r0, r0 @ 4 nop padding
132 ldr r1, =UNCACHEABLE_ADDR @ ptr to uncacheable address
133 @ --- aligned to a cache line
134 mcr p15, 0, r0, c15, c2, 2 @ disable clock switching
135 ldr r1, [r1, #0] @ force switch to MCLK
136 mcr p15, 0, r0, c15, c8, 2 @ wait for interrupt
138 mcr p15, 0, r0, c15, c1, 2 @ enable clock switching
141 /* ================================= CACHE ================================ */
144 * cpu_sa1100_dcache_clean_area(addr,sz)
146 * Clean the specified entry of any caches such that the MMU
147 * translation fetches will obtain correct data.
149 * addr: cache-unaligned virtual address
152 ENTRY(cpu_sa1100_dcache_clean_area)
153 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
154 add r0, r0, #DCACHELINESIZE
155 subs r1, r1, #DCACHELINESIZE
159 /* =============================== PageTable ============================== */
162 * cpu_sa1100_switch_mm(pgd)
164 * Set the translation base pointer to be as described by pgd.
166 * pgd: new page tables
169 ENTRY(cpu_sa1100_switch_mm)
170 flush_1100_dcache r3, ip, r1
172 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
173 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB
174 mcr p15, 0, ip, c7, c10, 4 @ drain WB
175 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
176 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
180 * cpu_sa1100_set_pte(ptep, pte)
182 * Set a PTE and flush it out
185 ENTRY(cpu_sa1100_set_pte)
186 str r1, [r0], #-2048 @ linux version
188 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
190 bic r2, r1, #PTE_SMALL_AP_MASK
191 bic r2, r2, #PTE_TYPE_MASK
192 orr r2, r2, #PTE_TYPE_SMALL
194 tst r1, #L_PTE_USER @ User?
195 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
197 tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
198 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
200 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
203 str r2, [r0] @ hardware version
205 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
206 mcr p15, 0, r0, c7, c10, 4 @ drain WB
211 .type __sa1100_setup, #function
214 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
215 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
216 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
217 mrc p15, 0, r0, c1, c0 @ get control register v4
218 ldr r5, sa1100_cr1_clear
220 ldr r5, sa1100_cr1_set
223 .size __sa1100_setup, . - __sa1100_setup
227 * .RVI ZFRS BLDP WCAM
228 * ..11 0001 ..11 1101
231 .type sa1100_cr1_clear, #object
232 .type sa1100_cr1_set, #object
241 * Purpose : Function pointers used to access above functions - all calls
246 * SA1100 and SA1110 share the same function calls
248 .type sa1100_processor_functions, #object
249 ENTRY(sa1100_processor_functions)
251 .word cpu_sa1100_proc_init
252 .word cpu_sa1100_proc_fin
253 .word cpu_sa1100_reset
254 .word cpu_sa1100_do_idle
255 .word cpu_sa1100_dcache_clean_area
256 .word cpu_sa1100_switch_mm
257 .word cpu_sa1100_set_pte
258 .size sa1100_processor_functions, . - sa1100_processor_functions
262 .type cpu_arch_name, #object
265 .size cpu_arch_name, . - cpu_arch_name
267 .type cpu_elf_name, #object
270 .size cpu_elf_name, . - cpu_elf_name
272 .type cpu_sa1100_name, #object
274 .asciz "StrongARM-1100"
275 .size cpu_sa1100_name, . - cpu_sa1100_name
277 .type cpu_sa1110_name, #object
279 .asciz "StrongARM-1110"
280 .size cpu_sa1110_name, . - cpu_sa1110_name
284 .section ".proc.info.init", #alloc, #execinstr
286 .type __sa1100_proc_info,#object
290 .long PMD_TYPE_SECT | \
291 PMD_SECT_BUFFERABLE | \
292 PMD_SECT_CACHEABLE | \
293 PMD_SECT_AP_WRITE | \
298 .long HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT | HWCAP_FAST_MULT
299 .long cpu_sa1100_name
300 .long sa1100_processor_functions
304 .size __sa1100_proc_info, . - __sa1100_proc_info
306 .type __sa1110_proc_info,#object
310 .long PMD_TYPE_SECT | \
311 PMD_SECT_BUFFERABLE | \
312 PMD_SECT_CACHEABLE | \
313 PMD_SECT_AP_WRITE | \
318 .long HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT | HWCAP_FAST_MULT
319 .long cpu_sa1110_name
320 .long sa1100_processor_functions
324 .size __sa1110_proc_info, . - __sa1110_proc_info