2 * We need constants.h for:
7 #include <asm/asm-offsets.h>
8 #include <asm/thread_info.h>
11 * vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm)
13 .macro vma_vm_mm, rd, rn
14 ldr \rd, [\rn, #VMA_VM_MM]
18 * vma_vm_flags - get vma->vm_flags
20 .macro vma_vm_flags, rd, rn
21 ldr \rd, [\rn, #VMA_VM_FLAGS]
25 ldr \rd, [\rn, #TI_TASK]
26 ldr \rd, [\rd, #TSK_ACTIVE_MM]
30 * act_mm - get current->active_mm
35 ldr \rd, [\rd, #TI_TASK]
36 ldr \rd, [\rd, #TSK_ACTIVE_MM]
40 * mmid - get context id from mm pointer (mm->context.id)
43 ldr \rd, [\rn, #MM_CONTEXT_ID]
47 * mask_asid - mask the ASID from the context ID
53 .macro crval, clear, mmuset, ucset
64 * cache_line_size - get the cache line size from the CSIDR register
65 * (available on ARMv7+). It assumes that the CSSR register was configured
66 * to access the L1 data cache CSIDR.
68 .macro dcache_line_size, reg, tmp
69 mrc p15, 1, \tmp, c0, c0, 0 @ read CSIDR
70 and \tmp, \tmp, #7 @ cache line size encoding
71 mov \reg, #16 @ size offset
72 mov \reg, \reg, lsl \tmp @ actual cache line size
77 * Sanity check the PTE configuration for the code below - which makes
78 * certain assumptions about how these bits are layed out.
81 #if L_PTE_SHARED != PTE_EXT_SHARED
82 #error PTE shared bit mismatch
84 #if (L_PTE_EXEC+L_PTE_USER+L_PTE_WRITE+L_PTE_DIRTY+L_PTE_YOUNG+\
85 L_PTE_FILE+L_PTE_PRESENT) > L_PTE_SHARED
86 #error Invalid Linux PTE bit settings
88 #endif /* CONFIG_MMU */
91 * The ARMv6 and ARMv7 set_pte_ext translation function.
93 * Permission translation:
94 * YUWD APX AP1 AP0 SVC User
95 * 0xxx 0 0 0 no acc no acc
96 * 100x 1 0 1 r/o no acc
97 * 10x0 1 0 1 r/o no acc
98 * 1011 0 0 1 r/w no acc
103 * If !CONFIG_CPU_USE_DOMAINS, the following permissions are changed:
107 .macro armv6_mt_table pfx
109 .long 0x00 @ L_PTE_MT_UNCACHED
110 .long PTE_EXT_TEX(1) @ L_PTE_MT_BUFFERABLE
111 .long PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH
112 .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK
113 .long PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED
115 .long 0x00 @ L_PTE_MT_MINICACHE (not present)
116 .long PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC
118 .long PTE_EXT_TEX(1) @ L_PTE_MT_DEV_WC
120 .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED
121 .long PTE_EXT_TEX(2) @ L_PTE_MT_DEV_NONSHARED
127 .macro armv6_set_pte_ext pfx
128 str r1, [r0], #-2048 @ linux version
130 bic r3, r1, #0x000003fc
131 bic r3, r3, #PTE_TYPE_MASK
133 orr r3, r3, #PTE_EXT_AP0 | 2
135 adr ip, \pfx\()_mt_table
136 and r2, r1, #L_PTE_MT_MASK
140 tstne r1, #L_PTE_DIRTY
141 orreq r3, r3, #PTE_EXT_APX
144 orrne r3, r3, #PTE_EXT_AP1
145 #ifdef CONFIG_CPU_USE_DOMAINS
146 @ allow kernel read/write access to read-only user pages
147 tstne r3, #PTE_EXT_APX
148 bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
152 orreq r3, r3, #PTE_EXT_XN
157 tstne r1, #L_PTE_PRESENT
161 mcr p15, 0, r0, c7, c10, 1 @ flush_pte
166 * The ARMv3, ARMv4 and ARMv5 set_pte_ext translation function,
167 * covering most CPUs except Xscale and Xscale 3.
169 * Permission translation:
171 * 0xxx 0x00 no acc no acc
172 * 100x 0x00 r/o no acc
173 * 10x0 0x00 r/o no acc
174 * 1011 0x55 r/w no acc
179 .macro armv3_set_pte_ext wc_disable=1
180 str r1, [r0], #-2048 @ linux version
182 eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
184 bic r2, r1, #PTE_SMALL_AP_MASK @ keep C, B bits
185 bic r2, r2, #PTE_TYPE_MASK
186 orr r2, r2, #PTE_TYPE_SMALL
188 tst r3, #L_PTE_USER @ user?
189 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
191 tst r3, #L_PTE_WRITE | L_PTE_DIRTY @ write and dirty?
192 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
194 tst r3, #L_PTE_PRESENT | L_PTE_YOUNG @ present and young?
198 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
199 tst r2, #PTE_CACHEABLE
200 bicne r2, r2, #PTE_BUFFERABLE
203 str r2, [r0] @ hardware version
208 * Xscale set_pte_ext translation, split into two halves to cope
209 * with work-arounds. r3 must be preserved by code between these
212 * Permission translation:
214 * 0xxx 00 no acc no acc
222 .macro xscale_set_pte_ext_prologue
223 str r1, [r0], #-2048 @ linux version
225 eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
227 bic r2, r1, #PTE_SMALL_AP_MASK @ keep C, B bits
228 orr r2, r2, #PTE_TYPE_EXT @ extended page
230 tst r3, #L_PTE_USER @ user?
231 orrne r2, r2, #PTE_EXT_AP_URO_SRW @ yes -> user r/o, system r/w
233 tst r3, #L_PTE_WRITE | L_PTE_DIRTY @ write and dirty?
234 orreq r2, r2, #PTE_EXT_AP_UNO_SRW @ yes -> user n/a, system r/w
235 @ combined with user -> user r/w
238 .macro xscale_set_pte_ext_epilogue
239 tst r3, #L_PTE_PRESENT | L_PTE_YOUNG @ present and young?
240 movne r2, #0 @ no -> fault
242 str r2, [r0] @ hardware version
244 mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
245 mcr p15, 0, ip, c7, c10, 4 @ data write barrier