2 * We need constants.h for:
7 #include <asm/asm-offsets.h>
8 #include <asm/thread_info.h>
11 * vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm)
13 .macro vma_vm_mm, rd, rn
14 ldr \rd, [\rn, #VMA_VM_MM]
18 * vma_vm_flags - get vma->vm_flags
20 .macro vma_vm_flags, rd, rn
21 ldr \rd, [\rn, #VMA_VM_FLAGS]
25 ldr \rd, [\rn, #TI_TASK]
26 ldr \rd, [\rd, #TSK_ACTIVE_MM]
30 * act_mm - get current->active_mm
35 ldr \rd, [\rd, #TI_TASK]
36 ldr \rd, [\rd, #TSK_ACTIVE_MM]
40 * mmid - get context id from mm pointer (mm->context.id)
43 ldr \rd, [\rn, #MM_CONTEXT_ID]
47 * mask_asid - mask the ASID from the context ID
53 .macro crval, clear, mmuset, ucset
64 * dcache_line_size - get the minimum D-cache line size from the CTR register
67 .macro dcache_line_size, reg, tmp
68 mrc p15, 0, \tmp, c0, c0, 1 @ read ctr
70 and \tmp, \tmp, #0xf @ cache line size encoding
71 mov \reg, #4 @ bytes per word
72 mov \reg, \reg, lsl \tmp @ actual cache line size
76 * icache_line_size - get the minimum I-cache line size from the CTR register
79 .macro icache_line_size, reg, tmp
80 mrc p15, 0, \tmp, c0, c0, 1 @ read ctr
81 and \tmp, \tmp, #0xf @ cache line size encoding
82 mov \reg, #4 @ bytes per word
83 mov \reg, \reg, lsl \tmp @ actual cache line size
87 * Sanity check the PTE configuration for the code below - which makes
88 * certain assumptions about how these bits are laid out.
91 #if L_PTE_SHARED != PTE_EXT_SHARED
92 #error PTE shared bit mismatch
94 #if (L_PTE_XN+L_PTE_USER+L_PTE_RDONLY+L_PTE_DIRTY+L_PTE_YOUNG+\
95 L_PTE_FILE+L_PTE_PRESENT) > L_PTE_SHARED
96 #error Invalid Linux PTE bit settings
98 #endif /* CONFIG_MMU */
101 * The ARMv6 and ARMv7 set_pte_ext translation function.
103 * Permission translation:
104 * YUWD APX AP1 AP0 SVC User
105 * 0xxx 0 0 0 no acc no acc
106 * 100x 1 0 1 r/o no acc
107 * 10x0 1 0 1 r/o no acc
108 * 1011 0 0 1 r/w no acc
113 .macro armv6_mt_table pfx
115 .long 0x00 @ L_PTE_MT_UNCACHED
116 .long PTE_EXT_TEX(1) @ L_PTE_MT_BUFFERABLE
117 .long PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH
118 .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK
119 .long PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED
121 .long 0x00 @ L_PTE_MT_MINICACHE (not present)
122 .long PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC
124 .long PTE_EXT_TEX(1) @ L_PTE_MT_DEV_WC
126 .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED
127 .long PTE_EXT_TEX(2) @ L_PTE_MT_DEV_NONSHARED
130 .long PTE_CACHEABLE | PTE_BUFFERABLE | PTE_EXT_APX @ L_PTE_MT_VECTORS
133 .macro armv6_set_pte_ext pfx
134 str r1, [r0], #2048 @ linux version
136 bic r3, r1, #0x000003fc
137 bic r3, r3, #PTE_TYPE_MASK
139 orr r3, r3, #PTE_EXT_AP0 | 2
141 adr ip, \pfx\()_mt_table
142 and r2, r1, #L_PTE_MT_MASK
145 eor r1, r1, #L_PTE_DIRTY
146 tst r1, #L_PTE_DIRTY|L_PTE_RDONLY
147 orrne r3, r3, #PTE_EXT_APX
150 orrne r3, r3, #PTE_EXT_AP1
151 tstne r3, #PTE_EXT_APX
153 @ user read-only -> kernel read-only
154 bicne r3, r3, #PTE_EXT_AP0
157 orrne r3, r3, #PTE_EXT_XN
162 tstne r1, #L_PTE_PRESENT
164 tstne r1, #L_PTE_NONE
168 mcr p15, 0, r0, c7, c10, 1 @ flush_pte
173 * The ARMv3, ARMv4 and ARMv5 set_pte_ext translation function,
174 * covering most CPUs except Xscale and Xscale 3.
176 * Permission translation:
178 * 0xxx 0x00 no acc no acc
179 * 100x 0x00 r/o no acc
180 * 10x0 0x00 r/o no acc
181 * 1011 0x55 r/w no acc
186 .macro armv3_set_pte_ext wc_disable=1
187 str r1, [r0], #2048 @ linux version
189 eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY
191 bic r2, r1, #PTE_SMALL_AP_MASK @ keep C, B bits
192 bic r2, r2, #PTE_TYPE_MASK
193 orr r2, r2, #PTE_TYPE_SMALL
195 tst r3, #L_PTE_USER @ user?
196 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
198 tst r3, #L_PTE_RDONLY | L_PTE_DIRTY @ write and dirty?
199 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
201 tst r3, #L_PTE_PRESENT | L_PTE_YOUNG @ present and young?
205 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
206 tst r2, #PTE_CACHEABLE
207 bicne r2, r2, #PTE_BUFFERABLE
210 str r2, [r0] @ hardware version
215 * Xscale set_pte_ext translation, split into two halves to cope
216 * with work-arounds. r3 must be preserved by code between these
219 * Permission translation:
221 * 0xxx 00 no acc no acc
229 .macro xscale_set_pte_ext_prologue
230 str r1, [r0] @ linux version
232 eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY
234 bic r2, r1, #PTE_SMALL_AP_MASK @ keep C, B bits
235 orr r2, r2, #PTE_TYPE_EXT @ extended page
237 tst r3, #L_PTE_USER @ user?
238 orrne r2, r2, #PTE_EXT_AP_URO_SRW @ yes -> user r/o, system r/w
240 tst r3, #L_PTE_RDONLY | L_PTE_DIRTY @ write and dirty?
241 orreq r2, r2, #PTE_EXT_AP_UNO_SRW @ yes -> user n/a, system r/w
242 @ combined with user -> user r/w
245 .macro xscale_set_pte_ext_epilogue
246 tst r3, #L_PTE_PRESENT | L_PTE_YOUNG @ present and young?
247 movne r2, #0 @ no -> fault
249 str r2, [r0, #2048]! @ hardware version
251 mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
252 mcr p15, 0, ip, c7, c10, 4 @ data write barrier
255 .macro define_processor_functions name:req, dabort:req, pabort:req, nommu=0, suspend=0
256 .type \name\()_processor_functions, #object
258 ENTRY(\name\()_processor_functions)
261 .word cpu_\name\()_proc_init
262 .word cpu_\name\()_proc_fin
263 .word cpu_\name\()_reset
264 .word cpu_\name\()_do_idle
265 .word cpu_\name\()_dcache_clean_area
266 .word cpu_\name\()_switch_mm
271 .word cpu_\name\()_set_pte_ext
275 .word cpu_\name\()_suspend_size
276 #ifdef CONFIG_PM_SLEEP
277 .word cpu_\name\()_do_suspend
278 .word cpu_\name\()_do_resume
289 .size \name\()_processor_functions, . - \name\()_processor_functions
292 .macro define_cache_functions name:req
294 .type \name\()_cache_fns, #object
295 ENTRY(\name\()_cache_fns)
296 .long \name\()_flush_icache_all
297 .long \name\()_flush_kern_cache_all
298 .long \name\()_flush_user_cache_all
299 .long \name\()_flush_user_cache_range
300 .long \name\()_coherent_kern_range
301 .long \name\()_coherent_user_range
302 .long \name\()_flush_kern_dcache_area
303 .long \name\()_dma_map_area
304 .long \name\()_dma_unmap_area
305 .long \name\()_dma_flush_range
306 .size \name\()_cache_fns, . - \name\()_cache_fns
309 .macro define_tlb_functions name:req, flags_up:req, flags_smp
310 .type \name\()_tlb_fns, #object
311 ENTRY(\name\()_tlb_fns)
312 .long \name\()_flush_user_tlb_range
313 .long \name\()_flush_kern_tlb_range
315 ALT_SMP(.long \flags_smp )
316 ALT_UP(.long \flags_up )
320 .size \name\()_tlb_fns, . - \name\()_tlb_fns