2 * linux/arch/arm/mm/mmu.c
4 * Copyright (C) 1995-2005 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #include <linux/module.h>
11 #include <linux/kernel.h>
12 #include <linux/errno.h>
13 #include <linux/init.h>
14 #include <linux/mman.h>
15 #include <linux/nodemask.h>
16 #include <linux/memblock.h>
19 #include <asm/cputype.h>
20 #include <asm/sections.h>
21 #include <asm/cachetype.h>
22 #include <asm/setup.h>
23 #include <asm/sizes.h>
24 #include <asm/smp_plat.h>
26 #include <asm/highmem.h>
27 #include <asm/traps.h>
29 #include <asm/mach/arch.h>
30 #include <asm/mach/map.h>
35 * empty_zero_page is a special page that is used for
36 * zero-initialized data and COW.
38 struct page *empty_zero_page;
39 EXPORT_SYMBOL(empty_zero_page);
42 * The pmd table for the upper-most set of pages.
46 #define CPOLICY_UNCACHED 0
47 #define CPOLICY_BUFFERED 1
48 #define CPOLICY_WRITETHROUGH 2
49 #define CPOLICY_WRITEBACK 3
50 #define CPOLICY_WRITEALLOC 4
52 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
53 static unsigned int ecc_mask __initdata = 0;
55 pgprot_t pgprot_kernel;
57 EXPORT_SYMBOL(pgprot_user);
58 EXPORT_SYMBOL(pgprot_kernel);
61 const char policy[16];
67 static struct cachepolicy cache_policies[] __initdata = {
71 .pmd = PMD_SECT_UNCACHED,
72 .pte = L_PTE_MT_UNCACHED,
76 .pmd = PMD_SECT_BUFFERED,
77 .pte = L_PTE_MT_BUFFERABLE,
79 .policy = "writethrough",
82 .pte = L_PTE_MT_WRITETHROUGH,
84 .policy = "writeback",
87 .pte = L_PTE_MT_WRITEBACK,
89 .policy = "writealloc",
92 .pte = L_PTE_MT_WRITEALLOC,
97 * These are useful for identifying cache coherency
98 * problems by allowing the cache or the cache and
99 * writebuffer to be turned off. (Note: the write
100 * buffer should not be on and the cache off).
102 static int __init early_cachepolicy(char *p)
106 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
107 int len = strlen(cache_policies[i].policy);
109 if (memcmp(p, cache_policies[i].policy, len) == 0) {
111 cr_alignment &= ~cache_policies[i].cr_mask;
112 cr_no_alignment &= ~cache_policies[i].cr_mask;
116 if (i == ARRAY_SIZE(cache_policies))
117 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
119 * This restriction is partly to do with the way we boot; it is
120 * unpredictable to have memory mapped using two different sets of
121 * memory attributes (shared, type, and cache attribs). We can not
122 * change these attributes once the initial assembly has setup the
125 if (cpu_architecture() >= CPU_ARCH_ARMv6) {
126 printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
127 cachepolicy = CPOLICY_WRITEBACK;
130 set_cr(cr_alignment);
133 early_param("cachepolicy", early_cachepolicy);
135 static int __init early_nocache(char *__unused)
137 char *p = "buffered";
138 printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
139 early_cachepolicy(p);
142 early_param("nocache", early_nocache);
144 static int __init early_nowrite(char *__unused)
146 char *p = "uncached";
147 printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
148 early_cachepolicy(p);
151 early_param("nowb", early_nowrite);
153 static int __init early_ecc(char *p)
155 if (memcmp(p, "on", 2) == 0)
156 ecc_mask = PMD_PROTECTION;
157 else if (memcmp(p, "off", 3) == 0)
161 early_param("ecc", early_ecc);
163 static int __init noalign_setup(char *__unused)
165 cr_alignment &= ~CR_A;
166 cr_no_alignment &= ~CR_A;
167 set_cr(cr_alignment);
170 __setup("noalign", noalign_setup);
173 void adjust_cr(unsigned long mask, unsigned long set)
181 local_irq_save(flags);
183 cr_no_alignment = (cr_no_alignment & ~mask) | set;
184 cr_alignment = (cr_alignment & ~mask) | set;
186 set_cr((get_cr() & ~mask) | set);
188 local_irq_restore(flags);
192 #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
193 #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE
195 static struct mem_type mem_types[] = {
196 [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */
197 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
199 .prot_l1 = PMD_TYPE_TABLE,
200 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S,
203 [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
204 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
205 .prot_l1 = PMD_TYPE_TABLE,
206 .prot_sect = PROT_SECT_DEVICE,
209 [MT_DEVICE_CACHED] = { /* ioremap_cached */
210 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
211 .prot_l1 = PMD_TYPE_TABLE,
212 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
215 [MT_DEVICE_WC] = { /* ioremap_wc */
216 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
217 .prot_l1 = PMD_TYPE_TABLE,
218 .prot_sect = PROT_SECT_DEVICE,
222 .prot_pte = PROT_PTE_DEVICE,
223 .prot_l1 = PMD_TYPE_TABLE,
224 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
228 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
229 .domain = DOMAIN_KERNEL,
232 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
233 .domain = DOMAIN_KERNEL,
236 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
238 .prot_l1 = PMD_TYPE_TABLE,
239 .domain = DOMAIN_USER,
241 [MT_HIGH_VECTORS] = {
242 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
243 L_PTE_USER | L_PTE_RDONLY,
244 .prot_l1 = PMD_TYPE_TABLE,
245 .domain = DOMAIN_USER,
248 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
249 .prot_l1 = PMD_TYPE_TABLE,
250 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
251 .domain = DOMAIN_KERNEL,
254 .prot_sect = PMD_TYPE_SECT,
255 .domain = DOMAIN_KERNEL,
257 [MT_MEMORY_NONCACHED] = {
258 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
260 .prot_l1 = PMD_TYPE_TABLE,
261 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
262 .domain = DOMAIN_KERNEL,
265 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
267 .prot_l1 = PMD_TYPE_TABLE,
268 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
269 .domain = DOMAIN_KERNEL,
272 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
273 .prot_l1 = PMD_TYPE_TABLE,
274 .domain = DOMAIN_KERNEL,
278 const struct mem_type *get_mem_type(unsigned int type)
280 return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
282 EXPORT_SYMBOL(get_mem_type);
285 * Adjust the PMD section entries according to the CPU in use.
287 static void __init build_mem_type_table(void)
289 struct cachepolicy *cp;
290 unsigned int cr = get_cr();
291 unsigned int user_pgprot, kern_pgprot, vecs_pgprot;
292 int cpu_arch = cpu_architecture();
295 if (cpu_arch < CPU_ARCH_ARMv6) {
296 #if defined(CONFIG_CPU_DCACHE_DISABLE)
297 if (cachepolicy > CPOLICY_BUFFERED)
298 cachepolicy = CPOLICY_BUFFERED;
299 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
300 if (cachepolicy > CPOLICY_WRITETHROUGH)
301 cachepolicy = CPOLICY_WRITETHROUGH;
304 if (cpu_arch < CPU_ARCH_ARMv5) {
305 if (cachepolicy >= CPOLICY_WRITEALLOC)
306 cachepolicy = CPOLICY_WRITEBACK;
310 cachepolicy = CPOLICY_WRITEALLOC;
313 * Strip out features not present on earlier architectures.
314 * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those
315 * without extended page tables don't have the 'Shared' bit.
317 if (cpu_arch < CPU_ARCH_ARMv5)
318 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
319 mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
320 if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
321 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
322 mem_types[i].prot_sect &= ~PMD_SECT_S;
325 * ARMv5 and lower, bit 4 must be set for page tables (was: cache
326 * "update-able on write" bit on ARM610). However, Xscale and
327 * Xscale3 require this bit to be cleared.
329 if (cpu_is_xscale() || cpu_is_xsc3()) {
330 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
331 mem_types[i].prot_sect &= ~PMD_BIT4;
332 mem_types[i].prot_l1 &= ~PMD_BIT4;
334 } else if (cpu_arch < CPU_ARCH_ARMv6) {
335 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
336 if (mem_types[i].prot_l1)
337 mem_types[i].prot_l1 |= PMD_BIT4;
338 if (mem_types[i].prot_sect)
339 mem_types[i].prot_sect |= PMD_BIT4;
344 * Mark the device areas according to the CPU/architecture.
346 if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
347 if (!cpu_is_xsc3()) {
349 * Mark device regions on ARMv6+ as execute-never
350 * to prevent speculative instruction fetches.
352 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
353 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
354 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
355 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
357 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
359 * For ARMv7 with TEX remapping,
360 * - shared device is SXCB=1100
361 * - nonshared device is SXCB=0100
362 * - write combine device mem is SXCB=0001
363 * (Uncached Normal memory)
365 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
366 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
367 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
368 } else if (cpu_is_xsc3()) {
371 * - shared device is TEXCB=00101
372 * - nonshared device is TEXCB=01000
373 * - write combine device mem is TEXCB=00100
374 * (Inner/Outer Uncacheable in xsc3 parlance)
376 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
377 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
378 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
381 * For ARMv6 and ARMv7 without TEX remapping,
382 * - shared device is TEXCB=00001
383 * - nonshared device is TEXCB=01000
384 * - write combine device mem is TEXCB=00100
385 * (Uncached Normal in ARMv6 parlance).
387 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
388 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
389 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
393 * On others, write combining is "Uncached/Buffered"
395 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
399 * Now deal with the memory-type mappings
401 cp = &cache_policies[cachepolicy];
402 vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
405 * Only use write-through for non-SMP systems
407 if (!is_smp() && cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH)
408 vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte;
411 * Enable CPU-specific coherency if supported.
412 * (Only available on XSC3 at the moment.)
414 if (arch_is_coherent() && cpu_is_xsc3()) {
415 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
416 mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
417 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
418 mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
421 * ARMv6 and above have extended page tables.
423 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
425 * Mark cache clean areas and XIP ROM read only
426 * from SVC mode and no access from userspace.
428 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
429 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
430 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
434 * Mark memory with the "shared" attribute
437 user_pgprot |= L_PTE_SHARED;
438 kern_pgprot |= L_PTE_SHARED;
439 vecs_pgprot |= L_PTE_SHARED;
440 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
441 mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
442 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
443 mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
444 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
445 mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
446 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
447 mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
452 * Non-cacheable Normal - intended for memory areas that must
453 * not cause dirty cache line writebacks when used
455 if (cpu_arch >= CPU_ARCH_ARMv6) {
456 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
457 /* Non-cacheable Normal is XCB = 001 */
458 mem_types[MT_MEMORY_NONCACHED].prot_sect |=
461 /* For both ARMv6 and non-TEX-remapping ARMv7 */
462 mem_types[MT_MEMORY_NONCACHED].prot_sect |=
466 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
469 for (i = 0; i < 16; i++) {
470 unsigned long v = pgprot_val(protection_map[i]);
471 protection_map[i] = __pgprot(v | user_pgprot);
474 mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
475 mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
477 pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
478 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
479 L_PTE_DIRTY | kern_pgprot);
481 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
482 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
483 mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
484 mem_types[MT_MEMORY].prot_pte |= kern_pgprot;
485 mem_types[MT_MEMORY_NONCACHED].prot_sect |= ecc_mask;
486 mem_types[MT_ROM].prot_sect |= cp->pmd;
490 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
494 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
497 printk("Memory policy: ECC %sabled, Data cache %s\n",
498 ecc_mask ? "en" : "dis", cp->policy);
500 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
501 struct mem_type *t = &mem_types[i];
503 t->prot_l1 |= PMD_DOMAIN(t->domain);
505 t->prot_sect |= PMD_DOMAIN(t->domain);
509 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
510 pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
511 unsigned long size, pgprot_t vma_prot)
514 return pgprot_noncached(vma_prot);
515 else if (file->f_flags & O_SYNC)
516 return pgprot_writecombine(vma_prot);
519 EXPORT_SYMBOL(phys_mem_access_prot);
522 #define vectors_base() (vectors_high() ? 0xffff0000 : 0)
524 static void __init *early_alloc(unsigned long sz)
526 void *ptr = __va(memblock_alloc(sz, sz));
531 static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot)
533 if (pmd_none(*pmd)) {
534 pte_t *pte = early_alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE);
535 __pmd_populate(pmd, __pa(pte), prot);
537 BUG_ON(pmd_bad(*pmd));
538 return pte_offset_kernel(pmd, addr);
541 static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
542 unsigned long end, unsigned long pfn,
543 const struct mem_type *type)
545 pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1);
547 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
549 } while (pte++, addr += PAGE_SIZE, addr != end);
552 static void __init alloc_init_section(pud_t *pud, unsigned long addr,
553 unsigned long end, phys_addr_t phys,
554 const struct mem_type *type)
556 pmd_t *pmd = pmd_offset(pud, addr);
559 * Try a section mapping - end, addr and phys must all be aligned
560 * to a section boundary. Note that PMDs refer to the individual
561 * L1 entries, whereas PGDs refer to a group of L1 entries making
562 * up one logical pointer to an L2 table.
564 if (((addr | end | phys) & ~SECTION_MASK) == 0) {
567 if (addr & SECTION_SIZE)
571 *pmd = __pmd(phys | type->prot_sect);
572 phys += SECTION_SIZE;
573 } while (pmd++, addr += SECTION_SIZE, addr != end);
578 * No need to loop; pte's aren't interested in the
579 * individual L1 entries.
581 alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type);
585 static void alloc_init_pud(pgd_t *pgd, unsigned long addr, unsigned long end,
586 unsigned long phys, const struct mem_type *type)
588 pud_t *pud = pud_offset(pgd, addr);
592 next = pud_addr_end(addr, end);
593 alloc_init_section(pud, addr, next, phys, type);
595 } while (pud++, addr = next, addr != end);
598 static void __init create_36bit_mapping(struct map_desc *md,
599 const struct mem_type *type)
601 unsigned long addr, length, end;
606 phys = __pfn_to_phys(md->pfn);
607 length = PAGE_ALIGN(md->length);
609 if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
610 printk(KERN_ERR "MM: CPU does not support supersection "
611 "mapping for 0x%08llx at 0x%08lx\n",
612 (long long)__pfn_to_phys((u64)md->pfn), addr);
616 /* N.B. ARMv6 supersections are only defined to work with domain 0.
617 * Since domain assignments can in fact be arbitrary, the
618 * 'domain == 0' check below is required to insure that ARMv6
619 * supersections are only allocated for domain 0 regardless
620 * of the actual domain assignments in use.
623 printk(KERN_ERR "MM: invalid domain in supersection "
624 "mapping for 0x%08llx at 0x%08lx\n",
625 (long long)__pfn_to_phys((u64)md->pfn), addr);
629 if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
630 printk(KERN_ERR "MM: cannot create mapping for 0x%08llx"
631 " at 0x%08lx invalid alignment\n",
632 (long long)__pfn_to_phys((u64)md->pfn), addr);
637 * Shift bits [35:32] of address into bits [23:20] of PMD
640 phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
642 pgd = pgd_offset_k(addr);
645 pud_t *pud = pud_offset(pgd, addr);
646 pmd_t *pmd = pmd_offset(pud, addr);
649 for (i = 0; i < 16; i++)
650 *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER);
652 addr += SUPERSECTION_SIZE;
653 phys += SUPERSECTION_SIZE;
654 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
655 } while (addr != end);
659 * Create the page directory entries and any necessary
660 * page tables for the mapping specified by `md'. We
661 * are able to cope here with varying sizes and address
662 * offsets, and we take full advantage of sections and
665 static void __init create_mapping(struct map_desc *md)
667 unsigned long addr, length, end;
669 const struct mem_type *type;
672 if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
673 printk(KERN_WARNING "BUG: not creating mapping for 0x%08llx"
674 " at 0x%08lx in user region\n",
675 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
679 if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
680 md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) {
681 printk(KERN_WARNING "BUG: mapping for 0x%08llx"
682 " at 0x%08lx overlaps vmalloc space\n",
683 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
686 type = &mem_types[md->type];
689 * Catch 36-bit addresses
691 if (md->pfn >= 0x100000) {
692 create_36bit_mapping(md, type);
696 addr = md->virtual & PAGE_MASK;
697 phys = __pfn_to_phys(md->pfn);
698 length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
700 if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
701 printk(KERN_WARNING "BUG: map for 0x%08llx at 0x%08lx can not "
702 "be mapped using pages, ignoring.\n",
703 (long long)__pfn_to_phys(md->pfn), addr);
707 pgd = pgd_offset_k(addr);
710 unsigned long next = pgd_addr_end(addr, end);
712 alloc_init_pud(pgd, addr, next, phys, type);
716 } while (pgd++, addr != end);
720 * Create the architecture specific mappings
722 void __init iotable_init(struct map_desc *io_desc, int nr)
726 for (i = 0; i < nr; i++)
727 create_mapping(io_desc + i);
730 static void * __initdata vmalloc_min = (void *)(VMALLOC_END - SZ_128M);
733 * vmalloc=size forces the vmalloc area to be exactly 'size'
734 * bytes. This can be used to increase (or decrease) the vmalloc
735 * area - the default is 128m.
737 static int __init early_vmalloc(char *arg)
739 unsigned long vmalloc_reserve = memparse(arg, NULL);
741 if (vmalloc_reserve < SZ_16M) {
742 vmalloc_reserve = SZ_16M;
744 "vmalloc area too small, limiting to %luMB\n",
745 vmalloc_reserve >> 20);
748 if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
749 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
751 "vmalloc area is too big, limiting to %luMB\n",
752 vmalloc_reserve >> 20);
755 vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
758 early_param("vmalloc", early_vmalloc);
760 static phys_addr_t lowmem_limit __initdata = 0;
762 static void __init sanity_check_meminfo(void)
764 int i, j, highmem = 0;
766 lowmem_limit = __pa(vmalloc_min - 1) + 1;
767 memblock_set_current_limit(lowmem_limit);
769 for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
770 struct membank *bank = &meminfo.bank[j];
771 *bank = meminfo.bank[i];
773 #ifdef CONFIG_HIGHMEM
774 if (__va(bank->start) > vmalloc_min ||
775 __va(bank->start) < (void *)PAGE_OFFSET)
778 bank->highmem = highmem;
781 * Split those memory banks which are partially overlapping
782 * the vmalloc area greatly simplifying things later.
784 if (__va(bank->start) < vmalloc_min &&
785 bank->size > vmalloc_min - __va(bank->start)) {
786 if (meminfo.nr_banks >= NR_BANKS) {
787 printk(KERN_CRIT "NR_BANKS too low, "
788 "ignoring high memory\n");
790 memmove(bank + 1, bank,
791 (meminfo.nr_banks - i) * sizeof(*bank));
794 bank[1].size -= vmalloc_min - __va(bank->start);
795 bank[1].start = __pa(vmalloc_min - 1) + 1;
796 bank[1].highmem = highmem = 1;
799 bank->size = vmalloc_min - __va(bank->start);
802 bank->highmem = highmem;
805 * Check whether this memory bank would entirely overlap
808 if (__va(bank->start) >= vmalloc_min ||
809 __va(bank->start) < (void *)PAGE_OFFSET) {
810 printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
811 "(vmalloc region overlap).\n",
812 (unsigned long long)bank->start,
813 (unsigned long long)bank->start + bank->size - 1);
818 * Check whether this memory bank would partially overlap
821 if (__va(bank->start + bank->size) > vmalloc_min ||
822 __va(bank->start + bank->size) < __va(bank->start)) {
823 unsigned long newsize = vmalloc_min - __va(bank->start);
824 printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx "
825 "to -%.8llx (vmalloc region overlap).\n",
826 (unsigned long long)bank->start,
827 (unsigned long long)bank->start + bank->size - 1,
828 (unsigned long long)bank->start + newsize - 1);
829 bank->size = newsize;
834 #ifdef CONFIG_HIGHMEM
836 const char *reason = NULL;
838 if (cache_is_vipt_aliasing()) {
840 * Interactions between kmap and other mappings
841 * make highmem support with aliasing VIPT caches
844 reason = "with VIPT aliasing cache";
847 printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n",
849 while (j > 0 && meminfo.bank[j - 1].highmem)
854 meminfo.nr_banks = j;
857 static inline void prepare_page_table(void)
863 * Clear out all the mappings below the kernel image.
865 for (addr = 0; addr < MODULES_VADDR; addr += PGDIR_SIZE)
866 pmd_clear(pmd_off_k(addr));
868 #ifdef CONFIG_XIP_KERNEL
869 /* The XIP kernel is mapped in the module area -- skip over it */
870 addr = ((unsigned long)_etext + PGDIR_SIZE - 1) & PGDIR_MASK;
872 for ( ; addr < PAGE_OFFSET; addr += PGDIR_SIZE)
873 pmd_clear(pmd_off_k(addr));
876 * Find the end of the first block of lowmem.
878 end = memblock.memory.regions[0].base + memblock.memory.regions[0].size;
879 if (end >= lowmem_limit)
883 * Clear out all the kernel space mappings, except for the first
884 * memory bank, up to the end of the vmalloc region.
886 for (addr = __phys_to_virt(end);
887 addr < VMALLOC_END; addr += PGDIR_SIZE)
888 pmd_clear(pmd_off_k(addr));
892 * Reserve the special regions of memory
894 void __init arm_mm_memblock_reserve(void)
897 * Reserve the page tables. These are already in use,
898 * and can only be in node 0.
900 memblock_reserve(__pa(swapper_pg_dir), PTRS_PER_PGD * sizeof(pgd_t));
904 * Because of the SA1111 DMA bug, we want to preserve our
905 * precious DMA-able memory...
907 memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
912 * Set up device the mappings. Since we clear out the page tables for all
913 * mappings above VMALLOC_END, we will remove any debug device mappings.
914 * This means you have to be careful how you debug this function, or any
915 * called function. This means you can't use any function or debugging
916 * method which may touch any device, otherwise the kernel _will_ crash.
918 static void __init devicemaps_init(struct machine_desc *mdesc)
924 * Allocate the vector page early.
926 vectors_page = early_alloc(PAGE_SIZE);
928 for (addr = VMALLOC_END; addr; addr += PGDIR_SIZE)
929 pmd_clear(pmd_off_k(addr));
932 * Map the kernel if it is XIP.
933 * It is always first in the modulearea.
935 #ifdef CONFIG_XIP_KERNEL
936 map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
937 map.virtual = MODULES_VADDR;
938 map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
940 create_mapping(&map);
944 * Map the cache flushing regions.
947 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
948 map.virtual = FLUSH_BASE;
950 map.type = MT_CACHECLEAN;
951 create_mapping(&map);
953 #ifdef FLUSH_BASE_MINICACHE
954 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
955 map.virtual = FLUSH_BASE_MINICACHE;
957 map.type = MT_MINICLEAN;
958 create_mapping(&map);
962 * Create a mapping for the machine vectors at the high-vectors
963 * location (0xffff0000). If we aren't using high-vectors, also
964 * create a mapping at the low-vectors virtual address.
966 map.pfn = __phys_to_pfn(virt_to_phys(vectors_page));
967 map.virtual = 0xffff0000;
968 map.length = PAGE_SIZE;
969 map.type = MT_HIGH_VECTORS;
970 create_mapping(&map);
972 if (!vectors_high()) {
974 map.type = MT_LOW_VECTORS;
975 create_mapping(&map);
979 * Ask the machine support to map in the statically mapped devices.
985 * Finally flush the caches and tlb to ensure that we're in a
986 * consistent state wrt the writebuffer. This also ensures that
987 * any write-allocated cache lines in the vector page are written
988 * back. After this point, we can start to touch devices again.
990 local_flush_tlb_all();
994 static void __init kmap_init(void)
996 #ifdef CONFIG_HIGHMEM
997 pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
998 PKMAP_BASE, _PAGE_KERNEL_TABLE);
1002 static void __init map_lowmem(void)
1004 struct memblock_region *reg;
1006 /* Map all the lowmem memory banks. */
1007 for_each_memblock(memory, reg) {
1008 phys_addr_t start = reg->base;
1009 phys_addr_t end = start + reg->size;
1010 struct map_desc map;
1012 if (end > lowmem_limit)
1017 map.pfn = __phys_to_pfn(start);
1018 map.virtual = __phys_to_virt(start);
1019 map.length = end - start;
1020 map.type = MT_MEMORY;
1022 create_mapping(&map);
1027 * paging_init() sets up the page tables, initialises the zone memory
1028 * maps, and sets up the zero page, bad page and bad page tables.
1030 void __init paging_init(struct machine_desc *mdesc)
1034 build_mem_type_table();
1035 sanity_check_meminfo();
1036 prepare_page_table();
1038 devicemaps_init(mdesc);
1041 top_pmd = pmd_off_k(0xffff0000);
1043 /* allocate the zero page. */
1044 zero_page = early_alloc(PAGE_SIZE);
1048 empty_zero_page = virt_to_page(zero_page);
1049 __flush_dcache_page(NULL, empty_zero_page);