1 #include <asm/hardware/gic.h>
6 .macro get_irqnr_preamble, base, tmp
7 ldr \base, =gic_cpu_base_addr
11 .macro arch_ret_to_user, tmp1, tmp2
15 * The interrupt numbering scheme is defined in the
16 * interrupt controller spec. To wit:
18 * Interrupts 0-15 are IPI
20 * 29-31 are local. We allow 30 to be used for the watchdog.
22 * 1021-1022 are reserved
23 * 1023 is "spurious" (no interrupt)
25 * For now, we ignore all local interrupts so only return an interrupt if it's
26 * between 30 and 1020. The test_for_ipi routine below will pick up on IPIs.
28 * A simple read from the controller will tell us the number of the highest
29 * priority enabled interrupt. We then just need to check whether it is in the
30 * valid range for an IRQ (30-1020 inclusive).
33 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
34 ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
36 bic \irqnr, \irqstat, #0x1c00
43 /* We assume that irqstat (the raw value of the IRQ acknowledge
44 * register) is preserved from the macro above.
45 * If there is an IPI, we immediately signal end of interrupt on the
46 * controller, since this requires the original irqstat value which
47 * we won't easily be able to recreate later.
50 .macro test_for_ipi, irqnr, irqstat, base, tmp
51 bic \irqnr, \irqstat, #0x1c00
53 strcc \irqstat, [\base, #GIC_CPU_EOI]
57 /* As above, this assumes that irqstat and base are preserved.. */
59 .macro test_for_ltirq, irqnr, irqstat, base, tmp
60 bic \irqnr, \irqstat, #0x1c00
64 streq \irqstat, [\base, #GIC_CPU_EOI]