2 * linux/arch/arm/mach-versatile/pci.c
4 * (C) Copyright Koninklijke Philips Electronics NV 2004. All rights reserved.
5 * You can redistribute and/or modify this software under the terms of version 2
6 * of the GNU General Public License as published by the Free Software Foundation.
7 * THIS SOFTWARE IS PROVIDED "AS IS" WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
8 * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. See the GNU
9 * General Public License for more details.
10 * Koninklijke Philips Electronics nor its subsidiaries is obligated to provide any support for this software.
12 * ARM Versatile PCI driver.
14 * 14/04/2005 Initial version, colin.king@philips.com
17 #include <linux/kernel.h>
18 #include <linux/pci.h>
19 #include <linux/ioport.h>
20 #include <linux/interrupt.h>
21 #include <linux/spinlock.h>
22 #include <linux/init.h>
25 #include <mach/hardware.h>
27 #include <asm/system.h>
28 #include <asm/mach/pci.h>
31 * these spaces are mapped using the following base registers:
33 * Usage Local Bus Memory Base/Map registers used
35 * Mem 50000000 - 5FFFFFFF LB_BASE0/LB_MAP0, non prefetch
36 * Mem 60000000 - 6FFFFFFF LB_BASE1/LB_MAP1, prefetch
37 * IO 44000000 - 4FFFFFFF LB_BASE2/LB_MAP2, IO
38 * Cfg 42000000 - 42FFFFFF PCI config
41 #define __IO_ADDRESS(n) ((void __iomem *)(unsigned long)IO_ADDRESS(n))
42 #define SYS_PCICTL __IO_ADDRESS(VERSATILE_SYS_PCICTL)
43 #define PCI_IMAP0 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x0)
44 #define PCI_IMAP1 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x4)
45 #define PCI_IMAP2 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x8)
46 #define PCI_SMAP0 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x10)
47 #define PCI_SMAP1 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x14)
48 #define PCI_SMAP2 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x18)
49 #define PCI_SELFID __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0xc)
51 #define DEVICE_ID_OFFSET 0x00
52 #define CSR_OFFSET 0x04
53 #define CLASS_ID_OFFSET 0x08
55 #define VP_PCI_DEVICE_ID 0x030010ee
56 #define VP_PCI_CLASS_ID 0x0b400000
58 static unsigned long pci_slot_ignore = 0;
60 static int __init versatile_pci_slot_ignore(char *str)
65 while ((retval = get_option(&str,&slot))) {
66 if ((slot < 0) || (slot > 31)) {
67 printk("Illegal slot value: %d\n",slot);
69 pci_slot_ignore |= (1 << slot);
75 __setup("pci_slot_ignore=", versatile_pci_slot_ignore);
78 static void __iomem *__pci_addr(struct pci_bus *bus,
79 unsigned int devfn, int offset)
81 unsigned int busnr = bus->number;
84 * Trap out illegal values
93 return VERSATILE_PCI_CFG_VIRT_BASE + ((busnr << 16) |
94 (PCI_SLOT(devfn) << 11) | (PCI_FUNC(devfn) << 8) | offset);
97 static int versatile_read_config(struct pci_bus *bus, unsigned int devfn, int where,
100 void __iomem *addr = __pci_addr(bus, devfn, where & ~3);
102 int slot = PCI_SLOT(devfn);
104 if (pci_slot_ignore & (1 << slot)) {
105 /* Ignore this slot */
119 v = __raw_readl(addr);
120 if (where & 2) v >>= 16;
121 if (where & 1) v >>= 8;
126 v = __raw_readl(addr);
127 if (where & 2) v >>= 16;
132 v = __raw_readl(addr);
138 return PCIBIOS_SUCCESSFUL;
141 static int versatile_write_config(struct pci_bus *bus, unsigned int devfn, int where,
144 void __iomem *addr = __pci_addr(bus, devfn, where);
145 int slot = PCI_SLOT(devfn);
147 if (pci_slot_ignore & (1 << slot)) {
148 return PCIBIOS_SUCCESSFUL;
153 __raw_writeb((u8)val, addr);
157 __raw_writew((u16)val, addr);
161 __raw_writel(val, addr);
165 return PCIBIOS_SUCCESSFUL;
168 static struct pci_ops pci_versatile_ops = {
169 .read = versatile_read_config,
170 .write = versatile_write_config,
173 static struct resource io_mem = {
174 .name = "PCI I/O space",
175 .start = VERSATILE_PCI_MEM_BASE0,
176 .end = VERSATILE_PCI_MEM_BASE0+VERSATILE_PCI_MEM_BASE0_SIZE-1,
177 .flags = IORESOURCE_IO,
180 static struct resource non_mem = {
181 .name = "PCI non-prefetchable",
182 .start = VERSATILE_PCI_MEM_BASE1,
183 .end = VERSATILE_PCI_MEM_BASE1+VERSATILE_PCI_MEM_BASE1_SIZE-1,
184 .flags = IORESOURCE_MEM,
187 static struct resource pre_mem = {
188 .name = "PCI prefetchable",
189 .start = VERSATILE_PCI_MEM_BASE2,
190 .end = VERSATILE_PCI_MEM_BASE2+VERSATILE_PCI_MEM_BASE2_SIZE-1,
191 .flags = IORESOURCE_MEM | IORESOURCE_PREFETCH,
194 static int __init pci_versatile_setup_resources(struct resource **resource)
198 ret = request_resource(&iomem_resource, &io_mem);
200 printk(KERN_ERR "PCI: unable to allocate I/O "
201 "memory region (%d)\n", ret);
204 ret = request_resource(&iomem_resource, &non_mem);
206 printk(KERN_ERR "PCI: unable to allocate non-prefetchable "
207 "memory region (%d)\n", ret);
210 ret = request_resource(&iomem_resource, &pre_mem);
212 printk(KERN_ERR "PCI: unable to allocate prefetchable "
213 "memory region (%d)\n", ret);
214 goto release_non_mem;
218 * bus->resource[0] is the IO resource for this bus
219 * bus->resource[1] is the mem resource for this bus
220 * bus->resource[2] is the prefetch mem resource for this bus
222 resource[0] = &io_mem;
223 resource[1] = &non_mem;
224 resource[2] = &pre_mem;
229 release_resource(&non_mem);
231 release_resource(&io_mem);
236 int __init pci_versatile_setup(int nr, struct pci_sys_data *sys)
242 void __iomem *local_pci_cfg_base;
244 val = __raw_readl(SYS_PCICTL);
246 printk("Not plugged into PCI backplane!\n");
253 ret = pci_versatile_setup_resources(sys->resource);
255 printk("pci_versatile_setup: resources... oops?\n");
259 printk("pci_versatile_setup: resources... nr == 0??\n");
264 * We need to discover the PCI core first to configure itself
265 * before the main PCI probing is performed
268 if ((__raw_readl(VERSATILE_PCI_VIRT_BASE+(i<<11)+DEVICE_ID_OFFSET) == VP_PCI_DEVICE_ID) &&
269 (__raw_readl(VERSATILE_PCI_VIRT_BASE+(i<<11)+CLASS_ID_OFFSET) == VP_PCI_CLASS_ID)) {
275 printk("Cannot find PCI core!\n");
280 printk("PCI core found (slot %d)\n",myslot);
282 __raw_writel(myslot, PCI_SELFID);
283 local_pci_cfg_base = VERSATILE_PCI_CFG_VIRT_BASE + (myslot << 11);
285 val = __raw_readl(local_pci_cfg_base + CSR_OFFSET);
286 val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE;
287 __raw_writel(val, local_pci_cfg_base + CSR_OFFSET);
290 * Configure the PCI inbound memory windows to be 1:1 mapped to SDRAM
292 __raw_writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_0);
293 __raw_writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_1);
294 __raw_writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_2);
297 * Do not to map Versatile FPGA PCI device into memory space
299 pci_slot_ignore |= (1 << myslot);
307 struct pci_bus *pci_versatile_scan_bus(int nr, struct pci_sys_data *sys)
309 return pci_scan_bus(sys->busnr, &pci_versatile_ops, sys);
312 void __init pci_versatile_preinit(void)
314 __raw_writel(VERSATILE_PCI_MEM_BASE0 >> 28, PCI_IMAP0);
315 __raw_writel(VERSATILE_PCI_MEM_BASE1 >> 28, PCI_IMAP1);
316 __raw_writel(VERSATILE_PCI_MEM_BASE2 >> 28, PCI_IMAP2);
318 __raw_writel(PHYS_OFFSET >> 28, PCI_SMAP0);
319 __raw_writel(PHYS_OFFSET >> 28, PCI_SMAP1);
320 __raw_writel(PHYS_OFFSET >> 28, PCI_SMAP2);
322 __raw_writel(1, SYS_PCICTL);
326 * map the specified device/slot/pin to an IRQ. Different backplanes may need to modify this.
328 static int __init versatile_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
331 int devslot = PCI_SLOT(dev->devfn);
339 irq = 27 + ((slot + pin - 1) & 3);
341 printk("PCI map irq: slot %d, pin %d, devslot %d, irq: %d\n",slot,pin,devslot,irq);
346 static struct hw_pci versatile_pci __initdata = {
348 .map_irq = versatile_map_irq,
350 .setup = pci_versatile_setup,
351 .scan = pci_versatile_scan_bus,
352 .preinit = pci_versatile_preinit,
355 static int __init versatile_pci_init(void)
357 pci_common_init(&versatile_pci);
361 subsys_initcall(versatile_pci_init);