arch/arm/mach-versatile/core.c

   1 /*
   2  *  linux/arch/arm/mach-versatile/core.c
   3  *
   4  *  Copyright (C) 1999 - 2003 ARM Limited
   5  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21 #include <linux/init.h>
  22 #include <linux/device.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/irqdomain.h>
  27 #include <linux/of_address.h>
  28 #include <linux/of_platform.h>
  29 #include <linux/amba/bus.h>
  30 #include <linux/amba/clcd.h>
  31 #include <linux/amba/pl061.h>
  32 #include <linux/amba/mmci.h>
  33 #include <linux/amba/pl022.h>
  34 #include <linux/io.h>
  35 #include <linux/gfp.h>
  36 #include <linux/clkdev.h>
  37 #include <linux/mtd/physmap.h>
  38
  39 #include <asm/system.h>
  40 #include <asm/irq.h>
  41 #include <asm/leds.h>
  42 #include <asm/hardware/arm_timer.h>
  43 #include <asm/hardware/icst.h>
  44 #include <asm/hardware/vic.h>
  45 #include <asm/mach-types.h>
  46
  47 #include <asm/mach/arch.h>
  48 #include <asm/mach/irq.h>
  49 #include <asm/mach/time.h>
  50 #include <asm/mach/map.h>
  51 #include <mach/hardware.h>
  52 #include <mach/platform.h>
  53 #include <asm/hardware/timer-sp.h>
  54
  55 #include <plat/clcd.h>
  56 #include <plat/fpga-irq.h>
  57 #include <plat/sched_clock.h>
  58
  59 #include "core.h"
  60
  61 /*
  62  * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
  63  * is the (PA >> 12).
  64  *
  65  * Setup a VA for the Versatile Vectored Interrupt Controller.
  66  */
  67 #define VA_VIC_BASE             __io_address(VERSATILE_VIC_BASE)
  68 #define VA_SIC_BASE             __io_address(VERSATILE_SIC_BASE)
  69
  70 static struct fpga_irq_data sic_irq = {
  71         .base           = VA_SIC_BASE,
  72         .irq_start      = IRQ_SIC_START,
  73         .chip.name      = "SIC",
  74 };
  75
  76 #if 1
  77 #define IRQ_MMCI0A      IRQ_VICSOURCE22
  78 #define IRQ_AACI        IRQ_VICSOURCE24
  79 #define IRQ_ETH         IRQ_VICSOURCE25
  80 #define PIC_MASK        0xFFD00000
  81 #else
  82 #define IRQ_MMCI0A      IRQ_SIC_MMCI0A
  83 #define IRQ_AACI        IRQ_SIC_AACI
  84 #define IRQ_ETH         IRQ_SIC_ETH
  85 #define PIC_MASK        0
  86 #endif
  87
  88 /* Lookup table for finding a DT node that represents the vic instance */
  89 static const struct of_device_id vic_of_match[] __initconst = {
  90         { .compatible = "arm,versatile-vic", },
  91         {}
  92 };
  93
  94 static const struct of_device_id sic_of_match[] __initconst = {
  95         { .compatible = "arm,versatile-sic", },
  96         {}
  97 };
  98
  99 void __init versatile_init_irq(void)
 100 {
 101         struct device_node *np;
 102
 103         np = of_find_matching_node_by_address(NULL, vic_of_match,
 104                                               VERSATILE_VIC_BASE);
 105         __vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0, 0, np);
 106
 107         writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
 108
 109         fpga_irq_init(IRQ_VICSOURCE31, ~PIC_MASK, &sic_irq);
 110         irq_domain_generate_simple(sic_of_match, VERSATILE_SIC_BASE, IRQ_SIC_START);
 111
 112         /*
 113          * Interrupts on secondary controller from 0 to 8 are routed to
 114          * source 31 on PIC.
 115          * Interrupts from 21 to 31 are routed directly to the VIC on
 116          * the corresponding number on primary controller. This is controlled
 117          * by setting PIC_ENABLEx.
 118          */
 119         writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
 120 }
 121
 122 static struct map_desc versatile_io_desc[] __initdata = {
 123         {
 124                 .virtual        =  IO_ADDRESS(VERSATILE_SYS_BASE),
 125                 .pfn            = __phys_to_pfn(VERSATILE_SYS_BASE),
 126                 .length         = SZ_4K,
 127                 .type           = MT_DEVICE
 128         }, {
 129                 .virtual        =  IO_ADDRESS(VERSATILE_SIC_BASE),
 130                 .pfn            = __phys_to_pfn(VERSATILE_SIC_BASE),
 131                 .length         = SZ_4K,
 132                 .type           = MT_DEVICE
 133         }, {
 134                 .virtual        =  IO_ADDRESS(VERSATILE_VIC_BASE),
 135                 .pfn            = __phys_to_pfn(VERSATILE_VIC_BASE),
 136                 .length         = SZ_4K,
 137                 .type           = MT_DEVICE
 138         }, {
 139                 .virtual        =  IO_ADDRESS(VERSATILE_SCTL_BASE),
 140                 .pfn            = __phys_to_pfn(VERSATILE_SCTL_BASE),
 141                 .length         = SZ_4K * 9,
 142                 .type           = MT_DEVICE
 143         },
 144 #ifdef CONFIG_MACH_VERSATILE_AB
 145         {
 146                 .virtual        =  IO_ADDRESS(VERSATILE_IB2_BASE),
 147                 .pfn            = __phys_to_pfn(VERSATILE_IB2_BASE),
 148                 .length         = SZ_64M,
 149                 .type           = MT_DEVICE
 150         },
 151 #endif
 152 #ifdef CONFIG_DEBUG_LL
 153         {
 154                 .virtual        =  IO_ADDRESS(VERSATILE_UART0_BASE),
 155                 .pfn            = __phys_to_pfn(VERSATILE_UART0_BASE),
 156                 .length         = SZ_4K,
 157                 .type           = MT_DEVICE
 158         },
 159 #endif
 160 #ifdef CONFIG_PCI
 161         {
 162                 .virtual        =  IO_ADDRESS(VERSATILE_PCI_CORE_BASE),
 163                 .pfn            = __phys_to_pfn(VERSATILE_PCI_CORE_BASE),
 164                 .length         = SZ_4K,
 165                 .type           = MT_DEVICE
 166         }, {
 167                 .virtual        =  (unsigned long)VERSATILE_PCI_VIRT_BASE,
 168                 .pfn            = __phys_to_pfn(VERSATILE_PCI_BASE),
 169                 .length         = VERSATILE_PCI_BASE_SIZE,
 170                 .type           = MT_DEVICE
 171         }, {
 172                 .virtual        =  (unsigned long)VERSATILE_PCI_CFG_VIRT_BASE,
 173                 .pfn            = __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
 174                 .length         = VERSATILE_PCI_CFG_BASE_SIZE,
 175                 .type           = MT_DEVICE
 176         },
 177 #if 0
 178         {
 179                 .virtual        =  VERSATILE_PCI_VIRT_MEM_BASE0,
 180                 .pfn            = __phys_to_pfn(VERSATILE_PCI_MEM_BASE0),
 181                 .length         = SZ_16M,
 182                 .type           = MT_DEVICE
 183         }, {
 184                 .virtual        =  VERSATILE_PCI_VIRT_MEM_BASE1,
 185                 .pfn            = __phys_to_pfn(VERSATILE_PCI_MEM_BASE1),
 186                 .length         = SZ_16M,
 187                 .type           = MT_DEVICE
 188         }, {
 189                 .virtual        =  VERSATILE_PCI_VIRT_MEM_BASE2,
 190                 .pfn            = __phys_to_pfn(VERSATILE_PCI_MEM_BASE2),
 191                 .length         = SZ_16M,
 192                 .type           = MT_DEVICE
 193         },
 194 #endif
 195 #endif
 196 };
 197
 198 void __init versatile_map_io(void)
 199 {
 200         iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
 201 }
 202
 203
 204 #define VERSATILE_FLASHCTRL    (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
 205
 206 static void versatile_flash_set_vpp(struct platform_device *pdev, int on)
 207 {
 208         u32 val;
 209
 210         val = __raw_readl(VERSATILE_FLASHCTRL);
 211         if (on)
 212                 val |= VERSATILE_FLASHPROG_FLVPPEN;
 213         else
 214                 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
 215         __raw_writel(val, VERSATILE_FLASHCTRL);
 216 }
 217
 218 static struct physmap_flash_data versatile_flash_data = {
 219         .width                  = 4,
 220         .set_vpp                = versatile_flash_set_vpp,
 221 };
 222
 223 static struct resource versatile_flash_resource = {
 224         .start                  = VERSATILE_FLASH_BASE,
 225         .end                    = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE - 1,
 226         .flags                  = IORESOURCE_MEM,
 227 };
 228
 229 static struct platform_device versatile_flash_device = {
 230         .name                   = "physmap-flash",
 231         .id                     = 0,
 232         .dev                    = {
 233                 .platform_data  = &versatile_flash_data,
 234         },
 235         .num_resources          = 1,
 236         .resource               = &versatile_flash_resource,
 237 };
 238
 239 static struct resource smc91x_resources[] = {
 240         [0] = {
 241                 .start          = VERSATILE_ETH_BASE,
 242                 .end            = VERSATILE_ETH_BASE + SZ_64K - 1,
 243                 .flags          = IORESOURCE_MEM,
 244         },
 245         [1] = {
 246                 .start          = IRQ_ETH,
 247                 .end            = IRQ_ETH,
 248                 .flags          = IORESOURCE_IRQ,
 249         },
 250 };
 251
 252 static struct platform_device smc91x_device = {
 253         .name           = "smc91x",
 254         .id             = 0,
 255         .num_resources  = ARRAY_SIZE(smc91x_resources),
 256         .resource       = smc91x_resources,
 257 };
 258
 259 static struct resource versatile_i2c_resource = {
 260         .start                  = VERSATILE_I2C_BASE,
 261         .end                    = VERSATILE_I2C_BASE + SZ_4K - 1,
 262         .flags                  = IORESOURCE_MEM,
 263 };
 264
 265 static struct platform_device versatile_i2c_device = {
 266         .name                   = "versatile-i2c",
 267         .id                     = 0,
 268         .num_resources          = 1,
 269         .resource               = &versatile_i2c_resource,
 270 };
 271
 272 static struct i2c_board_info versatile_i2c_board_info[] = {
 273         {
 274                 I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
 275         },
 276 };
 277
 278 static int __init versatile_i2c_init(void)
 279 {
 280         return i2c_register_board_info(0, versatile_i2c_board_info,
 281                                        ARRAY_SIZE(versatile_i2c_board_info));
 282 }
 283 arch_initcall(versatile_i2c_init);
 284
 285 #define VERSATILE_SYSMCI        (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
 286
 287 unsigned int mmc_status(struct device *dev)
 288 {
 289         struct amba_device *adev = container_of(dev, struct amba_device, dev);
 290         u32 mask;
 291
 292         if (adev->res.start == VERSATILE_MMCI0_BASE)
 293                 mask = 1;
 294         else
 295                 mask = 2;
 296
 297         return readl(VERSATILE_SYSMCI) & mask;
 298 }
 299
 300 static struct mmci_platform_data mmc0_plat_data = {
 301         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 302         .status         = mmc_status,
 303         .gpio_wp        = -1,
 304         .gpio_cd        = -1,
 305 };
 306
 307 static struct resource char_lcd_resources[] = {
 308         {
 309                 .start = VERSATILE_CHAR_LCD_BASE,
 310                 .end   = (VERSATILE_CHAR_LCD_BASE + SZ_4K - 1),
 311                 .flags = IORESOURCE_MEM,
 312         },
 313 };
 314
 315 static struct platform_device char_lcd_device = {
 316         .name           =       "arm-charlcd",
 317         .id             =       -1,
 318         .num_resources  =       ARRAY_SIZE(char_lcd_resources),
 319         .resource       =       char_lcd_resources,
 320 };
 321
 322 /*
 323  * Clock handling
 324  */
 325 static const struct icst_params versatile_oscvco_params = {
 326         .ref            = 24000000,
 327         .vco_max        = ICST307_VCO_MAX,
 328         .vco_min        = ICST307_VCO_MIN,
 329         .vd_min         = 4 + 8,
 330         .vd_max         = 511 + 8,
 331         .rd_min         = 1 + 2,
 332         .rd_max         = 127 + 2,
 333         .s2div          = icst307_s2div,
 334         .idx2s          = icst307_idx2s,
 335 };
 336
 337 static void versatile_oscvco_set(struct clk *clk, struct icst_vco vco)
 338 {
 339         void __iomem *sys_lock = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LOCK_OFFSET;
 340         u32 val;
 341
 342         val = readl(clk->vcoreg) & ~0x7ffff;
 343         val |= vco.v | (vco.r << 9) | (vco.s << 16);
 344
 345         writel(0xa05f, sys_lock);
 346         writel(val, clk->vcoreg);
 347         writel(0, sys_lock);
 348 }
 349
 350 static const struct clk_ops osc4_clk_ops = {
 351         .round  = icst_clk_round,
 352         .set    = icst_clk_set,
 353         .setvco = versatile_oscvco_set,
 354 };
 355
 356 static struct clk osc4_clk = {
 357         .ops    = &osc4_clk_ops,
 358         .params = &versatile_oscvco_params,
 359 };
 360
 361 /*
 362  * These are fixed clocks.
 363  */
 364 static struct clk ref24_clk = {
 365         .rate   = 24000000,
 366 };
 367
 368 static struct clk sp804_clk = {
 369         .rate   = 1000000,
 370 };
 371
 372 static struct clk dummy_apb_pclk;
 373
 374 static struct clk_lookup lookups[] = {
 375         {       /* AMBA bus clock */
 376                 .con_id         = "apb_pclk",
 377                 .clk            = &dummy_apb_pclk,
 378         }, {    /* UART0 */
 379                 .dev_id         = "dev:f1",
 380                 .clk            = &ref24_clk,
 381         }, {    /* UART1 */
 382                 .dev_id         = "dev:f2",
 383                 .clk            = &ref24_clk,
 384         }, {    /* UART2 */
 385                 .dev_id         = "dev:f3",
 386                 .clk            = &ref24_clk,
 387         }, {    /* UART3 */
 388                 .dev_id         = "fpga:09",
 389                 .clk            = &ref24_clk,
 390         }, {    /* KMI0 */
 391                 .dev_id         = "fpga:06",
 392                 .clk            = &ref24_clk,
 393         }, {    /* KMI1 */
 394                 .dev_id         = "fpga:07",
 395                 .clk            = &ref24_clk,
 396         }, {    /* MMC0 */
 397                 .dev_id         = "fpga:05",
 398                 .clk            = &ref24_clk,
 399         }, {    /* MMC1 */
 400                 .dev_id         = "fpga:0b",
 401                 .clk            = &ref24_clk,
 402         }, {    /* SSP */
 403                 .dev_id         = "dev:f4",
 404                 .clk            = &ref24_clk,
 405         }, {    /* CLCD */
 406                 .dev_id         = "dev:20",
 407                 .clk            = &osc4_clk,
 408         }, {    /* SP804 timers */
 409                 .dev_id         = "sp804",
 410                 .clk            = &sp804_clk,
 411         },
 412 };
 413
 414 /*
 415  * CLCD support.
 416  */
 417 #define SYS_CLCD_MODE_MASK      (3 << 0)
 418 #define SYS_CLCD_MODE_888       (0 << 0)
 419 #define SYS_CLCD_MODE_5551      (1 << 0)
 420 #define SYS_CLCD_MODE_565_RLSB  (2 << 0)
 421 #define SYS_CLCD_MODE_565_BLSB  (3 << 0)
 422 #define SYS_CLCD_NLCDIOON       (1 << 2)
 423 #define SYS_CLCD_VDDPOSSWITCH   (1 << 3)
 424 #define SYS_CLCD_PWR3V5SWITCH   (1 << 4)
 425 #define SYS_CLCD_ID_MASK        (0x1f << 8)
 426 #define SYS_CLCD_ID_SANYO_3_8   (0x00 << 8)
 427 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
 428 #define SYS_CLCD_ID_EPSON_2_2   (0x02 << 8)
 429 #define SYS_CLCD_ID_SANYO_2_5   (0x07 << 8)
 430 #define SYS_CLCD_ID_VGA         (0x1f << 8)
 431
 432 static bool is_sanyo_2_5_lcd;
 433
 434 /*
 435  * Disable all display connectors on the interface module.
 436  */
 437 static void versatile_clcd_disable(struct clcd_fb *fb)
 438 {
 439         void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
 440         u32 val;
 441
 442         val = readl(sys_clcd);
 443         val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 444         writel(val, sys_clcd);
 445
 446 #ifdef CONFIG_MACH_VERSATILE_AB
 447         /*
 448          * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
 449          */
 450         if (machine_is_versatile_ab() && is_sanyo_2_5_lcd) {
 451                 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
 452                 unsigned long ctrl;
 453
 454                 ctrl = readl(versatile_ib2_ctrl);
 455                 ctrl &= ~0x01;
 456                 writel(ctrl, versatile_ib2_ctrl);
 457         }
 458 #endif
 459 }
 460
 461 /*
 462  * Enable the relevant connector on the interface module.
 463  */
 464 static void versatile_clcd_enable(struct clcd_fb *fb)
 465 {
 466         struct fb_var_screeninfo *var = &fb->fb.var;
 467         void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
 468         u32 val;
 469
 470         val = readl(sys_clcd);
 471         val &= ~SYS_CLCD_MODE_MASK;
 472
 473         switch (var->green.length) {
 474         case 5:
 475                 val |= SYS_CLCD_MODE_5551;
 476                 break;
 477         case 6:
 478                 if (var->red.offset == 0)
 479                         val |= SYS_CLCD_MODE_565_RLSB;
 480                 else
 481                         val |= SYS_CLCD_MODE_565_BLSB;
 482                 break;
 483         case 8:
 484                 val |= SYS_CLCD_MODE_888;
 485                 break;
 486         }
 487
 488         /*
 489          * Set the MUX
 490          */
 491         writel(val, sys_clcd);
 492
 493         /*
 494          * And now enable the PSUs
 495          */
 496         val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 497         writel(val, sys_clcd);
 498
 499 #ifdef CONFIG_MACH_VERSATILE_AB
 500         /*
 501          * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
 502          */
 503         if (machine_is_versatile_ab() && is_sanyo_2_5_lcd) {
 504                 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
 505                 unsigned long ctrl;
 506
 507                 ctrl = readl(versatile_ib2_ctrl);
 508                 ctrl |= 0x01;
 509                 writel(ctrl, versatile_ib2_ctrl);
 510         }
 511 #endif
 512 }
 513
 514 /*
 515  * Detect which LCD panel is connected, and return the appropriate
 516  * clcd_panel structure.  Note: we do not have any information on
 517  * the required timings for the 8.4in panel, so we presently assume
 518  * VGA timings.
 519  */
 520 static int versatile_clcd_setup(struct clcd_fb *fb)
 521 {
 522         void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
 523         const char *panel_name;
 524         u32 val;
 525
 526         is_sanyo_2_5_lcd = false;
 527
 528         val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
 529         if (val == SYS_CLCD_ID_SANYO_3_8)
 530                 panel_name = "Sanyo TM38QV67A02A";
 531         else if (val == SYS_CLCD_ID_SANYO_2_5) {
 532                 panel_name = "Sanyo QVGA Portrait";
 533                 is_sanyo_2_5_lcd = true;
 534         } else if (val == SYS_CLCD_ID_EPSON_2_2)
 535                 panel_name = "Epson L2F50113T00";
 536         else if (val == SYS_CLCD_ID_VGA)
 537                 panel_name = "VGA";
 538         else {
 539                 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
 540                         val);
 541                 panel_name = "VGA";
 542         }
 543
 544         fb->panel = versatile_clcd_get_panel(panel_name);
 545         if (!fb->panel)
 546                 return -EINVAL;
 547
 548         return versatile_clcd_setup_dma(fb, SZ_1M);
 549 }
 550
 551 static void versatile_clcd_decode(struct clcd_fb *fb, struct clcd_regs *regs)
 552 {
 553         clcdfb_decode(fb, regs);
 554
 555         /* Always clear BGR for RGB565: we do the routing externally */
 556         if (fb->fb.var.green.length == 6)
 557                 regs->cntl &= ~CNTL_BGR;
 558 }
 559
 560 static struct clcd_board clcd_plat_data = {
 561         .name           = "Versatile",
 562         .caps           = CLCD_CAP_5551 | CLCD_CAP_565 | CLCD_CAP_888,
 563         .check          = clcdfb_check,
 564         .decode         = versatile_clcd_decode,
 565         .disable        = versatile_clcd_disable,
 566         .enable         = versatile_clcd_enable,
 567         .setup          = versatile_clcd_setup,
 568         .mmap           = versatile_clcd_mmap_dma,
 569         .remove         = versatile_clcd_remove_dma,
 570 };
 571
 572 static struct pl061_platform_data gpio0_plat_data = {
 573         .gpio_base      = 0,
 574         .irq_base       = IRQ_GPIO0_START,
 575 };
 576
 577 static struct pl061_platform_data gpio1_plat_data = {
 578         .gpio_base      = 8,
 579         .irq_base       = IRQ_GPIO1_START,
 580 };
 581
 582 static struct pl022_ssp_controller ssp0_plat_data = {
 583         .bus_id = 0,
 584         .enable_dma = 0,
 585         .num_chipselect = 1,
 586 };
 587
 588 #define AACI_IRQ        { IRQ_AACI }
 589 #define MMCI0_IRQ       { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
 590 #define KMI0_IRQ        { IRQ_SIC_KMI0 }
 591 #define KMI1_IRQ        { IRQ_SIC_KMI1 }
 592
 593 /*
 594  * These devices are connected directly to the multi-layer AHB switch
 595  */
 596 #define SMC_IRQ         { }
 597 #define MPMC_IRQ        { }
 598 #define CLCD_IRQ        { IRQ_CLCDINT }
 599 #define DMAC_IRQ        { IRQ_DMAINT }
 600
 601 /*
 602  * These devices are connected via the core APB bridge
 603  */
 604 #define SCTL_IRQ        { }
 605 #define WATCHDOG_IRQ    { IRQ_WDOGINT }
 606 #define GPIO0_IRQ       { IRQ_GPIOINT0 }
 607 #define GPIO1_IRQ       { IRQ_GPIOINT1 }
 608 #define RTC_IRQ         { IRQ_RTCINT }
 609
 610 /*
 611  * These devices are connected via the DMA APB bridge
 612  */
 613 #define SCI_IRQ         { IRQ_SCIINT }
 614 #define UART0_IRQ       { IRQ_UARTINT0 }
 615 #define UART1_IRQ       { IRQ_UARTINT1 }
 616 #define UART2_IRQ       { IRQ_UARTINT2 }
 617 #define SSP_IRQ         { IRQ_SSPINT }
 618
 619 /* FPGA Primecells */
 620 APB_DEVICE(aaci,  "fpga:04", AACI,     NULL);
 621 APB_DEVICE(mmc0,  "fpga:05", MMCI0,    &mmc0_plat_data);
 622 APB_DEVICE(kmi0,  "fpga:06", KMI0,     NULL);
 623 APB_DEVICE(kmi1,  "fpga:07", KMI1,     NULL);
 624
 625 /* DevChip Primecells */
 626 AHB_DEVICE(smc,   "dev:00",  SMC,      NULL);
 627 AHB_DEVICE(mpmc,  "dev:10",  MPMC,     NULL);
 628 AHB_DEVICE(clcd,  "dev:20",  CLCD,     &clcd_plat_data);
 629 AHB_DEVICE(dmac,  "dev:30",  DMAC,     NULL);
 630 APB_DEVICE(sctl,  "dev:e0",  SCTL,     NULL);
 631 APB_DEVICE(wdog,  "dev:e1",  WATCHDOG, NULL);
 632 APB_DEVICE(gpio0, "dev:e4",  GPIO0,    &gpio0_plat_data);
 633 APB_DEVICE(gpio1, "dev:e5",  GPIO1,    &gpio1_plat_data);
 634 APB_DEVICE(rtc,   "dev:e8",  RTC,      NULL);
 635 APB_DEVICE(sci0,  "dev:f0",  SCI,      NULL);
 636 APB_DEVICE(uart0, "dev:f1",  UART0,    NULL);
 637 APB_DEVICE(uart1, "dev:f2",  UART1,    NULL);
 638 APB_DEVICE(uart2, "dev:f3",  UART2,    NULL);
 639 APB_DEVICE(ssp0,  "dev:f4",  SSP,      &ssp0_plat_data);
 640
 641 static struct amba_device *amba_devs[] __initdata = {
 642         &dmac_device,
 643         &uart0_device,
 644         &uart1_device,
 645         &uart2_device,
 646         &smc_device,
 647         &mpmc_device,
 648         &clcd_device,
 649         &sctl_device,
 650         &wdog_device,
 651         &gpio0_device,
 652         &gpio1_device,
 653         &rtc_device,
 654         &sci0_device,
 655         &ssp0_device,
 656         &aaci_device,
 657         &mmc0_device,
 658         &kmi0_device,
 659         &kmi1_device,
 660 };
 661
 662 #ifdef CONFIG_OF
 663 /*
 664  * Lookup table for attaching a specific name and platform_data pointer to
 665  * devices as they get created by of_platform_populate().  Ideally this table
 666  * would not exist, but the current clock implementation depends on some devices
 667  * having a specific name.
 668  */
 669 struct of_dev_auxdata versatile_auxdata_lookup[] __initdata = {
 670         OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI0_BASE, "fpga:05", NULL),
 671         OF_DEV_AUXDATA("arm,primecell", VERSATILE_KMI0_BASE, "fpga:06", NULL),
 672         OF_DEV_AUXDATA("arm,primecell", VERSATILE_KMI1_BASE, "fpga:07", NULL),
 673         OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART3_BASE, "fpga:09", NULL),
 674         OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI1_BASE, "fpga:0b", NULL),
 675
 676         OF_DEV_AUXDATA("arm,primecell", VERSATILE_CLCD_BASE, "dev:20", &clcd_plat_data),
 677         OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART0_BASE, "dev:f1", NULL),
 678         OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART1_BASE, "dev:f2", NULL),
 679         OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART2_BASE, "dev:f3", NULL),
 680         OF_DEV_AUXDATA("arm,primecell", VERSATILE_SSP_BASE, "dev:f4", NULL),
 681
 682 #if 0
 683         /*
 684          * These entries are unnecessary because no clocks referencing
 685          * them.  I've left them in for now as place holders in case
 686          * any of them need to be added back, but they should be
 687          * removed before actually committing this patch.  --gcl
 688          */
 689         OF_DEV_AUXDATA("arm,primecell", VERSATILE_AACI_BASE, "fpga:04", NULL),
 690         OF_DEV_AUXDATA("arm,primecell", VERSATILE_SCI1_BASE, "fpga:0a", NULL),
 691         OF_DEV_AUXDATA("arm,primecell", VERSATILE_SMC_BASE, "dev:00", NULL),
 692         OF_DEV_AUXDATA("arm,primecell", VERSATILE_MPMC_BASE, "dev:10", NULL),
 693         OF_DEV_AUXDATA("arm,primecell", VERSATILE_DMAC_BASE, "dev:30", NULL),
 694
 695         OF_DEV_AUXDATA("arm,primecell", VERSATILE_SCTL_BASE, "dev:e0", NULL),
 696         OF_DEV_AUXDATA("arm,primecell", VERSATILE_WATCHDOG_BASE, "dev:e1", NULL),
 697         OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO0_BASE, "dev:e4", NULL),
 698         OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO1_BASE, "dev:e5", NULL),
 699         OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO2_BASE, "dev:e6", NULL),
 700         OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO3_BASE, "dev:e7", NULL),
 701         OF_DEV_AUXDATA("arm,primecell", VERSATILE_RTC_BASE, "dev:e8", NULL),
 702         OF_DEV_AUXDATA("arm,primecell", VERSATILE_SCI_BASE, "dev:f0", NULL),
 703 #endif
 704         {}
 705 };
 706 #endif
 707
 708 #ifdef CONFIG_LEDS
 709 #define VA_LEDS_BASE (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
 710
 711 static void versatile_leds_event(led_event_t ledevt)
 712 {
 713         unsigned long flags;
 714         u32 val;
 715
 716         local_irq_save(flags);
 717         val = readl(VA_LEDS_BASE);
 718
 719         switch (ledevt) {
 720         case led_idle_start:
 721                 val = val & ~VERSATILE_SYS_LED0;
 722                 break;
 723
 724         case led_idle_end:
 725                 val = val | VERSATILE_SYS_LED0;
 726                 break;
 727
 728         case led_timer:
 729                 val = val ^ VERSATILE_SYS_LED1;
 730                 break;
 731
 732         case led_halted:
 733                 val = 0;
 734                 break;
 735
 736         default:
 737                 break;
 738         }
 739
 740         writel(val, VA_LEDS_BASE);
 741         local_irq_restore(flags);
 742 }
 743 #endif  /* CONFIG_LEDS */
 744
 745 void versatile_restart(char mode, const char *cmd)
 746 {
 747         void __iomem *sys = __io_address(VERSATILE_SYS_BASE);
 748         u32 val;
 749
 750         val = __raw_readl(sys + VERSATILE_SYS_RESETCTL_OFFSET);
 751         val |= 0x105;
 752
 753         __raw_writel(0xa05f, sys + VERSATILE_SYS_LOCK_OFFSET);
 754         __raw_writel(val, sys + VERSATILE_SYS_RESETCTL_OFFSET);
 755         __raw_writel(0, sys + VERSATILE_SYS_LOCK_OFFSET);
 756 }
 757
 758 /* Early initializations */
 759 void __init versatile_init_early(void)
 760 {
 761         void __iomem *sys = __io_address(VERSATILE_SYS_BASE);
 762
 763         osc4_clk.vcoreg = sys + VERSATILE_SYS_OSCCLCD_OFFSET;
 764         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 765
 766         versatile_sched_clock_init(sys + VERSATILE_SYS_24MHz_OFFSET, 24000000);
 767 }
 768
 769 void __init versatile_init(void)
 770 {
 771         int i;
 772
 773         platform_device_register(&versatile_flash_device);
 774         platform_device_register(&versatile_i2c_device);
 775         platform_device_register(&smc91x_device);
 776         platform_device_register(&char_lcd_device);
 777
 778         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
 779                 struct amba_device *d = amba_devs[i];
 780                 amba_device_register(d, &iomem_resource);
 781         }
 782
 783 #ifdef CONFIG_LEDS
 784         leds_event = versatile_leds_event;
 785 #endif
 786 }
 787
 788 /*
 789  * Where is the timer (VA)?
 790  */
 791 #define TIMER0_VA_BASE           __io_address(VERSATILE_TIMER0_1_BASE)
 792 #define TIMER1_VA_BASE          (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20)
 793 #define TIMER2_VA_BASE           __io_address(VERSATILE_TIMER2_3_BASE)
 794 #define TIMER3_VA_BASE          (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20)
 795
 796 /*
 797  * Set up timer interrupt, and return the current time in seconds.
 798  */
 799 static void __init versatile_timer_init(void)
 800 {
 801         u32 val;
 802
 803         /*
 804          * set clock frequency:
 805          *      VERSATILE_REFCLK is 32KHz
 806          *      VERSATILE_TIMCLK is 1MHz
 807          */
 808         val = readl(__io_address(VERSATILE_SCTL_BASE));
 809         writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
 810                (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
 811                (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
 812                (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
 813                __io_address(VERSATILE_SCTL_BASE));
 814
 815         /*
 816          * Initialise to a known state (all timers off)
 817          */
 818         writel(0, TIMER0_VA_BASE + TIMER_CTRL);
 819         writel(0, TIMER1_VA_BASE + TIMER_CTRL);
 820         writel(0, TIMER2_VA_BASE + TIMER_CTRL);
 821         writel(0, TIMER3_VA_BASE + TIMER_CTRL);
 822
 823         sp804_clocksource_init(TIMER3_VA_BASE, "timer3");
 824         sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMERINT0_1, "timer0");
 825 }
 826
 827 struct sys_timer versatile_timer = {
 828         .init           = versatile_timer_init,
 829 };
 830