2 * Copyright (C) 2009 ST-Ericsson.
4 * U8500 hardware definitions
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
10 #ifndef __MACH_HARDWARE_H
11 #define __MACH_HARDWARE_H
13 /* macros to get at IO space when running virtually
14 * We dont map all the peripherals, let ioremap do
15 * this for us. We map only very basic peripherals here.
17 #define U8500_IO_VIRTUAL 0xf0000000
18 #define U8500_IO_PHYSICAL 0xa0000000
20 /* this macro is used in assembly, so no cast */
21 #define IO_ADDRESS(x) \
22 (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + U8500_IO_VIRTUAL)
24 /* typesafe io address */
25 #define __io_address(n) __io(IO_ADDRESS(n))
26 /* used by some plat-nomadik code */
27 #define io_p2v(n) __io_address(n)
30 * Base address definitions for U8500 Onchip IPs. All the
31 * peripherals are contained in a single 1 Mbyte region, with
32 * AHB peripherals at the bottom and APB peripherals at the
33 * top of the region. PER stands for PERIPHERAL region which
34 * itself divided into sub regions.
36 #define U8500_PER3_BASE 0x80000000
37 #define U8500_PER2_BASE 0x80110000
38 #define U8500_PER1_BASE 0x80120000
39 #define U8500_PER4_BASE 0x80150000
41 #define U8500_PER6_BASE 0xa03c0000
42 #define U8500_PER5_BASE 0xa03e0000
43 #define U8500_PER7_BASE 0xa03d0000
45 #define U8500_SVA_BASE 0xa0100000
46 #define U8500_SIA_BASE 0xa0200000
48 #define U8500_SGA_BASE 0xa0300000
49 #define U8500_MCDE_BASE 0xa0350000
50 #define U8500_DMA_BASE 0xa0362000
52 #define U8500_SCU_BASE 0xa0410000
53 #define U8500_GIC_CPU_BASE 0xa0410100
54 #define U8500_TWD_BASE 0xa0410600
55 #define U8500_GIC_DIST_BASE 0xa0411000
56 #define U8500_L2CC_BASE 0xa0412000
58 #define U8500_TWD_SIZE 0x100
60 /* per7 base addressess */
61 #define U8500_CR_BASE_ED (U8500_PER7_BASE + 0x8000)
62 #define U8500_MTU0_BASE_ED (U8500_PER7_BASE + 0xa000)
63 #define U8500_MTU1_BASE_ED (U8500_PER7_BASE + 0xb000)
64 #define U8500_TZPC0_BASE_ED (U8500_PER7_BASE + 0xc000)
65 #define U8500_CLKRST7_BASE_ED (U8500_PER7_BASE + 0xf000)
67 /* per6 base addressess */
68 #define U8500_RNG_BASE (U8500_PER6_BASE + 0x0000)
69 #define U8500_PKA_BASE (U8500_PER6_BASE + 0x1000)
70 #define U8500_PKAM_BASE (U8500_PER6_BASE + 0x2000)
71 #define U8500_MTU0_BASE_V1 (U8500_PER6_BASE + 0x6000)
72 #define U8500_MTU1_BASE_V1 (U8500_PER6_BASE + 0x7000)
73 #define U8500_CR_BASE_V1 (U8500_PER6_BASE + 0x8000)
74 #define U8500_CRYPTO0_BASE (U8500_PER6_BASE + 0xa000)
75 #define U8500_CRYPTO1_BASE (U8500_PER6_BASE + 0xb000)
76 #define U8500_CLKRST6_BASE (U8500_PER6_BASE + 0xf000)
78 /* per5 base addressess */
79 #define U8500_USBOTG_BASE (U8500_PER5_BASE + 0x00000)
80 #define U8500_GPIO5_BASE (U8500_PER5_BASE + 0x1e000)
81 #define U8500_CLKRST5_BASE (U8500_PER5_BASE + 0x1f000)
83 /* per4 base addressess */
84 #define U8500_BACKUPRAM0_BASE (U8500_PER4_BASE + 0x0000)
85 #define U8500_BACKUPRAM1_BASE (U8500_PER4_BASE + 0x1000)
86 #define U8500_RTT0_BASE (U8500_PER4_BASE + 0x2000)
87 #define U8500_RTT1_BASE (U8500_PER4_BASE + 0x3000)
88 #define U8500_RTC_BASE (U8500_PER4_BASE + 0x4000)
89 #define U8500_SCR_BASE (U8500_PER4_BASE + 0x5000)
90 #define U8500_DMC_BASE (U8500_PER4_BASE + 0x6000)
91 #define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x7000)
93 /* per3 base addressess */
94 #define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000)
95 #define U8500_SSP0_BASE (U8500_PER3_BASE + 0x2000)
96 #define U8500_SSP1_BASE (U8500_PER3_BASE + 0x3000)
97 #define U8500_I2C0_BASE (U8500_PER3_BASE + 0x4000)
98 #define U8500_SDI2_BASE (U8500_PER3_BASE + 0x5000)
99 #define U8500_SKE_BASE (U8500_PER3_BASE + 0x6000)
100 #define U8500_UART2_BASE (U8500_PER3_BASE + 0x7000)
101 #define U8500_SDI5_BASE (U8500_PER3_BASE + 0x8000)
102 #define U8500_GPIO3_BASE (U8500_PER3_BASE + 0xe000)
103 #define U8500_CLKRST3_BASE (U8500_PER3_BASE + 0xf000)
105 /* per2 base addressess */
106 #define U8500_I2C3_BASE (U8500_PER2_BASE + 0x0000)
107 #define U8500_SPI2_BASE (U8500_PER2_BASE + 0x1000)
108 #define U8500_SPI1_BASE (U8500_PER2_BASE + 0x2000)
109 #define U8500_PWL_BASE (U8500_PER2_BASE + 0x3000)
110 #define U8500_SDI4_BASE (U8500_PER2_BASE + 0x4000)
111 #define U8500_MSP2_BASE (U8500_PER2_BASE + 0x7000)
112 #define U8500_SDI1_BASE (U8500_PER2_BASE + 0x8000)
113 #define U8500_SDI3_BASE (U8500_PER2_BASE + 0x9000)
114 #define U8500_SPI0_BASE (U8500_PER2_BASE + 0xa000)
115 #define U8500_HSIR_BASE (U8500_PER2_BASE + 0xb000)
116 #define U8500_HSIT_BASE (U8500_PER2_BASE + 0xc000)
117 #define U8500_GPIO2_BASE (U8500_PER2_BASE + 0xe000)
118 #define U8500_CLKRST2_BASE (U8500_PER2_BASE + 0xf000)
120 /* per1 base addresses */
121 #define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000)
122 #define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000)
123 #define U8500_I2C1_BASE (U8500_PER1_BASE + 0x2000)
124 #define U8500_MSP0_BASE (U8500_PER1_BASE + 0x3000)
125 #define U8500_MSP1_BASE (U8500_PER1_BASE + 0x4000)
126 #define U8500_SDI0_BASE (U8500_PER1_BASE + 0x6000)
127 #define U8500_I2C2_BASE (U8500_PER1_BASE + 0x8000)
128 #define U8500_SPI3_BASE (U8500_PER1_BASE + 0x9000)
129 #define U8500_SLIM0_BASE (U8500_PER1_BASE + 0xa000)
130 #define U8500_GPIO1_BASE (U8500_PER1_BASE + 0xe000)
131 #define U8500_CLKRST1_BASE (U8500_PER1_BASE + 0xf000)
133 #define U8500_GPIOBANK0_BASE U8500_GPIO1_BASE
134 #define U8500_GPIOBANK1_BASE (U8500_GPIO1_BASE + 0x80)
135 #define U8500_GPIOBANK2_BASE U8500_GPIO3_BASE
136 #define U8500_GPIOBANK3_BASE (U8500_GPIO3_BASE + 0x80)
137 #define U8500_GPIOBANK4_BASE (U8500_GPIO3_BASE + 0x100)
138 #define U8500_GPIOBANK5_BASE (U8500_GPIO3_BASE + 0x180)
139 #define U8500_GPIOBANK6_BASE U8500_GPIO2_BASE
140 #define U8500_GPIOBANK7_BASE (U8500_GPIO2_BASE + 0x80)
141 #define U8500_GPIOBANK8_BASE U8500_GPIO5_BASE
143 /* ST-Ericsson modified pl022 id */
144 #define SSP_PER_ID 0x01080022
148 #include <asm/cputype.h>
150 static inline bool cpu_is_u8500ed(void)
152 return (read_cpuid_id() & 15) == 0;
155 static inline bool cpu_is_u8500v1(void)
157 return (read_cpuid_id() & 15) == 1;
162 #endif /* __MACH_HARDWARE_H */