2 * Copyright (C) ST-Ericsson SA 2010
4 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
5 * License terms: GNU General Public License (GPL) version 2
8 #include <linux/platform_device.h>
10 #include <linux/clk.h>
11 #include <linux/mfd/db8500-prcmu.h>
12 #include <linux/mfd/db5500-prcmu.h>
14 #include <asm/cacheflush.h>
15 #include <asm/hardware/cache-l2x0.h>
16 #include <asm/hardware/gic.h>
17 #include <asm/mach/map.h>
18 #include <asm/localtimer.h>
21 #include <mach/hardware.h>
22 #include <mach/setup.h>
23 #include <mach/devices.h>
27 void __iomem *_PRCMU_BASE;
29 #ifdef CONFIG_CACHE_L2X0
30 static void __iomem *l2x0_base;
33 void __init ux500_init_irq(void)
35 void __iomem *dist_base;
36 void __iomem *cpu_base;
39 dist_base = __io_address(U5500_GIC_DIST_BASE);
40 cpu_base = __io_address(U5500_GIC_CPU_BASE);
41 } else if (cpu_is_u8500()) {
42 dist_base = __io_address(U8500_GIC_DIST_BASE);
43 cpu_base = __io_address(U8500_GIC_CPU_BASE);
47 gic_init(0, 29, dist_base, cpu_base);
50 * Init clocks here so that they are available for system timer
54 db5500_prcmu_early_init();
60 #ifdef CONFIG_CACHE_L2X0
61 static inline void ux500_cache_wait(void __iomem *reg, unsigned long mask)
63 /* wait for the operation to complete */
64 while (readl_relaxed(reg) & mask)
68 static inline void ux500_cache_sync(void)
70 void __iomem *base = l2x0_base;
72 writel_relaxed(0, base + L2X0_CACHE_SYNC);
73 ux500_cache_wait(base + L2X0_CACHE_SYNC, 1);
77 * The L2 cache cannot be turned off in the non-secure world.
78 * Dummy until a secure service is in place.
80 static void ux500_l2x0_disable(void)
85 * This is only called when doing a kexec, just after turning off the L2
86 * and L1 cache, and it is surrounded by a spinlock in the generic version.
87 * However, we're not really turning off the L2 cache right now and the
88 * PL310 does not support exclusive accesses (used to implement the spinlock).
89 * So, the invalidation needs to be done without the spinlock.
91 static void ux500_l2x0_inv_all(void)
93 void __iomem *base = l2x0_base;
94 uint32_t l2x0_way_mask = (1<<16) - 1; /* Bitmask of active ways */
96 /* invalidate all ways */
97 writel_relaxed(l2x0_way_mask, base + L2X0_INV_WAY);
98 ux500_cache_wait(base + L2X0_INV_WAY, l2x0_way_mask);
102 static int ux500_l2x0_init(void)
105 l2x0_base = __io_address(U5500_L2CC_BASE);
106 else if (cpu_is_u8500())
107 l2x0_base = __io_address(U8500_L2CC_BASE);
111 /* 64KB way size, 8 way associativity, force WA */
112 l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff);
114 /* Override invalidate function */
115 outer_cache.disable = ux500_l2x0_disable;
116 outer_cache.inv_all = ux500_l2x0_inv_all;
120 early_initcall(ux500_l2x0_init);
123 static void __init ux500_timer_init(void)
125 #ifdef CONFIG_LOCAL_TIMERS
126 /* Setup the local timer base */
128 twd_base = __io_address(U5500_TWD_BASE);
129 else if (cpu_is_u8500())
130 twd_base = __io_address(U8500_TWD_BASE);
135 mtu_base = __io_address(U5500_MTU0_BASE);
136 else if (cpu_is_u8500ed())
137 mtu_base = __io_address(U8500_MTU0_BASE_ED);
138 else if (cpu_is_u8500())
139 mtu_base = __io_address(U8500_MTU0_BASE);
146 struct sys_timer ux500_timer = {
147 .init = ux500_timer_init,