arch/arm/mach-u300/core.c

   1 /*
   2  *
   3  * arch/arm/mach-u300/core.c
   4  *
   5  *
   6  * Copyright (C) 2007-2010 ST-Ericsson SA
   7  * License terms: GNU General Public License (GPL) version 2
   8  * Core platform support, IRQ handling and device definitions.
   9  * Author: Linus Walleij <linus.walleij@stericsson.com>
  10  */
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/spinlock.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/bitops.h>
  16 #include <linux/device.h>
  17 #include <linux/mm.h>
  18 #include <linux/termios.h>
  19 #include <linux/dmaengine.h>
  20 #include <linux/amba/bus.h>
  21 #include <linux/amba/serial.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/gpio.h>
  24 #include <linux/clk.h>
  25 #include <linux/err.h>
  26 #include <linux/mtd/nand.h>
  27 #include <linux/mtd/fsmc.h>
  28
  29 #include <asm/types.h>
  30 #include <asm/setup.h>
  31 #include <asm/memory.h>
  32 #include <asm/hardware/vic.h>
  33 #include <asm/mach/map.h>
  34 #include <asm/mach/irq.h>
  35
  36 #include <mach/coh901318.h>
  37 #include <mach/hardware.h>
  38 #include <mach/syscon.h>
  39 #include <mach/dma_channels.h>
  40 #include <mach/gpio-u300.h>
  41
  42 #include "clock.h"
  43 #include "mmc.h"
  44 #include "spi.h"
  45 #include "i2c.h"
  46
  47 /*
  48  * Static I/O mappings that are needed for booting the U300 platforms. The
  49  * only things we need are the areas where we find the timer, syscon and
  50  * intcon, since the remaining device drivers will map their own memory
  51  * physical to virtual as the need arise.
  52  */
  53 static struct map_desc u300_io_desc[] __initdata = {
  54         {
  55                 .virtual        = U300_SLOW_PER_VIRT_BASE,
  56                 .pfn            = __phys_to_pfn(U300_SLOW_PER_PHYS_BASE),
  57                 .length         = SZ_64K,
  58                 .type           = MT_DEVICE,
  59         },
  60         {
  61                 .virtual        = U300_AHB_PER_VIRT_BASE,
  62                 .pfn            = __phys_to_pfn(U300_AHB_PER_PHYS_BASE),
  63                 .length         = SZ_32K,
  64                 .type           = MT_DEVICE,
  65         },
  66         {
  67                 .virtual        = U300_FAST_PER_VIRT_BASE,
  68                 .pfn            = __phys_to_pfn(U300_FAST_PER_PHYS_BASE),
  69                 .length         = SZ_32K,
  70                 .type           = MT_DEVICE,
  71         },
  72         {
  73                 .virtual        = 0xffff2000, /* TCM memory */
  74                 .pfn            = __phys_to_pfn(0xffff2000),
  75                 .length         = SZ_16K,
  76                 .type           = MT_DEVICE,
  77         },
  78
  79         /*
  80          * This overlaps with the IRQ vectors etc at 0xffff0000, so these
  81          * may have to be moved to 0x00000000 in order to use the ROM.
  82          */
  83         /*
  84         {
  85                 .virtual        = U300_BOOTROM_VIRT_BASE,
  86                 .pfn            = __phys_to_pfn(U300_BOOTROM_PHYS_BASE),
  87                 .length         = SZ_64K,
  88                 .type           = MT_ROM,
  89         },
  90         */
  91 };
  92
  93 void __init u300_map_io(void)
  94 {
  95         iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc));
  96 }
  97
  98 /*
  99  * Declaration of devices found on the U300 board and
 100  * their respective memory locations.
 101  */
 102
 103 static struct amba_pl011_data uart0_plat_data = {
 104 #ifdef CONFIG_COH901318
 105         .dma_filter = coh901318_filter_id,
 106         .dma_rx_param = (void *) U300_DMA_UART0_RX,
 107         .dma_tx_param = (void *) U300_DMA_UART0_TX,
 108 #endif
 109 };
 110
 111 static struct amba_device uart0_device = {
 112         .dev = {
 113                 .coherent_dma_mask = ~0,
 114                 .init_name = "uart0", /* Slow device at 0x3000 offset */
 115                 .platform_data = &uart0_plat_data,
 116         },
 117         .res = {
 118                 .start = U300_UART0_BASE,
 119                 .end   = U300_UART0_BASE + SZ_4K - 1,
 120                 .flags = IORESOURCE_MEM,
 121         },
 122         .irq = { IRQ_U300_UART0, NO_IRQ },
 123 };
 124
 125 /* The U335 have an additional UART1 on the APP CPU */
 126 #ifdef CONFIG_MACH_U300_BS335
 127 static struct amba_pl011_data uart1_plat_data = {
 128 #ifdef CONFIG_COH901318
 129         .dma_filter = coh901318_filter_id,
 130         .dma_rx_param = (void *) U300_DMA_UART1_RX,
 131         .dma_tx_param = (void *) U300_DMA_UART1_TX,
 132 #endif
 133 };
 134
 135 static struct amba_device uart1_device = {
 136         .dev = {
 137                 .coherent_dma_mask = ~0,
 138                 .init_name = "uart1", /* Fast device at 0x7000 offset */
 139                 .platform_data = &uart1_plat_data,
 140         },
 141         .res = {
 142                 .start = U300_UART1_BASE,
 143                 .end   = U300_UART1_BASE + SZ_4K - 1,
 144                 .flags = IORESOURCE_MEM,
 145         },
 146         .irq = { IRQ_U300_UART1, NO_IRQ },
 147 };
 148 #endif
 149
 150 static struct amba_device pl172_device = {
 151         .dev = {
 152                 .init_name = "pl172", /* AHB device at 0x4000 offset */
 153                 .platform_data = NULL,
 154         },
 155         .res = {
 156                 .start = U300_EMIF_CFG_BASE,
 157                 .end   = U300_EMIF_CFG_BASE + SZ_4K - 1,
 158                 .flags = IORESOURCE_MEM,
 159         },
 160 };
 161
 162
 163 /*
 164  * Everything within this next ifdef deals with external devices connected to
 165  * the APP SPI bus.
 166  */
 167 static struct amba_device pl022_device = {
 168         .dev = {
 169                 .coherent_dma_mask = ~0,
 170                 .init_name = "pl022", /* Fast device at 0x6000 offset */
 171         },
 172         .res = {
 173                 .start = U300_SPI_BASE,
 174                 .end   = U300_SPI_BASE + SZ_4K - 1,
 175                 .flags = IORESOURCE_MEM,
 176         },
 177         .irq = {IRQ_U300_SPI, NO_IRQ },
 178         /*
 179          * This device has a DMA channel but the Linux driver does not use
 180          * it currently.
 181          */
 182 };
 183
 184 static struct amba_device mmcsd_device = {
 185         .dev = {
 186                 .init_name = "mmci", /* Fast device at 0x1000 offset */
 187                 .platform_data = NULL, /* Added later */
 188         },
 189         .res = {
 190                 .start = U300_MMCSD_BASE,
 191                 .end   = U300_MMCSD_BASE + SZ_4K - 1,
 192                 .flags = IORESOURCE_MEM,
 193         },
 194         .irq = {IRQ_U300_MMCSD_MCIINTR0, IRQ_U300_MMCSD_MCIINTR1 },
 195         /*
 196          * This device has a DMA channel but the Linux driver does not use
 197          * it currently.
 198          */
 199 };
 200
 201 /*
 202  * The order of device declaration may be important, since some devices
 203  * have dependencies on other devices being initialized first.
 204  */
 205 static struct amba_device *amba_devs[] __initdata = {
 206         &uart0_device,
 207 #ifdef CONFIG_MACH_U300_BS335
 208         &uart1_device,
 209 #endif
 210         &pl022_device,
 211         &pl172_device,
 212         &mmcsd_device,
 213 };
 214
 215 /* Here follows a list of all hw resources that the platform devices
 216  * allocate. Note, clock dependencies are not included
 217  */
 218
 219 static struct resource gpio_resources[] = {
 220         {
 221                 .start = U300_GPIO_BASE,
 222                 .end   = (U300_GPIO_BASE + SZ_4K - 1),
 223                 .flags = IORESOURCE_MEM,
 224         },
 225         {
 226                 .name  = "gpio0",
 227                 .start = IRQ_U300_GPIO_PORT0,
 228                 .end   = IRQ_U300_GPIO_PORT0,
 229                 .flags = IORESOURCE_IRQ,
 230         },
 231         {
 232                 .name  = "gpio1",
 233                 .start = IRQ_U300_GPIO_PORT1,
 234                 .end   = IRQ_U300_GPIO_PORT1,
 235                 .flags = IORESOURCE_IRQ,
 236         },
 237         {
 238                 .name  = "gpio2",
 239                 .start = IRQ_U300_GPIO_PORT2,
 240                 .end   = IRQ_U300_GPIO_PORT2,
 241                 .flags = IORESOURCE_IRQ,
 242         },
 243 #if defined(CONFIG_MACH_U300_BS365) || defined(CONFIG_MACH_U300_BS335)
 244         {
 245                 .name  = "gpio3",
 246                 .start = IRQ_U300_GPIO_PORT3,
 247                 .end   = IRQ_U300_GPIO_PORT3,
 248                 .flags = IORESOURCE_IRQ,
 249         },
 250         {
 251                 .name  = "gpio4",
 252                 .start = IRQ_U300_GPIO_PORT4,
 253                 .end   = IRQ_U300_GPIO_PORT4,
 254                 .flags = IORESOURCE_IRQ,
 255         },
 256 #endif
 257 #ifdef CONFIG_MACH_U300_BS335
 258         {
 259                 .name  = "gpio5",
 260                 .start = IRQ_U300_GPIO_PORT5,
 261                 .end   = IRQ_U300_GPIO_PORT5,
 262                 .flags = IORESOURCE_IRQ,
 263         },
 264         {
 265                 .name  = "gpio6",
 266                 .start = IRQ_U300_GPIO_PORT6,
 267                 .end   = IRQ_U300_GPIO_PORT6,
 268                 .flags = IORESOURCE_IRQ,
 269         },
 270 #endif /* CONFIG_MACH_U300_BS335 */
 271 };
 272
 273 static struct resource keypad_resources[] = {
 274         {
 275                 .start = U300_KEYPAD_BASE,
 276                 .end   = U300_KEYPAD_BASE + SZ_4K - 1,
 277                 .flags = IORESOURCE_MEM,
 278         },
 279         {
 280                 .name  = "coh901461-press",
 281                 .start = IRQ_U300_KEYPAD_KEYBF,
 282                 .end   = IRQ_U300_KEYPAD_KEYBF,
 283                 .flags = IORESOURCE_IRQ,
 284         },
 285         {
 286                 .name  = "coh901461-release",
 287                 .start = IRQ_U300_KEYPAD_KEYBR,
 288                 .end   = IRQ_U300_KEYPAD_KEYBR,
 289                 .flags = IORESOURCE_IRQ,
 290         },
 291 };
 292
 293 static struct resource rtc_resources[] = {
 294         {
 295                 .start = U300_RTC_BASE,
 296                 .end   = U300_RTC_BASE + SZ_4K - 1,
 297                 .flags = IORESOURCE_MEM,
 298         },
 299         {
 300                 .start = IRQ_U300_RTC,
 301                 .end   = IRQ_U300_RTC,
 302                 .flags = IORESOURCE_IRQ,
 303         },
 304 };
 305
 306 /*
 307  * Fsmc does have IRQs: #43 and #44 (NFIF and NFIF2)
 308  * but these are not yet used by the driver.
 309  */
 310 static struct resource fsmc_resources[] = {
 311         {
 312                 .name  = "nand_data",
 313                 .start = U300_NAND_CS0_PHYS_BASE,
 314                 .end   = U300_NAND_CS0_PHYS_BASE + SZ_16K - 1,
 315                 .flags = IORESOURCE_MEM,
 316         },
 317         {
 318                 .name  = "fsmc_regs",
 319                 .start = U300_NAND_IF_PHYS_BASE,
 320                 .end   = U300_NAND_IF_PHYS_BASE + SZ_4K - 1,
 321                 .flags = IORESOURCE_MEM,
 322         },
 323 };
 324
 325 static struct resource i2c0_resources[] = {
 326         {
 327                 .start = U300_I2C0_BASE,
 328                 .end   = U300_I2C0_BASE + SZ_4K - 1,
 329                 .flags = IORESOURCE_MEM,
 330         },
 331         {
 332                 .start = IRQ_U300_I2C0,
 333                 .end   = IRQ_U300_I2C0,
 334                 .flags = IORESOURCE_IRQ,
 335         },
 336 };
 337
 338 static struct resource i2c1_resources[] = {
 339         {
 340                 .start = U300_I2C1_BASE,
 341                 .end   = U300_I2C1_BASE + SZ_4K - 1,
 342                 .flags = IORESOURCE_MEM,
 343         },
 344         {
 345                 .start = IRQ_U300_I2C1,
 346                 .end   = IRQ_U300_I2C1,
 347                 .flags = IORESOURCE_IRQ,
 348         },
 349
 350 };
 351
 352 static struct resource wdog_resources[] = {
 353         {
 354                 .start = U300_WDOG_BASE,
 355                 .end   = U300_WDOG_BASE + SZ_4K - 1,
 356                 .flags = IORESOURCE_MEM,
 357         },
 358         {
 359                 .start = IRQ_U300_WDOG,
 360                 .end   = IRQ_U300_WDOG,
 361                 .flags = IORESOURCE_IRQ,
 362         }
 363 };
 364
 365 /* TODO: These should be protected by suitable #ifdef's */
 366 static struct resource ave_resources[] = {
 367         {
 368                 .name  = "AVE3e I/O Area",
 369                 .start = U300_VIDEOENC_BASE,
 370                 .end   = U300_VIDEOENC_BASE + SZ_512K - 1,
 371                 .flags = IORESOURCE_MEM,
 372         },
 373         {
 374                 .name  = "AVE3e IRQ0",
 375                 .start = IRQ_U300_VIDEO_ENC_0,
 376                 .end   = IRQ_U300_VIDEO_ENC_0,
 377                 .flags = IORESOURCE_IRQ,
 378         },
 379         {
 380                 .name  = "AVE3e IRQ1",
 381                 .start = IRQ_U300_VIDEO_ENC_1,
 382                 .end   = IRQ_U300_VIDEO_ENC_1,
 383                 .flags = IORESOURCE_IRQ,
 384         },
 385         {
 386                 .name  = "AVE3e Physmem Area",
 387                 .start = 0, /* 0 will be remapped to reserved memory */
 388                 .end   = SZ_1M - 1,
 389                 .flags = IORESOURCE_MEM,
 390         },
 391         /*
 392          * The AVE3e requires two regions of 256MB that it considers
 393          * "invisible". The hardware will not be able to access these
 394          * addresses, so they should never point to system RAM.
 395          */
 396         {
 397                 .name  = "AVE3e Reserved 0",
 398                 .start = 0xd0000000,
 399                 .end   = 0xd0000000 + SZ_256M - 1,
 400                 .flags = IORESOURCE_MEM,
 401         },
 402         {
 403                 .name  = "AVE3e Reserved 1",
 404                 .start = 0xe0000000,
 405                 .end   = 0xe0000000 + SZ_256M - 1,
 406                 .flags = IORESOURCE_MEM,
 407         },
 408 };
 409
 410 static struct resource dma_resource[] = {
 411         {
 412                 .start = U300_DMAC_BASE,
 413                 .end = U300_DMAC_BASE + PAGE_SIZE - 1,
 414                 .flags =  IORESOURCE_MEM,
 415         },
 416         {
 417                 .start = IRQ_U300_DMA,
 418                 .end = IRQ_U300_DMA,
 419                 .flags =  IORESOURCE_IRQ,
 420         }
 421 };
 422
 423 #ifdef CONFIG_MACH_U300_BS335
 424 /* points out all dma slave channels.
 425  * Syntax is [A1, B1, A2, B2, .... ,-1,-1]
 426  * Select all channels from A to B, end of list is marked with -1,-1
 427  */
 428 static int dma_slave_channels[] = {
 429         U300_DMA_MSL_TX_0, U300_DMA_SPI_RX,
 430         U300_DMA_UART1_TX, U300_DMA_UART1_RX, -1, -1};
 431
 432 /* points out all dma memcpy channels. */
 433 static int dma_memcpy_channels[] = {
 434         U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1};
 435
 436 #else /* CONFIG_MACH_U300_BS335 */
 437
 438 static int dma_slave_channels[] = {U300_DMA_MSL_TX_0, U300_DMA_SPI_RX, -1, -1};
 439 static int dma_memcpy_channels[] = {
 440         U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_10, -1, -1};
 441
 442 #endif
 443
 444 /** register dma for memory access
 445  *
 446  * active  1 means dma intends to access memory
 447  *         0 means dma wont access memory
 448  */
 449 static void coh901318_access_memory_state(struct device *dev, bool active)
 450 {
 451 }
 452
 453 #define flags_memcpy_config (COH901318_CX_CFG_CH_DISABLE | \
 454                         COH901318_CX_CFG_RM_MEMORY_TO_MEMORY | \
 455                         COH901318_CX_CFG_LCR_DISABLE | \
 456                         COH901318_CX_CFG_TC_IRQ_ENABLE | \
 457                         COH901318_CX_CFG_BE_IRQ_ENABLE)
 458 #define flags_memcpy_lli_chained (COH901318_CX_CTRL_TC_ENABLE | \
 459                         COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
 460                         COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
 461                         COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
 462                         COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
 463                         COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
 464                         COH901318_CX_CTRL_MASTER_MODE_M1RW | \
 465                         COH901318_CX_CTRL_TCP_DISABLE | \
 466                         COH901318_CX_CTRL_TC_IRQ_DISABLE | \
 467                         COH901318_CX_CTRL_HSP_DISABLE | \
 468                         COH901318_CX_CTRL_HSS_DISABLE | \
 469                         COH901318_CX_CTRL_DDMA_LEGACY | \
 470                         COH901318_CX_CTRL_PRDD_SOURCE)
 471 #define flags_memcpy_lli (COH901318_CX_CTRL_TC_ENABLE | \
 472                         COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
 473                         COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
 474                         COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
 475                         COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
 476                         COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
 477                         COH901318_CX_CTRL_MASTER_MODE_M1RW | \
 478                         COH901318_CX_CTRL_TCP_DISABLE | \
 479                         COH901318_CX_CTRL_TC_IRQ_DISABLE | \
 480                         COH901318_CX_CTRL_HSP_DISABLE | \
 481                         COH901318_CX_CTRL_HSS_DISABLE | \
 482                         COH901318_CX_CTRL_DDMA_LEGACY | \
 483                         COH901318_CX_CTRL_PRDD_SOURCE)
 484 #define flags_memcpy_lli_last (COH901318_CX_CTRL_TC_ENABLE | \
 485                         COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
 486                         COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
 487                         COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
 488                         COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
 489                         COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
 490                         COH901318_CX_CTRL_MASTER_MODE_M1RW | \
 491                         COH901318_CX_CTRL_TCP_DISABLE | \
 492                         COH901318_CX_CTRL_TC_IRQ_ENABLE | \
 493                         COH901318_CX_CTRL_HSP_DISABLE | \
 494                         COH901318_CX_CTRL_HSS_DISABLE | \
 495                         COH901318_CX_CTRL_DDMA_LEGACY | \
 496                         COH901318_CX_CTRL_PRDD_SOURCE)
 497
 498 const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
 499         {
 500                 .number = U300_DMA_MSL_TX_0,
 501                 .name = "MSL TX 0",
 502                 .priority_high = 0,
 503                 .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x20,
 504         },
 505         {
 506                 .number = U300_DMA_MSL_TX_1,
 507                 .name = "MSL TX 1",
 508                 .priority_high = 0,
 509                 .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x20,
 510                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 511                                 COH901318_CX_CFG_LCR_DISABLE |
 512                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 513                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 514                 .param.ctrl_lli_chained = 0 |
 515                                 COH901318_CX_CTRL_TC_ENABLE |
 516                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 517                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 518                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 519                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 520                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 521                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 522                                 COH901318_CX_CTRL_TCP_DISABLE |
 523                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 524                                 COH901318_CX_CTRL_HSP_ENABLE |
 525                                 COH901318_CX_CTRL_HSS_DISABLE |
 526                                 COH901318_CX_CTRL_DDMA_LEGACY |
 527                                 COH901318_CX_CTRL_PRDD_SOURCE,
 528                 .param.ctrl_lli = 0 |
 529                                 COH901318_CX_CTRL_TC_ENABLE |
 530                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 531                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 532                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 533                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 534                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 535                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 536                                 COH901318_CX_CTRL_TCP_ENABLE |
 537                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 538                                 COH901318_CX_CTRL_HSP_ENABLE |
 539                                 COH901318_CX_CTRL_HSS_DISABLE |
 540                                 COH901318_CX_CTRL_DDMA_LEGACY |
 541                                 COH901318_CX_CTRL_PRDD_SOURCE,
 542                 .param.ctrl_lli_last = 0 |
 543                                 COH901318_CX_CTRL_TC_ENABLE |
 544                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 545                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 546                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 547                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 548                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 549                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 550                                 COH901318_CX_CTRL_TCP_ENABLE |
 551                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 552                                 COH901318_CX_CTRL_HSP_ENABLE |
 553                                 COH901318_CX_CTRL_HSS_DISABLE |
 554                                 COH901318_CX_CTRL_DDMA_LEGACY |
 555                                 COH901318_CX_CTRL_PRDD_SOURCE,
 556         },
 557         {
 558                 .number = U300_DMA_MSL_TX_2,
 559                 .name = "MSL TX 2",
 560                 .priority_high = 0,
 561                 .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x20,
 562                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 563                                 COH901318_CX_CFG_LCR_DISABLE |
 564                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 565                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 566                 .param.ctrl_lli_chained = 0 |
 567                                 COH901318_CX_CTRL_TC_ENABLE |
 568                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 569                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 570                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 571                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 572                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 573                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 574                                 COH901318_CX_CTRL_TCP_DISABLE |
 575                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 576                                 COH901318_CX_CTRL_HSP_ENABLE |
 577                                 COH901318_CX_CTRL_HSS_DISABLE |
 578                                 COH901318_CX_CTRL_DDMA_LEGACY |
 579                                 COH901318_CX_CTRL_PRDD_SOURCE,
 580                 .param.ctrl_lli = 0 |
 581                                 COH901318_CX_CTRL_TC_ENABLE |
 582                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 583                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 584                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 585                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 586                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 587                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 588                                 COH901318_CX_CTRL_TCP_ENABLE |
 589                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 590                                 COH901318_CX_CTRL_HSP_ENABLE |
 591                                 COH901318_CX_CTRL_HSS_DISABLE |
 592                                 COH901318_CX_CTRL_DDMA_LEGACY |
 593                                 COH901318_CX_CTRL_PRDD_SOURCE,
 594                 .param.ctrl_lli_last = 0 |
 595                                 COH901318_CX_CTRL_TC_ENABLE |
 596                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 597                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 598                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 599                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 600                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 601                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 602                                 COH901318_CX_CTRL_TCP_ENABLE |
 603                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 604                                 COH901318_CX_CTRL_HSP_ENABLE |
 605                                 COH901318_CX_CTRL_HSS_DISABLE |
 606                                 COH901318_CX_CTRL_DDMA_LEGACY |
 607                                 COH901318_CX_CTRL_PRDD_SOURCE,
 608                 .desc_nbr_max = 10,
 609         },
 610         {
 611                 .number = U300_DMA_MSL_TX_3,
 612                 .name = "MSL TX 3",
 613                 .priority_high = 0,
 614                 .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x20,
 615                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 616                                 COH901318_CX_CFG_LCR_DISABLE |
 617                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 618                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 619                 .param.ctrl_lli_chained = 0 |
 620                                 COH901318_CX_CTRL_TC_ENABLE |
 621                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 622                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 623                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 624                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 625                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 626                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 627                                 COH901318_CX_CTRL_TCP_DISABLE |
 628                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 629                                 COH901318_CX_CTRL_HSP_ENABLE |
 630                                 COH901318_CX_CTRL_HSS_DISABLE |
 631                                 COH901318_CX_CTRL_DDMA_LEGACY |
 632                                 COH901318_CX_CTRL_PRDD_SOURCE,
 633                 .param.ctrl_lli = 0 |
 634                                 COH901318_CX_CTRL_TC_ENABLE |
 635                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 636                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 637                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 638                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 639                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 640                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 641                                 COH901318_CX_CTRL_TCP_ENABLE |
 642                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 643                                 COH901318_CX_CTRL_HSP_ENABLE |
 644                                 COH901318_CX_CTRL_HSS_DISABLE |
 645                                 COH901318_CX_CTRL_DDMA_LEGACY |
 646                                 COH901318_CX_CTRL_PRDD_SOURCE,
 647                 .param.ctrl_lli_last = 0 |
 648                                 COH901318_CX_CTRL_TC_ENABLE |
 649                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 650                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 651                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 652                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 653                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 654                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 655                                 COH901318_CX_CTRL_TCP_ENABLE |
 656                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 657                                 COH901318_CX_CTRL_HSP_ENABLE |
 658                                 COH901318_CX_CTRL_HSS_DISABLE |
 659                                 COH901318_CX_CTRL_DDMA_LEGACY |
 660                                 COH901318_CX_CTRL_PRDD_SOURCE,
 661         },
 662         {
 663                 .number = U300_DMA_MSL_TX_4,
 664                 .name = "MSL TX 4",
 665                 .priority_high = 0,
 666                 .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x20,
 667                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 668                                 COH901318_CX_CFG_LCR_DISABLE |
 669                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 670                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 671                 .param.ctrl_lli_chained = 0 |
 672                                 COH901318_CX_CTRL_TC_ENABLE |
 673                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 674                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 675                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 676                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 677                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 678                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 679                                 COH901318_CX_CTRL_TCP_DISABLE |
 680                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 681                                 COH901318_CX_CTRL_HSP_ENABLE |
 682                                 COH901318_CX_CTRL_HSS_DISABLE |
 683                                 COH901318_CX_CTRL_DDMA_LEGACY |
 684                                 COH901318_CX_CTRL_PRDD_SOURCE,
 685                 .param.ctrl_lli = 0 |
 686                                 COH901318_CX_CTRL_TC_ENABLE |
 687                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 688                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 689                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 690                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 691                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 692                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 693                                 COH901318_CX_CTRL_TCP_ENABLE |
 694                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 695                                 COH901318_CX_CTRL_HSP_ENABLE |
 696                                 COH901318_CX_CTRL_HSS_DISABLE |
 697                                 COH901318_CX_CTRL_DDMA_LEGACY |
 698                                 COH901318_CX_CTRL_PRDD_SOURCE,
 699                 .param.ctrl_lli_last = 0 |
 700                                 COH901318_CX_CTRL_TC_ENABLE |
 701                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 702                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 703                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 704                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 705                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 706                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 707                                 COH901318_CX_CTRL_TCP_ENABLE |
 708                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 709                                 COH901318_CX_CTRL_HSP_ENABLE |
 710                                 COH901318_CX_CTRL_HSS_DISABLE |
 711                                 COH901318_CX_CTRL_DDMA_LEGACY |
 712                                 COH901318_CX_CTRL_PRDD_SOURCE,
 713         },
 714         {
 715                 .number = U300_DMA_MSL_TX_5,
 716                 .name = "MSL TX 5",
 717                 .priority_high = 0,
 718                 .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x20,
 719         },
 720         {
 721                 .number = U300_DMA_MSL_TX_6,
 722                 .name = "MSL TX 6",
 723                 .priority_high = 0,
 724                 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x20,
 725         },
 726         {
 727                 .number = U300_DMA_MSL_RX_0,
 728                 .name = "MSL RX 0",
 729                 .priority_high = 0,
 730                 .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x220,
 731         },
 732         {
 733                 .number = U300_DMA_MSL_RX_1,
 734                 .name = "MSL RX 1",
 735                 .priority_high = 0,
 736                 .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x220,
 737                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 738                                 COH901318_CX_CFG_LCR_DISABLE |
 739                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 740                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 741                 .param.ctrl_lli_chained = 0 |
 742                                 COH901318_CX_CTRL_TC_ENABLE |
 743                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 744                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 745                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 746                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 747                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 748                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 749                                 COH901318_CX_CTRL_TCP_DISABLE |
 750                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 751                                 COH901318_CX_CTRL_HSP_ENABLE |
 752                                 COH901318_CX_CTRL_HSS_DISABLE |
 753                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 754                                 COH901318_CX_CTRL_PRDD_DEST,
 755                 .param.ctrl_lli = 0,
 756                 .param.ctrl_lli_last = 0 |
 757                                 COH901318_CX_CTRL_TC_ENABLE |
 758                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 759                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 760                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 761                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 762                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 763                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 764                                 COH901318_CX_CTRL_TCP_DISABLE |
 765                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 766                                 COH901318_CX_CTRL_HSP_ENABLE |
 767                                 COH901318_CX_CTRL_HSS_DISABLE |
 768                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 769                                 COH901318_CX_CTRL_PRDD_DEST,
 770         },
 771         {
 772                 .number = U300_DMA_MSL_RX_2,
 773                 .name = "MSL RX 2",
 774                 .priority_high = 0,
 775                 .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x220,
 776                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 777                                 COH901318_CX_CFG_LCR_DISABLE |
 778                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 779                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 780                 .param.ctrl_lli_chained = 0 |
 781                                 COH901318_CX_CTRL_TC_ENABLE |
 782                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 783                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 784                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 785                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 786                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 787                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 788                                 COH901318_CX_CTRL_TCP_DISABLE |
 789                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 790                                 COH901318_CX_CTRL_HSP_ENABLE |
 791                                 COH901318_CX_CTRL_HSS_DISABLE |
 792                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 793                                 COH901318_CX_CTRL_PRDD_DEST,
 794                 .param.ctrl_lli = 0 |
 795                                 COH901318_CX_CTRL_TC_ENABLE |
 796                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 797                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 798                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 799                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 800                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 801                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 802                                 COH901318_CX_CTRL_TCP_DISABLE |
 803                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 804                                 COH901318_CX_CTRL_HSP_ENABLE |
 805                                 COH901318_CX_CTRL_HSS_DISABLE |
 806                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 807                                 COH901318_CX_CTRL_PRDD_DEST,
 808                 .param.ctrl_lli_last = 0 |
 809                                 COH901318_CX_CTRL_TC_ENABLE |
 810                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 811                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 812                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 813                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 814                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 815                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 816                                 COH901318_CX_CTRL_TCP_DISABLE |
 817                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 818                                 COH901318_CX_CTRL_HSP_ENABLE |
 819                                 COH901318_CX_CTRL_HSS_DISABLE |
 820                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 821                                 COH901318_CX_CTRL_PRDD_DEST,
 822         },
 823         {
 824                 .number = U300_DMA_MSL_RX_3,
 825                 .name = "MSL RX 3",
 826                 .priority_high = 0,
 827                 .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x220,
 828                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 829                                 COH901318_CX_CFG_LCR_DISABLE |
 830                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 831                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 832                 .param.ctrl_lli_chained = 0 |
 833                                 COH901318_CX_CTRL_TC_ENABLE |
 834                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 835                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 836                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 837                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 838                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 839                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 840                                 COH901318_CX_CTRL_TCP_DISABLE |
 841                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 842                                 COH901318_CX_CTRL_HSP_ENABLE |
 843                                 COH901318_CX_CTRL_HSS_DISABLE |
 844                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 845                                 COH901318_CX_CTRL_PRDD_DEST,
 846                 .param.ctrl_lli = 0 |
 847                                 COH901318_CX_CTRL_TC_ENABLE |
 848                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 849                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 850                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 851                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 852                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 853                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 854                                 COH901318_CX_CTRL_TCP_DISABLE |
 855                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 856                                 COH901318_CX_CTRL_HSP_ENABLE |
 857                                 COH901318_CX_CTRL_HSS_DISABLE |
 858                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 859                                 COH901318_CX_CTRL_PRDD_DEST,
 860                 .param.ctrl_lli_last = 0 |
 861                                 COH901318_CX_CTRL_TC_ENABLE |
 862                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 863                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 864                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 865                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 866                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 867                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 868                                 COH901318_CX_CTRL_TCP_DISABLE |
 869                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 870                                 COH901318_CX_CTRL_HSP_ENABLE |
 871                                 COH901318_CX_CTRL_HSS_DISABLE |
 872                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 873                                 COH901318_CX_CTRL_PRDD_DEST,
 874         },
 875         {
 876                 .number = U300_DMA_MSL_RX_4,
 877                 .name = "MSL RX 4",
 878                 .priority_high = 0,
 879                 .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x220,
 880                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 881                                 COH901318_CX_CFG_LCR_DISABLE |
 882                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 883                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 884                 .param.ctrl_lli_chained = 0 |
 885                                 COH901318_CX_CTRL_TC_ENABLE |
 886                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 887                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 888                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 889                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 890                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 891                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 892                                 COH901318_CX_CTRL_TCP_DISABLE |
 893                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 894                                 COH901318_CX_CTRL_HSP_ENABLE |
 895                                 COH901318_CX_CTRL_HSS_DISABLE |
 896                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 897                                 COH901318_CX_CTRL_PRDD_DEST,
 898                 .param.ctrl_lli = 0 |
 899                                 COH901318_CX_CTRL_TC_ENABLE |
 900                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 901                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 902                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 903                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 904                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 905                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 906                                 COH901318_CX_CTRL_TCP_DISABLE |
 907                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 908                                 COH901318_CX_CTRL_HSP_ENABLE |
 909                                 COH901318_CX_CTRL_HSS_DISABLE |
 910                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 911                                 COH901318_CX_CTRL_PRDD_DEST,
 912                 .param.ctrl_lli_last = 0 |
 913                                 COH901318_CX_CTRL_TC_ENABLE |
 914                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 915                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 916                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 917                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 918                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 919                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 920                                 COH901318_CX_CTRL_TCP_DISABLE |
 921                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 922                                 COH901318_CX_CTRL_HSP_ENABLE |
 923                                 COH901318_CX_CTRL_HSS_DISABLE |
 924                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 925                                 COH901318_CX_CTRL_PRDD_DEST,
 926         },
 927         {
 928                 .number = U300_DMA_MSL_RX_5,
 929                 .name = "MSL RX 5",
 930                 .priority_high = 0,
 931                 .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x220,
 932                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 933                                 COH901318_CX_CFG_LCR_DISABLE |
 934                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 935                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 936                 .param.ctrl_lli_chained = 0 |
 937                                 COH901318_CX_CTRL_TC_ENABLE |
 938                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 939                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 940                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 941                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 942                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 943                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 944                                 COH901318_CX_CTRL_TCP_DISABLE |
 945                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 946                                 COH901318_CX_CTRL_HSP_ENABLE |
 947                                 COH901318_CX_CTRL_HSS_DISABLE |
 948                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 949                                 COH901318_CX_CTRL_PRDD_DEST,
 950                 .param.ctrl_lli = 0 |
 951                                 COH901318_CX_CTRL_TC_ENABLE |
 952                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 953                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 954                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 955                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 956                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 957                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 958                                 COH901318_CX_CTRL_TCP_DISABLE |
 959                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 960                                 COH901318_CX_CTRL_HSP_ENABLE |
 961                                 COH901318_CX_CTRL_HSS_DISABLE |
 962                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 963                                 COH901318_CX_CTRL_PRDD_DEST,
 964                 .param.ctrl_lli_last = 0 |
 965                                 COH901318_CX_CTRL_TC_ENABLE |
 966                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 967                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 968                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 969                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 970                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 971                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 972                                 COH901318_CX_CTRL_TCP_DISABLE |
 973                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 974                                 COH901318_CX_CTRL_HSP_ENABLE |
 975                                 COH901318_CX_CTRL_HSS_DISABLE |
 976                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 977                                 COH901318_CX_CTRL_PRDD_DEST,
 978         },
 979         {
 980                 .number = U300_DMA_MSL_RX_6,
 981                 .name = "MSL RX 6",
 982                 .priority_high = 0,
 983                 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x220,
 984         },
 985         /*
 986          * Don't set up device address, burst count or size of src
 987          * or dst bus for this peripheral - handled by PrimeCell
 988          * DMA extension.
 989          */
 990         {
 991                 .number = U300_DMA_MMCSD_RX_TX,
 992                 .name = "MMCSD RX TX",
 993                 .priority_high = 0,
 994                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 995                                 COH901318_CX_CFG_LCR_DISABLE |
 996                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 997                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 998                 .param.ctrl_lli_chained = 0 |
 999                                 COH901318_CX_CTRL_TC_ENABLE |
1000                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1001                                 COH901318_CX_CTRL_TCP_ENABLE |
1002                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1003                                 COH901318_CX_CTRL_HSP_ENABLE |
1004                                 COH901318_CX_CTRL_HSS_DISABLE |
1005                                 COH901318_CX_CTRL_DDMA_LEGACY,
1006                 .param.ctrl_lli = 0 |
1007                                 COH901318_CX_CTRL_TC_ENABLE |
1008                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1009                                 COH901318_CX_CTRL_TCP_ENABLE |
1010                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1011                                 COH901318_CX_CTRL_HSP_ENABLE |
1012                                 COH901318_CX_CTRL_HSS_DISABLE |
1013                                 COH901318_CX_CTRL_DDMA_LEGACY,
1014                 .param.ctrl_lli_last = 0 |
1015                                 COH901318_CX_CTRL_TC_ENABLE |
1016                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1017                                 COH901318_CX_CTRL_TCP_DISABLE |
1018                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1019                                 COH901318_CX_CTRL_HSP_ENABLE |
1020                                 COH901318_CX_CTRL_HSS_DISABLE |
1021                                 COH901318_CX_CTRL_DDMA_LEGACY,
1022
1023         },
1024         {
1025                 .number = U300_DMA_MSPRO_TX,
1026                 .name = "MSPRO TX",
1027                 .priority_high = 0,
1028         },
1029         {
1030                 .number = U300_DMA_MSPRO_RX,
1031                 .name = "MSPRO RX",
1032                 .priority_high = 0,
1033         },
1034         /*
1035          * Don't set up device address, burst count or size of src
1036          * or dst bus for this peripheral - handled by PrimeCell
1037          * DMA extension.
1038          */
1039         {
1040                 .number = U300_DMA_UART0_TX,
1041                 .name = "UART0 TX",
1042                 .priority_high = 0,
1043                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1044                                 COH901318_CX_CFG_LCR_DISABLE |
1045                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1046                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1047                 .param.ctrl_lli_chained = 0 |
1048                                 COH901318_CX_CTRL_TC_ENABLE |
1049                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1050                                 COH901318_CX_CTRL_TCP_ENABLE |
1051                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1052                                 COH901318_CX_CTRL_HSP_ENABLE |
1053                                 COH901318_CX_CTRL_HSS_DISABLE |
1054                                 COH901318_CX_CTRL_DDMA_LEGACY,
1055                 .param.ctrl_lli = 0 |
1056                                 COH901318_CX_CTRL_TC_ENABLE |
1057                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1058                                 COH901318_CX_CTRL_TCP_ENABLE |
1059                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1060                                 COH901318_CX_CTRL_HSP_ENABLE |
1061                                 COH901318_CX_CTRL_HSS_DISABLE |
1062                                 COH901318_CX_CTRL_DDMA_LEGACY,
1063                 .param.ctrl_lli_last = 0 |
1064                                 COH901318_CX_CTRL_TC_ENABLE |
1065                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1066                                 COH901318_CX_CTRL_TCP_ENABLE |
1067                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1068                                 COH901318_CX_CTRL_HSP_ENABLE |
1069                                 COH901318_CX_CTRL_HSS_DISABLE |
1070                                 COH901318_CX_CTRL_DDMA_LEGACY,
1071         },
1072         {
1073                 .number = U300_DMA_UART0_RX,
1074                 .name = "UART0 RX",
1075                 .priority_high = 0,
1076                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1077                                 COH901318_CX_CFG_LCR_DISABLE |
1078                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1079                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1080                 .param.ctrl_lli_chained = 0 |
1081                                 COH901318_CX_CTRL_TC_ENABLE |
1082                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1083                                 COH901318_CX_CTRL_TCP_ENABLE |
1084                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1085                                 COH901318_CX_CTRL_HSP_ENABLE |
1086                                 COH901318_CX_CTRL_HSS_DISABLE |
1087                                 COH901318_CX_CTRL_DDMA_LEGACY,
1088                 .param.ctrl_lli = 0 |
1089                                 COH901318_CX_CTRL_TC_ENABLE |
1090                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1091                                 COH901318_CX_CTRL_TCP_ENABLE |
1092                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1093                                 COH901318_CX_CTRL_HSP_ENABLE |
1094                                 COH901318_CX_CTRL_HSS_DISABLE |
1095                                 COH901318_CX_CTRL_DDMA_LEGACY,
1096                 .param.ctrl_lli_last = 0 |
1097                                 COH901318_CX_CTRL_TC_ENABLE |
1098                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1099                                 COH901318_CX_CTRL_TCP_ENABLE |
1100                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1101                                 COH901318_CX_CTRL_HSP_ENABLE |
1102                                 COH901318_CX_CTRL_HSS_DISABLE |
1103                                 COH901318_CX_CTRL_DDMA_LEGACY,
1104         },
1105         {
1106                 .number = U300_DMA_APEX_TX,
1107                 .name = "APEX TX",
1108                 .priority_high = 0,
1109         },
1110         {
1111                 .number = U300_DMA_APEX_RX,
1112                 .name = "APEX RX",
1113                 .priority_high = 0,
1114         },
1115         {
1116                 .number = U300_DMA_PCM_I2S0_TX,
1117                 .name = "PCM I2S0 TX",
1118                 .priority_high = 1,
1119                 .dev_addr = U300_PCM_I2S0_BASE + 0x14,
1120                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1121                                 COH901318_CX_CFG_LCR_DISABLE |
1122                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1123                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1124                 .param.ctrl_lli_chained = 0 |
1125                                 COH901318_CX_CTRL_TC_ENABLE |
1126                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1127                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1128                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1129                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1130                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1131                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1132                                 COH901318_CX_CTRL_TCP_DISABLE |
1133                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1134                                 COH901318_CX_CTRL_HSP_ENABLE |
1135                                 COH901318_CX_CTRL_HSS_DISABLE |
1136                                 COH901318_CX_CTRL_DDMA_LEGACY |
1137                                 COH901318_CX_CTRL_PRDD_SOURCE,
1138                 .param.ctrl_lli = 0 |
1139                                 COH901318_CX_CTRL_TC_ENABLE |
1140                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1141                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1142                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1143                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1144                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1145                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1146                                 COH901318_CX_CTRL_TCP_ENABLE |
1147                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1148                                 COH901318_CX_CTRL_HSP_ENABLE |
1149                                 COH901318_CX_CTRL_HSS_DISABLE |
1150                                 COH901318_CX_CTRL_DDMA_LEGACY |
1151                                 COH901318_CX_CTRL_PRDD_SOURCE,
1152                 .param.ctrl_lli_last = 0 |
1153                                 COH901318_CX_CTRL_TC_ENABLE |
1154                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1155                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1156                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1157                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1158                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1159                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1160                                 COH901318_CX_CTRL_TCP_ENABLE |
1161                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1162                                 COH901318_CX_CTRL_HSP_ENABLE |
1163                                 COH901318_CX_CTRL_HSS_DISABLE |
1164                                 COH901318_CX_CTRL_DDMA_LEGACY |
1165                                 COH901318_CX_CTRL_PRDD_SOURCE,
1166         },
1167         {
1168                 .number = U300_DMA_PCM_I2S0_RX,
1169                 .name = "PCM I2S0 RX",
1170                 .priority_high = 1,
1171                 .dev_addr = U300_PCM_I2S0_BASE + 0x10,
1172                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1173                                 COH901318_CX_CFG_LCR_DISABLE |
1174                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1175                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1176                 .param.ctrl_lli_chained = 0 |
1177                                 COH901318_CX_CTRL_TC_ENABLE |
1178                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1179                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1180                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1181                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1182                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1183                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1184                                 COH901318_CX_CTRL_TCP_DISABLE |
1185                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1186                                 COH901318_CX_CTRL_HSP_ENABLE |
1187                                 COH901318_CX_CTRL_HSS_DISABLE |
1188                                 COH901318_CX_CTRL_DDMA_LEGACY |
1189                                 COH901318_CX_CTRL_PRDD_DEST,
1190                 .param.ctrl_lli = 0 |
1191                                 COH901318_CX_CTRL_TC_ENABLE |
1192                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1193                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1194                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1195                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1196                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1197                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1198                                 COH901318_CX_CTRL_TCP_ENABLE |
1199                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1200                                 COH901318_CX_CTRL_HSP_ENABLE |
1201                                 COH901318_CX_CTRL_HSS_DISABLE |
1202                                 COH901318_CX_CTRL_DDMA_LEGACY |
1203                                 COH901318_CX_CTRL_PRDD_DEST,
1204                 .param.ctrl_lli_last = 0 |
1205                                 COH901318_CX_CTRL_TC_ENABLE |
1206                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1207                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1208                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1209                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1210                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1211                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1212                                 COH901318_CX_CTRL_TCP_ENABLE |
1213                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1214                                 COH901318_CX_CTRL_HSP_ENABLE |
1215                                 COH901318_CX_CTRL_HSS_DISABLE |
1216                                 COH901318_CX_CTRL_DDMA_LEGACY |
1217                                 COH901318_CX_CTRL_PRDD_DEST,
1218         },
1219         {
1220                 .number = U300_DMA_PCM_I2S1_TX,
1221                 .name = "PCM I2S1 TX",
1222                 .priority_high = 1,
1223                 .dev_addr =  U300_PCM_I2S1_BASE + 0x14,
1224                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1225                                 COH901318_CX_CFG_LCR_DISABLE |
1226                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1227                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1228                 .param.ctrl_lli_chained = 0 |
1229                                 COH901318_CX_CTRL_TC_ENABLE |
1230                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1231                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1232                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1233                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1234                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1235                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1236                                 COH901318_CX_CTRL_TCP_DISABLE |
1237                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1238                                 COH901318_CX_CTRL_HSP_ENABLE |
1239                                 COH901318_CX_CTRL_HSS_DISABLE |
1240                                 COH901318_CX_CTRL_DDMA_LEGACY |
1241                                 COH901318_CX_CTRL_PRDD_SOURCE,
1242                 .param.ctrl_lli = 0 |
1243                                 COH901318_CX_CTRL_TC_ENABLE |
1244                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1245                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1246                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1247                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1248                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1249                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1250                                 COH901318_CX_CTRL_TCP_ENABLE |
1251                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1252                                 COH901318_CX_CTRL_HSP_ENABLE |
1253                                 COH901318_CX_CTRL_HSS_DISABLE |
1254                                 COH901318_CX_CTRL_DDMA_LEGACY |
1255                                 COH901318_CX_CTRL_PRDD_SOURCE,
1256                 .param.ctrl_lli_last = 0 |
1257                                 COH901318_CX_CTRL_TC_ENABLE |
1258                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1259                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1260                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1261                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1262                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1263                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1264                                 COH901318_CX_CTRL_TCP_ENABLE |
1265                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1266                                 COH901318_CX_CTRL_HSP_ENABLE |
1267                                 COH901318_CX_CTRL_HSS_DISABLE |
1268                                 COH901318_CX_CTRL_DDMA_LEGACY |
1269                                 COH901318_CX_CTRL_PRDD_SOURCE,
1270         },
1271         {
1272                 .number = U300_DMA_PCM_I2S1_RX,
1273                 .name = "PCM I2S1 RX",
1274                 .priority_high = 1,
1275                 .dev_addr = U300_PCM_I2S1_BASE + 0x10,
1276                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1277                                 COH901318_CX_CFG_LCR_DISABLE |
1278                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1279                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1280                 .param.ctrl_lli_chained = 0 |
1281                                 COH901318_CX_CTRL_TC_ENABLE |
1282                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1283                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1284                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1285                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1286                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1287                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1288                                 COH901318_CX_CTRL_TCP_DISABLE |
1289                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1290                                 COH901318_CX_CTRL_HSP_ENABLE |
1291                                 COH901318_CX_CTRL_HSS_DISABLE |
1292                                 COH901318_CX_CTRL_DDMA_LEGACY |
1293                                 COH901318_CX_CTRL_PRDD_DEST,
1294                 .param.ctrl_lli = 0 |
1295                                 COH901318_CX_CTRL_TC_ENABLE |
1296                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1297                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1298                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1299                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1300                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1301                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1302                                 COH901318_CX_CTRL_TCP_ENABLE |
1303                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1304                                 COH901318_CX_CTRL_HSP_ENABLE |
1305                                 COH901318_CX_CTRL_HSS_DISABLE |
1306                                 COH901318_CX_CTRL_DDMA_LEGACY |
1307                                 COH901318_CX_CTRL_PRDD_DEST,
1308                 .param.ctrl_lli_last = 0 |
1309                                 COH901318_CX_CTRL_TC_ENABLE |
1310                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1311                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1312                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1313                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1314                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1315                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1316                                 COH901318_CX_CTRL_TCP_ENABLE |
1317                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1318                                 COH901318_CX_CTRL_HSP_ENABLE |
1319                                 COH901318_CX_CTRL_HSS_DISABLE |
1320                                 COH901318_CX_CTRL_DDMA_LEGACY |
1321                                 COH901318_CX_CTRL_PRDD_DEST,
1322         },
1323         {
1324                 .number = U300_DMA_XGAM_CDI,
1325                 .name = "XGAM CDI",
1326                 .priority_high = 0,
1327         },
1328         {
1329                 .number = U300_DMA_XGAM_PDI,
1330                 .name = "XGAM PDI",
1331                 .priority_high = 0,
1332         },
1333         /*
1334          * Don't set up device address, burst count or size of src
1335          * or dst bus for this peripheral - handled by PrimeCell
1336          * DMA extension.
1337          */
1338         {
1339                 .number = U300_DMA_SPI_TX,
1340                 .name = "SPI TX",
1341                 .priority_high = 0,
1342                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1343                                 COH901318_CX_CFG_LCR_DISABLE |
1344                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1345                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1346                 .param.ctrl_lli_chained = 0 |
1347                                 COH901318_CX_CTRL_TC_ENABLE |
1348                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1349                                 COH901318_CX_CTRL_TCP_DISABLE |
1350                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1351                                 COH901318_CX_CTRL_HSP_ENABLE |
1352                                 COH901318_CX_CTRL_HSS_DISABLE |
1353                                 COH901318_CX_CTRL_DDMA_LEGACY,
1354                 .param.ctrl_lli = 0 |
1355                                 COH901318_CX_CTRL_TC_ENABLE |
1356                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1357                                 COH901318_CX_CTRL_TCP_DISABLE |
1358                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1359                                 COH901318_CX_CTRL_HSP_ENABLE |
1360                                 COH901318_CX_CTRL_HSS_DISABLE |
1361                                 COH901318_CX_CTRL_DDMA_LEGACY,
1362                 .param.ctrl_lli_last = 0 |
1363                                 COH901318_CX_CTRL_TC_ENABLE |
1364                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1365                                 COH901318_CX_CTRL_TCP_DISABLE |
1366                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1367                                 COH901318_CX_CTRL_HSP_ENABLE |
1368                                 COH901318_CX_CTRL_HSS_DISABLE |
1369                                 COH901318_CX_CTRL_DDMA_LEGACY,
1370         },
1371         {
1372                 .number = U300_DMA_SPI_RX,
1373                 .name = "SPI RX",
1374                 .priority_high = 0,
1375                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1376                                 COH901318_CX_CFG_LCR_DISABLE |
1377                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1378                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1379                 .param.ctrl_lli_chained = 0 |
1380                                 COH901318_CX_CTRL_TC_ENABLE |
1381                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1382                                 COH901318_CX_CTRL_TCP_DISABLE |
1383                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1384                                 COH901318_CX_CTRL_HSP_ENABLE |
1385                                 COH901318_CX_CTRL_HSS_DISABLE |
1386                                 COH901318_CX_CTRL_DDMA_LEGACY,
1387                 .param.ctrl_lli = 0 |
1388                                 COH901318_CX_CTRL_TC_ENABLE |
1389                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1390                                 COH901318_CX_CTRL_TCP_DISABLE |
1391                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1392                                 COH901318_CX_CTRL_HSP_ENABLE |
1393                                 COH901318_CX_CTRL_HSS_DISABLE |
1394                                 COH901318_CX_CTRL_DDMA_LEGACY,
1395                 .param.ctrl_lli_last = 0 |
1396                                 COH901318_CX_CTRL_TC_ENABLE |
1397                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1398                                 COH901318_CX_CTRL_TCP_DISABLE |
1399                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1400                                 COH901318_CX_CTRL_HSP_ENABLE |
1401                                 COH901318_CX_CTRL_HSS_DISABLE |
1402                                 COH901318_CX_CTRL_DDMA_LEGACY,
1403
1404         },
1405         {
1406                 .number = U300_DMA_GENERAL_PURPOSE_0,
1407                 .name = "GENERAL 00",
1408                 .priority_high = 0,
1409
1410                 .param.config = flags_memcpy_config,
1411                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1412                 .param.ctrl_lli = flags_memcpy_lli,
1413                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1414         },
1415         {
1416                 .number = U300_DMA_GENERAL_PURPOSE_1,
1417                 .name = "GENERAL 01",
1418                 .priority_high = 0,
1419
1420                 .param.config = flags_memcpy_config,
1421                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1422                 .param.ctrl_lli = flags_memcpy_lli,
1423                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1424         },
1425         {
1426                 .number = U300_DMA_GENERAL_PURPOSE_2,
1427                 .name = "GENERAL 02",
1428                 .priority_high = 0,
1429
1430                 .param.config = flags_memcpy_config,
1431                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1432                 .param.ctrl_lli = flags_memcpy_lli,
1433                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1434         },
1435         {
1436                 .number = U300_DMA_GENERAL_PURPOSE_3,
1437                 .name = "GENERAL 03",
1438                 .priority_high = 0,
1439
1440                 .param.config = flags_memcpy_config,
1441                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1442                 .param.ctrl_lli = flags_memcpy_lli,
1443                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1444         },
1445         {
1446                 .number = U300_DMA_GENERAL_PURPOSE_4,
1447                 .name = "GENERAL 04",
1448                 .priority_high = 0,
1449
1450                 .param.config = flags_memcpy_config,
1451                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1452                 .param.ctrl_lli = flags_memcpy_lli,
1453                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1454         },
1455         {
1456                 .number = U300_DMA_GENERAL_PURPOSE_5,
1457                 .name = "GENERAL 05",
1458                 .priority_high = 0,
1459
1460                 .param.config = flags_memcpy_config,
1461                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1462                 .param.ctrl_lli = flags_memcpy_lli,
1463                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1464         },
1465         {
1466                 .number = U300_DMA_GENERAL_PURPOSE_6,
1467                 .name = "GENERAL 06",
1468                 .priority_high = 0,
1469
1470                 .param.config = flags_memcpy_config,
1471                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1472                 .param.ctrl_lli = flags_memcpy_lli,
1473                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1474         },
1475         {
1476                 .number = U300_DMA_GENERAL_PURPOSE_7,
1477                 .name = "GENERAL 07",
1478                 .priority_high = 0,
1479
1480                 .param.config = flags_memcpy_config,
1481                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1482                 .param.ctrl_lli = flags_memcpy_lli,
1483                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1484         },
1485         {
1486                 .number = U300_DMA_GENERAL_PURPOSE_8,
1487                 .name = "GENERAL 08",
1488                 .priority_high = 0,
1489
1490                 .param.config = flags_memcpy_config,
1491                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1492                 .param.ctrl_lli = flags_memcpy_lli,
1493                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1494         },
1495 #ifdef CONFIG_MACH_U300_BS335
1496         {
1497                 .number = U300_DMA_UART1_TX,
1498                 .name = "UART1 TX",
1499                 .priority_high = 0,
1500         },
1501         {
1502                 .number = U300_DMA_UART1_RX,
1503                 .name = "UART1 RX",
1504                 .priority_high = 0,
1505         }
1506 #else
1507         {
1508                 .number = U300_DMA_GENERAL_PURPOSE_9,
1509                 .name = "GENERAL 09",
1510                 .priority_high = 0,
1511
1512                 .param.config = flags_memcpy_config,
1513                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1514                 .param.ctrl_lli = flags_memcpy_lli,
1515                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1516         },
1517         {
1518                 .number = U300_DMA_GENERAL_PURPOSE_10,
1519                 .name = "GENERAL 10",
1520                 .priority_high = 0,
1521
1522                 .param.config = flags_memcpy_config,
1523                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1524                 .param.ctrl_lli = flags_memcpy_lli,
1525                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1526         }
1527 #endif
1528 };
1529
1530
1531 static struct coh901318_platform coh901318_platform = {
1532         .chans_slave = dma_slave_channels,
1533         .chans_memcpy = dma_memcpy_channels,
1534         .access_memory_state = coh901318_access_memory_state,
1535         .chan_conf = chan_config,
1536         .max_channels = U300_DMA_CHANNELS,
1537 };
1538
1539 static struct platform_device wdog_device = {
1540         .name = "coh901327_wdog",
1541         .id = -1,
1542         .num_resources = ARRAY_SIZE(wdog_resources),
1543         .resource = wdog_resources,
1544 };
1545
1546 static struct platform_device i2c0_device = {
1547         .name = "stu300",
1548         .id = 0,
1549         .num_resources = ARRAY_SIZE(i2c0_resources),
1550         .resource = i2c0_resources,
1551 };
1552
1553 static struct platform_device i2c1_device = {
1554         .name = "stu300",
1555         .id = 1,
1556         .num_resources = ARRAY_SIZE(i2c1_resources),
1557         .resource = i2c1_resources,
1558 };
1559
1560 /*
1561  * The different variants have a few different versions of the
1562  * GPIO block, with different number of ports.
1563  */
1564 static struct u300_gpio_platform u300_gpio_plat = {
1565 #if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
1566         .variant = U300_GPIO_COH901335,
1567         .ports = 3,
1568 #endif
1569 #ifdef CONFIG_MACH_U300_BS335
1570         .variant = U300_GPIO_COH901571_3_BS335,
1571         .ports = 7,
1572 #endif
1573 #ifdef CONFIG_MACH_U300_BS365
1574         .variant = U300_GPIO_COH901571_3_BS365,
1575         .ports = 5,
1576 #endif
1577         .gpio_base = 0,
1578         .gpio_irq_base = IRQ_U300_GPIO_BASE,
1579 };
1580
1581 static struct platform_device gpio_device = {
1582         .name = "u300-gpio",
1583         .id = -1,
1584         .num_resources = ARRAY_SIZE(gpio_resources),
1585         .resource = gpio_resources,
1586         .dev = {
1587                 .platform_data = &u300_gpio_plat,
1588         },
1589 };
1590
1591 static struct platform_device keypad_device = {
1592         .name = "keypad",
1593         .id = -1,
1594         .num_resources = ARRAY_SIZE(keypad_resources),
1595         .resource = keypad_resources,
1596 };
1597
1598 static struct platform_device rtc_device = {
1599         .name = "rtc-coh901331",
1600         .id = -1,
1601         .num_resources = ARRAY_SIZE(rtc_resources),
1602         .resource = rtc_resources,
1603 };
1604
1605 static struct mtd_partition u300_partitions[] = {
1606         {
1607                 .name = "bootrecords",
1608                 .offset = 0,
1609                 .size = SZ_128K,
1610         },
1611         {
1612                 .name = "free",
1613                 .offset = SZ_128K,
1614                 .size = 8064 * SZ_1K,
1615         },
1616         {
1617                 .name = "platform",
1618                 .offset = 8192 * SZ_1K,
1619                 .size = 253952 * SZ_1K,
1620         },
1621 };
1622
1623 static struct fsmc_nand_platform_data nand_platform_data = {
1624         .partitions = u300_partitions,
1625         .nr_partitions = ARRAY_SIZE(u300_partitions),
1626         .options = NAND_SKIP_BBTSCAN,
1627         .width = FSMC_NAND_BW8,
1628 };
1629
1630 static struct platform_device nand_device = {
1631         .name = "fsmc-nand",
1632         .id = -1,
1633         .resource = fsmc_resources,
1634         .num_resources = ARRAY_SIZE(fsmc_resources),
1635         .dev = {
1636                 .platform_data = &nand_platform_data,
1637         },
1638 };
1639
1640 static struct platform_device ave_device = {
1641         .name = "video_enc",
1642         .id = -1,
1643         .num_resources = ARRAY_SIZE(ave_resources),
1644         .resource = ave_resources,
1645 };
1646
1647 static struct platform_device dma_device = {
1648         .name           = "coh901318",
1649         .id             = -1,
1650         .resource       = dma_resource,
1651         .num_resources  = ARRAY_SIZE(dma_resource),
1652         .dev = {
1653                 .platform_data = &coh901318_platform,
1654                 .coherent_dma_mask = ~0,
1655         },
1656 };
1657
1658 /*
1659  * Notice that AMBA devices are initialized before platform devices.
1660  *
1661  */
1662 static struct platform_device *platform_devs[] __initdata = {
1663         &dma_device,
1664         &i2c0_device,
1665         &i2c1_device,
1666         &keypad_device,
1667         &rtc_device,
1668         &gpio_device,
1669         &nand_device,
1670         &wdog_device,
1671         &ave_device
1672 };
1673
1674
1675 /*
1676  * Interrupts: the U300 platforms have two pl190 ARM PrimeCells connected
1677  * together so some interrupts are connected to the first one and some
1678  * to the second one.
1679  */
1680 void __init u300_init_irq(void)
1681 {
1682         u32 mask[2] = {0, 0};
1683         struct clk *clk;
1684         int i;
1685
1686         /* initialize clocking early, we want to clock the INTCON */
1687         u300_clock_init();
1688
1689         /* Clock the interrupt controller */
1690         clk = clk_get_sys("intcon", NULL);
1691         BUG_ON(IS_ERR(clk));
1692         clk_enable(clk);
1693
1694         for (i = 0; i < U300_VIC_IRQS_END; i++)
1695                 set_bit(i, (unsigned long *) &mask[0]);
1696         vic_init((void __iomem *) U300_INTCON0_VBASE, 0, mask[0], mask[0]);
1697         vic_init((void __iomem *) U300_INTCON1_VBASE, 32, mask[1], mask[1]);
1698 }
1699
1700
1701 /*
1702  * U300 platforms peripheral handling
1703  */
1704 struct db_chip {
1705         u16 chipid;
1706         const char *name;
1707 };
1708
1709 /*
1710  * This is a list of the Digital Baseband chips used in the U300 platform.
1711  */
1712 static struct db_chip db_chips[] __initdata = {
1713         {
1714                 .chipid = 0xb800,
1715                 .name = "DB3000",
1716         },
1717         {
1718                 .chipid = 0xc000,
1719                 .name = "DB3100",
1720         },
1721         {
1722                 .chipid = 0xc800,
1723                 .name = "DB3150",
1724         },
1725         {
1726                 .chipid = 0xd800,
1727                 .name = "DB3200",
1728         },
1729         {
1730                 .chipid = 0xe000,
1731                 .name = "DB3250",
1732         },
1733         {
1734                 .chipid = 0xe800,
1735                 .name = "DB3210",
1736         },
1737         {
1738                 .chipid = 0xf000,
1739                 .name = "DB3350 P1x",
1740         },
1741         {
1742                 .chipid = 0xf100,
1743                 .name = "DB3350 P2x",
1744         },
1745         {
1746                 .chipid = 0x0000, /* List terminator */
1747                 .name = NULL,
1748         }
1749 };
1750
1751 static void __init u300_init_check_chip(void)
1752 {
1753
1754         u16 val;
1755         struct db_chip *chip;
1756         const char *chipname;
1757         const char unknown[] = "UNKNOWN";
1758
1759         /* Read out and print chip ID */
1760         val = readw(U300_SYSCON_VBASE + U300_SYSCON_CIDR);
1761         /* This is in funky bigendian order... */
1762         val = (val & 0xFFU) << 8 | (val >> 8);
1763         chip = db_chips;
1764         chipname = unknown;
1765
1766         for ( ; chip->chipid; chip++) {
1767                 if (chip->chipid == (val & 0xFF00U)) {
1768                         chipname = chip->name;
1769                         break;
1770                 }
1771         }
1772         printk(KERN_INFO "Initializing U300 system on %s baseband chip " \
1773                "(chip ID 0x%04x)\n", chipname, val);
1774
1775 #ifdef CONFIG_MACH_U300_BS330
1776         if ((val & 0xFF00U) != 0xd800) {
1777                 printk(KERN_ERR "Platform configured for BS330 " \
1778                        "with DB3200 but %s detected, expect problems!",
1779                        chipname);
1780         }
1781 #endif
1782 #ifdef CONFIG_MACH_U300_BS335
1783         if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) {
1784                 printk(KERN_ERR "Platform configured for BS335 " \
1785                        " with DB3350 but %s detected, expect problems!",
1786                        chipname);
1787         }
1788 #endif
1789 #ifdef CONFIG_MACH_U300_BS365
1790         if ((val & 0xFF00U) != 0xe800) {
1791                 printk(KERN_ERR "Platform configured for BS365 " \
1792                        "with DB3210 but %s detected, expect problems!",
1793                        chipname);
1794         }
1795 #endif
1796
1797
1798 }
1799
1800 /*
1801  * Some devices and their resources require reserved physical memory from
1802  * the end of the available RAM. This function traverses the list of devices
1803  * and assigns actual addresses to these.
1804  */
1805 static void __init u300_assign_physmem(void)
1806 {
1807         unsigned long curr_start = __pa(high_memory);
1808         int i, j;
1809
1810         for (i = 0; i < ARRAY_SIZE(platform_devs); i++) {
1811                 for (j = 0; j < platform_devs[i]->num_resources; j++) {
1812                         struct resource *const res =
1813                           &platform_devs[i]->resource[j];
1814
1815                         if (IORESOURCE_MEM == res->flags &&
1816                                      0 == res->start) {
1817                                 res->start  = curr_start;
1818                                 res->end   += curr_start;
1819                                 curr_start += resource_size(res);
1820
1821                                 printk(KERN_INFO "core.c: Mapping RAM " \
1822                                        "%#x-%#x to device %s:%s\n",
1823                                         res->start, res->end,
1824                                        platform_devs[i]->name, res->name);
1825                         }
1826                 }
1827         }
1828 }
1829
1830 void __init u300_init_devices(void)
1831 {
1832         int i;
1833         u16 val;
1834
1835         /* Check what platform we run and print some status information */
1836         u300_init_check_chip();
1837
1838         /* Set system to run at PLL208, max performance, a known state. */
1839         val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
1840         val &= ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
1841         writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
1842         /* Wait for the PLL208 to lock if not locked in yet */
1843         while (!(readw(U300_SYSCON_VBASE + U300_SYSCON_CSR) &
1844                  U300_SYSCON_CSR_PLL208_LOCK_IND));
1845         /* Initialize SPI device with some board specifics */
1846         u300_spi_init(&pl022_device);
1847
1848         /* Register the AMBA devices in the AMBA bus abstraction layer */
1849         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
1850                 struct amba_device *d = amba_devs[i];
1851                 amba_device_register(d, &iomem_resource);
1852         }
1853
1854         u300_assign_physmem();
1855
1856         /* Register subdevices on the I2C buses */
1857         u300_i2c_register_board_devices();
1858
1859         /* Register the platform devices */
1860         platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
1861
1862         /* Register subdevices on the SPI bus */
1863         u300_spi_register_board_devices();
1864
1865 #ifndef CONFIG_MACH_U300_SEMI_IS_SHARED
1866         /*
1867          * Enable SEMI self refresh. Self-refresh of the SDRAM is entered when
1868          * both subsystems are requesting this mode.
1869          * If we not share the Acc SDRAM, this is never the case. Therefore
1870          * enable it here from the App side.
1871          */
1872         val = readw(U300_SYSCON_VBASE + U300_SYSCON_SMCR) |
1873                 U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE;
1874         writew(val, U300_SYSCON_VBASE + U300_SYSCON_SMCR);
1875 #endif /* CONFIG_MACH_U300_SEMI_IS_SHARED */
1876 }
1877
1878 static int core_module_init(void)
1879 {
1880         /*
1881          * This needs to be initialized later: it needs the input framework
1882          * to be initialized first.
1883          */
1884         return mmc_init(&mmcsd_device);
1885 }
1886 module_init(core_module_init);