2 * arch/arm/mach-tegra/tegra2_clocks.c
4 * Copyright (C) 2010 Google, Inc.
7 * Colin Cross <ccross@google.com>
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/list.h>
23 #include <linux/spinlock.h>
24 #include <linux/delay.h>
26 #include <linux/clkdev.h>
27 #include <linux/clk.h>
29 #include <mach/iomap.h>
30 #include <mach/suspend.h>
35 #define RST_DEVICES 0x004
36 #define RST_DEVICES_SET 0x300
37 #define RST_DEVICES_CLR 0x304
38 #define RST_DEVICES_NUM 3
40 #define CLK_OUT_ENB 0x010
41 #define CLK_OUT_ENB_SET 0x320
42 #define CLK_OUT_ENB_CLR 0x324
43 #define CLK_OUT_ENB_NUM 3
45 #define CLK_MASK_ARM 0x44
46 #define MISC_CLK_ENB 0x48
49 #define OSC_CTRL_OSC_FREQ_MASK (3<<30)
50 #define OSC_CTRL_OSC_FREQ_13MHZ (0<<30)
51 #define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30)
52 #define OSC_CTRL_OSC_FREQ_12MHZ (2<<30)
53 #define OSC_CTRL_OSC_FREQ_26MHZ (3<<30)
54 #define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
56 #define OSC_FREQ_DET 0x58
57 #define OSC_FREQ_DET_TRIG (1<<31)
59 #define OSC_FREQ_DET_STATUS 0x5C
60 #define OSC_FREQ_DET_BUSY (1<<31)
61 #define OSC_FREQ_DET_CNT_MASK 0xFFFF
63 #define PERIPH_CLK_SOURCE_I2S1 0x100
64 #define PERIPH_CLK_SOURCE_EMC 0x19c
65 #define PERIPH_CLK_SOURCE_OSC 0x1fc
66 #define PERIPH_CLK_SOURCE_NUM \
67 ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4)
69 #define PERIPH_CLK_SOURCE_MASK (3<<30)
70 #define PERIPH_CLK_SOURCE_SHIFT 30
71 #define PERIPH_CLK_SOURCE_ENABLE (1<<28)
72 #define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF
73 #define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF
74 #define PERIPH_CLK_SOURCE_DIV_SHIFT 0
77 #define PLL_BASE_BYPASS (1<<31)
78 #define PLL_BASE_ENABLE (1<<30)
79 #define PLL_BASE_REF_ENABLE (1<<29)
80 #define PLL_BASE_OVERRIDE (1<<28)
81 #define PLL_BASE_DIVP_MASK (0x7<<20)
82 #define PLL_BASE_DIVP_SHIFT 20
83 #define PLL_BASE_DIVN_MASK (0x3FF<<8)
84 #define PLL_BASE_DIVN_SHIFT 8
85 #define PLL_BASE_DIVM_MASK (0x1F)
86 #define PLL_BASE_DIVM_SHIFT 0
88 #define PLL_OUT_RATIO_MASK (0xFF<<8)
89 #define PLL_OUT_RATIO_SHIFT 8
90 #define PLL_OUT_OVERRIDE (1<<2)
91 #define PLL_OUT_CLKEN (1<<1)
92 #define PLL_OUT_RESET_DISABLE (1<<0)
94 #define PLL_MISC(c) (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)
96 #define PLL_MISC_DCCON_SHIFT 20
97 #define PLL_MISC_CPCON_SHIFT 8
98 #define PLL_MISC_CPCON_MASK (0xF<<PLL_MISC_CPCON_SHIFT)
99 #define PLL_MISC_LFCON_SHIFT 4
100 #define PLL_MISC_LFCON_MASK (0xF<<PLL_MISC_LFCON_SHIFT)
101 #define PLL_MISC_VCOCON_SHIFT 0
102 #define PLL_MISC_VCOCON_MASK (0xF<<PLL_MISC_VCOCON_SHIFT)
104 #define PLLU_BASE_POST_DIV (1<<20)
106 #define PLLD_MISC_CLKENABLE (1<<30)
107 #define PLLD_MISC_DIV_RST (1<<23)
108 #define PLLD_MISC_DCCON_SHIFT 12
110 #define PLLE_MISC_READY (1 << 15)
112 #define PERIPH_CLK_TO_ENB_REG(c) ((c->u.periph.clk_num / 32) * 4)
113 #define PERIPH_CLK_TO_ENB_SET_REG(c) ((c->u.periph.clk_num / 32) * 8)
114 #define PERIPH_CLK_TO_ENB_BIT(c) (1 << (c->u.periph.clk_num % 32))
116 #define SUPER_CLK_MUX 0x00
117 #define SUPER_STATE_SHIFT 28
118 #define SUPER_STATE_MASK (0xF << SUPER_STATE_SHIFT)
119 #define SUPER_STATE_STANDBY (0x0 << SUPER_STATE_SHIFT)
120 #define SUPER_STATE_IDLE (0x1 << SUPER_STATE_SHIFT)
121 #define SUPER_STATE_RUN (0x2 << SUPER_STATE_SHIFT)
122 #define SUPER_STATE_IRQ (0x3 << SUPER_STATE_SHIFT)
123 #define SUPER_STATE_FIQ (0x4 << SUPER_STATE_SHIFT)
124 #define SUPER_SOURCE_MASK 0xF
125 #define SUPER_FIQ_SOURCE_SHIFT 12
126 #define SUPER_IRQ_SOURCE_SHIFT 8
127 #define SUPER_RUN_SOURCE_SHIFT 4
128 #define SUPER_IDLE_SOURCE_SHIFT 0
130 #define SUPER_CLK_DIVIDER 0x04
132 #define BUS_CLK_DISABLE (1<<3)
133 #define BUS_CLK_DIV_MASK 0x3
136 #define PMC_CTRL_BLINK_ENB (1 << 7)
138 #define PMC_DPD_PADS_ORIDE 0x1c
139 #define PMC_DPD_PADS_ORIDE_BLINK_ENB (1 << 20)
141 #define PMC_BLINK_TIMER_DATA_ON_SHIFT 0
142 #define PMC_BLINK_TIMER_DATA_ON_MASK 0x7fff
143 #define PMC_BLINK_TIMER_ENB (1 << 15)
144 #define PMC_BLINK_TIMER_DATA_OFF_SHIFT 16
145 #define PMC_BLINK_TIMER_DATA_OFF_MASK 0xffff
147 static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
148 static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
151 * Some clocks share a register with other clocks. Any clock op that
152 * non-atomically modifies a register used by another clock must lock
153 * clock_register_lock first.
155 static DEFINE_SPINLOCK(clock_register_lock);
157 #define clk_writel(value, reg) \
158 __raw_writel(value, (u32)reg_clk_base + (reg))
159 #define clk_readl(reg) \
160 __raw_readl((u32)reg_clk_base + (reg))
161 #define pmc_writel(value, reg) \
162 __raw_writel(value, (u32)reg_pmc_base + (reg))
163 #define pmc_readl(reg) \
164 __raw_readl((u32)reg_pmc_base + (reg))
166 unsigned long clk_measure_input_freq(void)
168 u32 clock_autodetect;
169 clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET);
170 do {} while (clk_readl(OSC_FREQ_DET_STATUS) & OSC_FREQ_DET_BUSY);
171 clock_autodetect = clk_readl(OSC_FREQ_DET_STATUS);
172 if (clock_autodetect >= 732 - 3 && clock_autodetect <= 732 + 3) {
174 } else if (clock_autodetect >= 794 - 3 && clock_autodetect <= 794 + 3) {
176 } else if (clock_autodetect >= 1172 - 3 && clock_autodetect <= 1172 + 3) {
178 } else if (clock_autodetect >= 1587 - 3 && clock_autodetect <= 1587 + 3) {
181 pr_err("%s: Unexpected clock autodetect value %d", __func__, clock_autodetect);
187 static int clk_div71_get_divider(unsigned long parent_rate, unsigned long rate)
189 s64 divider_u71 = parent_rate * 2;
190 divider_u71 += rate - 1;
191 do_div(divider_u71, rate);
193 if (divider_u71 - 2 < 0)
196 if (divider_u71 - 2 > 255)
199 return divider_u71 - 2;
202 static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
206 divider_u16 = parent_rate;
207 divider_u16 += rate - 1;
208 do_div(divider_u16, rate);
210 if (divider_u16 - 1 < 0)
213 if (divider_u16 - 1 > 255)
216 return divider_u16 - 1;
219 /* clk_m functions */
220 static unsigned long tegra2_clk_m_autodetect_rate(struct clk *c)
222 u32 auto_clock_control = clk_readl(OSC_CTRL) & ~OSC_CTRL_OSC_FREQ_MASK;
224 c->rate = clk_measure_input_freq();
227 auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
230 auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ;
233 auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ;
236 auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ;
239 pr_err("%s: Unexpected clock rate %ld", __func__, c->rate);
242 clk_writel(auto_clock_control, OSC_CTRL);
246 static void tegra2_clk_m_init(struct clk *c)
248 pr_debug("%s on clock %s\n", __func__, c->name);
249 tegra2_clk_m_autodetect_rate(c);
252 static int tegra2_clk_m_enable(struct clk *c)
254 pr_debug("%s on clock %s\n", __func__, c->name);
258 static void tegra2_clk_m_disable(struct clk *c)
260 pr_debug("%s on clock %s\n", __func__, c->name);
264 static struct clk_ops tegra_clk_m_ops = {
265 .init = tegra2_clk_m_init,
266 .enable = tegra2_clk_m_enable,
267 .disable = tegra2_clk_m_disable,
270 void tegra2_periph_reset_assert(struct clk *c)
272 BUG_ON(!c->ops->reset);
273 c->ops->reset(c, true);
276 void tegra2_periph_reset_deassert(struct clk *c)
278 BUG_ON(!c->ops->reset);
279 c->ops->reset(c, false);
282 /* super clock functions */
283 /* "super clocks" on tegra have two-stage muxes and a clock skipping
284 * super divider. We will ignore the clock skipping divider, since we
285 * can't lower the voltage when using the clock skip, but we can if we
286 * lower the PLL frequency.
288 static void tegra2_super_clk_init(struct clk *c)
293 const struct clk_mux_sel *sel;
294 val = clk_readl(c->reg + SUPER_CLK_MUX);
296 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
297 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
298 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
299 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
300 source = (val >> shift) & SUPER_SOURCE_MASK;
301 for (sel = c->inputs; sel->input != NULL; sel++) {
302 if (sel->value == source)
305 BUG_ON(sel->input == NULL);
306 c->parent = sel->input;
309 static int tegra2_super_clk_enable(struct clk *c)
311 clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
315 static void tegra2_super_clk_disable(struct clk *c)
317 pr_debug("%s on clock %s\n", __func__, c->name);
319 /* oops - don't disable the CPU clock! */
323 static int tegra2_super_clk_set_parent(struct clk *c, struct clk *p)
326 const struct clk_mux_sel *sel;
329 val = clk_readl(c->reg + SUPER_CLK_MUX);;
330 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
331 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
332 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
333 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
334 for (sel = c->inputs; sel->input != NULL; sel++) {
335 if (sel->input == p) {
336 val &= ~(SUPER_SOURCE_MASK << shift);
337 val |= sel->value << shift;
342 clk_writel(val, c->reg);
344 if (c->refcnt && c->parent)
345 clk_disable(c->parent);
354 static struct clk_ops tegra_super_ops = {
355 .init = tegra2_super_clk_init,
356 .enable = tegra2_super_clk_enable,
357 .disable = tegra2_super_clk_disable,
358 .set_parent = tegra2_super_clk_set_parent,
361 /* virtual cpu clock functions */
362 /* some clocks can not be stopped (cpu, memory bus) while the SoC is running.
363 To change the frequency of these clocks, the parent pll may need to be
364 reprogrammed, so the clock must be moved off the pll, the pll reprogrammed,
365 and then the clock moved back to the pll. To hide this sequence, a virtual
368 static void tegra2_cpu_clk_init(struct clk *c)
372 static int tegra2_cpu_clk_enable(struct clk *c)
377 static void tegra2_cpu_clk_disable(struct clk *c)
379 pr_debug("%s on clock %s\n", __func__, c->name);
381 /* oops - don't disable the CPU clock! */
385 static int tegra2_cpu_clk_set_rate(struct clk *c, unsigned long rate)
389 * Take an extra reference to the main pll so it doesn't turn
390 * off when we move the cpu off of it
392 clk_enable(c->u.cpu.main);
394 ret = clk_set_parent(c->parent, c->u.cpu.backup);
396 pr_err("Failed to switch cpu to clock %s\n", c->u.cpu.backup->name);
400 if (rate == clk_get_rate(c->u.cpu.backup))
403 ret = clk_set_rate(c->u.cpu.main, rate);
405 pr_err("Failed to change cpu pll to %lu\n", rate);
409 ret = clk_set_parent(c->parent, c->u.cpu.main);
411 pr_err("Failed to switch cpu to clock %s\n", c->u.cpu.main->name);
416 clk_disable(c->u.cpu.main);
420 static struct clk_ops tegra_cpu_ops = {
421 .init = tegra2_cpu_clk_init,
422 .enable = tegra2_cpu_clk_enable,
423 .disable = tegra2_cpu_clk_disable,
424 .set_rate = tegra2_cpu_clk_set_rate,
427 /* bus clock functions */
428 static void tegra2_bus_clk_init(struct clk *c)
430 u32 val = clk_readl(c->reg);
431 c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON;
432 c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1;
436 static int tegra2_bus_clk_enable(struct clk *c)
441 spin_lock_irqsave(&clock_register_lock, flags);
443 val = clk_readl(c->reg);
444 val &= ~(BUS_CLK_DISABLE << c->reg_shift);
445 clk_writel(val, c->reg);
447 spin_unlock_irqrestore(&clock_register_lock, flags);
452 static void tegra2_bus_clk_disable(struct clk *c)
457 spin_lock_irqsave(&clock_register_lock, flags);
459 val = clk_readl(c->reg);
460 val |= BUS_CLK_DISABLE << c->reg_shift;
461 clk_writel(val, c->reg);
463 spin_unlock_irqrestore(&clock_register_lock, flags);
466 static int tegra2_bus_clk_set_rate(struct clk *c, unsigned long rate)
469 unsigned long parent_rate = clk_get_rate(c->parent);
474 spin_lock_irqsave(&clock_register_lock, flags);
476 val = clk_readl(c->reg);
477 for (i = 1; i <= 4; i++) {
478 if (rate == parent_rate / i) {
479 val &= ~(BUS_CLK_DIV_MASK << c->reg_shift);
480 val |= (i - 1) << c->reg_shift;
481 clk_writel(val, c->reg);
489 spin_unlock_irqrestore(&clock_register_lock, flags);
494 static struct clk_ops tegra_bus_ops = {
495 .init = tegra2_bus_clk_init,
496 .enable = tegra2_bus_clk_enable,
497 .disable = tegra2_bus_clk_disable,
498 .set_rate = tegra2_bus_clk_set_rate,
501 /* Blink output functions */
503 static void tegra2_blink_clk_init(struct clk *c)
507 val = pmc_readl(PMC_CTRL);
508 c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF;
510 val = pmc_readl(c->reg);
512 if (val & PMC_BLINK_TIMER_ENB) {
515 on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
516 PMC_BLINK_TIMER_DATA_ON_MASK;
517 val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
518 val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
520 /* each tick in the blink timer is 4 32KHz clocks */
527 static int tegra2_blink_clk_enable(struct clk *c)
531 val = pmc_readl(PMC_DPD_PADS_ORIDE);
532 pmc_writel(val | PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
534 val = pmc_readl(PMC_CTRL);
535 pmc_writel(val | PMC_CTRL_BLINK_ENB, PMC_CTRL);
540 static void tegra2_blink_clk_disable(struct clk *c)
544 val = pmc_readl(PMC_CTRL);
545 pmc_writel(val & ~PMC_CTRL_BLINK_ENB, PMC_CTRL);
547 val = pmc_readl(PMC_DPD_PADS_ORIDE);
548 pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
551 static int tegra2_blink_clk_set_rate(struct clk *c, unsigned long rate)
553 unsigned long parent_rate = clk_get_rate(c->parent);
554 if (rate >= parent_rate) {
556 pmc_writel(0, c->reg);
561 on_off = DIV_ROUND_UP(parent_rate / 8, rate);
564 val = (on_off & PMC_BLINK_TIMER_DATA_ON_MASK) <<
565 PMC_BLINK_TIMER_DATA_ON_SHIFT;
566 on_off &= PMC_BLINK_TIMER_DATA_OFF_MASK;
567 on_off <<= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
569 val |= PMC_BLINK_TIMER_ENB;
570 pmc_writel(val, c->reg);
576 static struct clk_ops tegra_blink_clk_ops = {
577 .init = &tegra2_blink_clk_init,
578 .enable = &tegra2_blink_clk_enable,
579 .disable = &tegra2_blink_clk_disable,
580 .set_rate = &tegra2_blink_clk_set_rate,
584 static int tegra2_pll_clk_wait_for_lock(struct clk *c)
586 udelay(c->u.pll.lock_delay);
591 static void tegra2_pll_clk_init(struct clk *c)
593 u32 val = clk_readl(c->reg + PLL_BASE);
595 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
597 if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
598 pr_warning("Clock %s has unknown fixed frequency\n", c->name);
601 } else if (val & PLL_BASE_BYPASS) {
605 c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
606 c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
608 c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
610 c->div *= (val & PLL_BASE_DIVP_MASK) ? 2 : 1;
614 static int tegra2_pll_clk_enable(struct clk *c)
617 pr_debug("%s on clock %s\n", __func__, c->name);
619 val = clk_readl(c->reg + PLL_BASE);
620 val &= ~PLL_BASE_BYPASS;
621 val |= PLL_BASE_ENABLE;
622 clk_writel(val, c->reg + PLL_BASE);
624 tegra2_pll_clk_wait_for_lock(c);
629 static void tegra2_pll_clk_disable(struct clk *c)
632 pr_debug("%s on clock %s\n", __func__, c->name);
634 val = clk_readl(c->reg);
635 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
636 clk_writel(val, c->reg);
639 static int tegra2_pll_clk_set_rate(struct clk *c, unsigned long rate)
642 unsigned long input_rate;
643 const struct clk_pll_freq_table *sel;
645 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
647 input_rate = clk_get_rate(c->parent);
648 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
649 if (sel->input_rate == input_rate && sel->output_rate == rate) {
651 c->div = sel->m * sel->p;
653 val = clk_readl(c->reg + PLL_BASE);
654 if (c->flags & PLL_FIXED)
655 val |= PLL_BASE_OVERRIDE;
656 val &= ~(PLL_BASE_DIVP_MASK | PLL_BASE_DIVN_MASK |
658 val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
659 (sel->n << PLL_BASE_DIVN_SHIFT);
660 BUG_ON(sel->p < 1 || sel->p > 2);
661 if (c->flags & PLLU) {
663 val |= PLLU_BASE_POST_DIV;
666 val |= 1 << PLL_BASE_DIVP_SHIFT;
668 clk_writel(val, c->reg + PLL_BASE);
670 if (c->flags & PLL_HAS_CPCON) {
671 val = clk_readl(c->reg + PLL_MISC(c));
672 val &= ~PLL_MISC_CPCON_MASK;
673 val |= sel->cpcon << PLL_MISC_CPCON_SHIFT;
674 clk_writel(val, c->reg + PLL_MISC(c));
678 tegra2_pll_clk_enable(c);
686 static struct clk_ops tegra_pll_ops = {
687 .init = tegra2_pll_clk_init,
688 .enable = tegra2_pll_clk_enable,
689 .disable = tegra2_pll_clk_disable,
690 .set_rate = tegra2_pll_clk_set_rate,
693 static void tegra2_pllx_clk_init(struct clk *c)
695 tegra2_pll_clk_init(c);
697 if (tegra_sku_id() == 7)
698 c->max_rate = 750000000;
701 static struct clk_ops tegra_pllx_ops = {
702 .init = tegra2_pllx_clk_init,
703 .enable = tegra2_pll_clk_enable,
704 .disable = tegra2_pll_clk_disable,
705 .set_rate = tegra2_pll_clk_set_rate,
708 static int tegra2_plle_clk_enable(struct clk *c)
712 pr_debug("%s on clock %s\n", __func__, c->name);
716 val = clk_readl(c->reg + PLL_BASE);
717 if (!(val & PLLE_MISC_READY))
720 val = clk_readl(c->reg + PLL_BASE);
721 val |= PLL_BASE_ENABLE | PLL_BASE_BYPASS;
722 clk_writel(val, c->reg + PLL_BASE);
727 static struct clk_ops tegra_plle_ops = {
728 .init = tegra2_pll_clk_init,
729 .enable = tegra2_plle_clk_enable,
730 .set_rate = tegra2_pll_clk_set_rate,
733 /* Clock divider ops */
734 static void tegra2_pll_div_clk_init(struct clk *c)
736 u32 val = clk_readl(c->reg);
738 val >>= c->reg_shift;
739 c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
740 if (!(val & PLL_OUT_RESET_DISABLE))
743 if (c->flags & DIV_U71) {
744 divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
745 c->div = (divu71 + 2);
747 } else if (c->flags & DIV_2) {
756 static int tegra2_pll_div_clk_enable(struct clk *c)
762 pr_debug("%s: %s\n", __func__, c->name);
763 if (c->flags & DIV_U71) {
764 spin_lock_irqsave(&clock_register_lock, flags);
765 val = clk_readl(c->reg);
766 new_val = val >> c->reg_shift;
769 new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
771 val &= ~(0xFFFF << c->reg_shift);
772 val |= new_val << c->reg_shift;
773 clk_writel(val, c->reg);
774 spin_unlock_irqrestore(&clock_register_lock, flags);
776 } else if (c->flags & DIV_2) {
777 BUG_ON(!(c->flags & PLLD));
778 spin_lock_irqsave(&clock_register_lock, flags);
779 val = clk_readl(c->reg);
780 val &= ~PLLD_MISC_DIV_RST;
781 clk_writel(val, c->reg);
782 spin_unlock_irqrestore(&clock_register_lock, flags);
788 static void tegra2_pll_div_clk_disable(struct clk *c)
794 pr_debug("%s: %s\n", __func__, c->name);
795 if (c->flags & DIV_U71) {
796 spin_lock_irqsave(&clock_register_lock, flags);
797 val = clk_readl(c->reg);
798 new_val = val >> c->reg_shift;
801 new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE);
803 val &= ~(0xFFFF << c->reg_shift);
804 val |= new_val << c->reg_shift;
805 clk_writel(val, c->reg);
806 spin_unlock_irqrestore(&clock_register_lock, flags);
807 } else if (c->flags & DIV_2) {
808 BUG_ON(!(c->flags & PLLD));
809 spin_lock_irqsave(&clock_register_lock, flags);
810 val = clk_readl(c->reg);
811 val |= PLLD_MISC_DIV_RST;
812 clk_writel(val, c->reg);
813 spin_unlock_irqrestore(&clock_register_lock, flags);
817 static int tegra2_pll_div_clk_set_rate(struct clk *c, unsigned long rate)
822 unsigned long parent_rate = clk_get_rate(c->parent);
825 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
826 if (c->flags & DIV_U71) {
827 divider_u71 = clk_div71_get_divider(parent_rate, rate);
828 if (divider_u71 >= 0) {
829 spin_lock_irqsave(&clock_register_lock, flags);
830 val = clk_readl(c->reg);
831 new_val = val >> c->reg_shift;
833 if (c->flags & DIV_U71_FIXED)
834 new_val |= PLL_OUT_OVERRIDE;
835 new_val &= ~PLL_OUT_RATIO_MASK;
836 new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT;
838 val &= ~(0xFFFF << c->reg_shift);
839 val |= new_val << c->reg_shift;
840 clk_writel(val, c->reg);
841 c->div = divider_u71 + 2;
843 spin_unlock_irqrestore(&clock_register_lock, flags);
846 } else if (c->flags & DIV_2) {
847 if (parent_rate == rate * 2)
853 static long tegra2_pll_div_clk_round_rate(struct clk *c, unsigned long rate)
856 unsigned long parent_rate = clk_get_rate(c->parent);
857 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
859 if (c->flags & DIV_U71) {
860 divider = clk_div71_get_divider(parent_rate, rate);
863 return parent_rate * 2 / (divider + 2);
864 } else if (c->flags & DIV_2) {
865 return parent_rate / 2;
870 static struct clk_ops tegra_pll_div_ops = {
871 .init = tegra2_pll_div_clk_init,
872 .enable = tegra2_pll_div_clk_enable,
873 .disable = tegra2_pll_div_clk_disable,
874 .set_rate = tegra2_pll_div_clk_set_rate,
875 .round_rate = tegra2_pll_div_clk_round_rate,
880 static void tegra2_periph_clk_init(struct clk *c)
882 u32 val = clk_readl(c->reg);
883 const struct clk_mux_sel *mux = 0;
884 const struct clk_mux_sel *sel;
885 if (c->flags & MUX) {
886 for (sel = c->inputs; sel->input != NULL; sel++) {
887 if (val >> PERIPH_CLK_SOURCE_SHIFT == sel->value)
892 c->parent = mux->input;
894 c->parent = c->inputs[0].input;
897 if (c->flags & DIV_U71) {
898 u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
901 } else if (c->flags & DIV_U16) {
902 u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
911 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
912 PERIPH_CLK_TO_ENB_BIT(c)))
914 if (!(c->flags & PERIPH_NO_RESET))
915 if (clk_readl(RST_DEVICES + PERIPH_CLK_TO_ENB_REG(c)) &
916 PERIPH_CLK_TO_ENB_BIT(c))
920 static int tegra2_periph_clk_enable(struct clk *c)
923 pr_debug("%s on clock %s\n", __func__, c->name);
925 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
926 CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
927 if (!(c->flags & PERIPH_NO_RESET) && !(c->flags & PERIPH_MANUAL_RESET))
928 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
929 RST_DEVICES_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
930 if (c->flags & PERIPH_EMC_ENB) {
931 /* The EMC peripheral clock has 2 extra enable bits */
932 /* FIXME: Do they need to be disabled? */
933 val = clk_readl(c->reg);
935 clk_writel(val, c->reg);
940 static void tegra2_periph_clk_disable(struct clk *c)
942 pr_debug("%s on clock %s\n", __func__, c->name);
944 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
945 CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
948 static void tegra2_periph_clk_reset(struct clk *c, bool assert)
950 unsigned long base = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
952 pr_debug("%s %s on clock %s\n", __func__,
953 assert ? "assert" : "deassert", c->name);
954 if (!(c->flags & PERIPH_NO_RESET))
955 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
956 base + PERIPH_CLK_TO_ENB_SET_REG(c));
959 static int tegra2_periph_clk_set_parent(struct clk *c, struct clk *p)
962 const struct clk_mux_sel *sel;
963 pr_debug("%s: %s %s\n", __func__, c->name, p->name);
964 for (sel = c->inputs; sel->input != NULL; sel++) {
965 if (sel->input == p) {
966 val = clk_readl(c->reg);
967 val &= ~PERIPH_CLK_SOURCE_MASK;
968 val |= (sel->value) << PERIPH_CLK_SOURCE_SHIFT;
973 clk_writel(val, c->reg);
975 if (c->refcnt && c->parent)
976 clk_disable(c->parent);
986 static int tegra2_periph_clk_set_rate(struct clk *c, unsigned long rate)
990 unsigned long parent_rate = clk_get_rate(c->parent);
992 if (c->flags & DIV_U71) {
993 divider = clk_div71_get_divider(parent_rate, rate);
995 val = clk_readl(c->reg);
996 val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK;
998 clk_writel(val, c->reg);
999 c->div = divider + 2;
1003 } else if (c->flags & DIV_U16) {
1004 divider = clk_div16_get_divider(parent_rate, rate);
1006 val = clk_readl(c->reg);
1007 val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK;
1009 clk_writel(val, c->reg);
1010 c->div = divider + 1;
1014 } else if (parent_rate <= rate) {
1022 static long tegra2_periph_clk_round_rate(struct clk *c,
1026 unsigned long parent_rate = clk_get_rate(c->parent);
1027 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
1029 if (c->flags & DIV_U71) {
1030 divider = clk_div71_get_divider(parent_rate, rate);
1034 return parent_rate * 2 / (divider + 2);
1035 } else if (c->flags & DIV_U16) {
1036 divider = clk_div16_get_divider(parent_rate, rate);
1039 return parent_rate / (divider + 1);
1044 static struct clk_ops tegra_periph_clk_ops = {
1045 .init = &tegra2_periph_clk_init,
1046 .enable = &tegra2_periph_clk_enable,
1047 .disable = &tegra2_periph_clk_disable,
1048 .set_parent = &tegra2_periph_clk_set_parent,
1049 .set_rate = &tegra2_periph_clk_set_rate,
1050 .round_rate = &tegra2_periph_clk_round_rate,
1051 .reset = &tegra2_periph_clk_reset,
1054 /* Clock doubler ops */
1055 static void tegra2_clk_double_init(struct clk *c)
1060 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
1061 PERIPH_CLK_TO_ENB_BIT(c)))
1065 static int tegra2_clk_double_set_rate(struct clk *c, unsigned long rate)
1067 if (rate != 2 * clk_get_rate(c->parent))
1074 static struct clk_ops tegra_clk_double_ops = {
1075 .init = &tegra2_clk_double_init,
1076 .enable = &tegra2_periph_clk_enable,
1077 .disable = &tegra2_periph_clk_disable,
1078 .set_rate = &tegra2_clk_double_set_rate,
1081 /* Audio sync clock ops */
1082 static void tegra2_audio_sync_clk_init(struct clk *c)
1085 const struct clk_mux_sel *sel;
1086 u32 val = clk_readl(c->reg);
1087 c->state = (val & (1<<4)) ? OFF : ON;
1089 for (sel = c->inputs; sel->input != NULL; sel++)
1090 if (sel->value == source)
1092 BUG_ON(sel->input == NULL);
1093 c->parent = sel->input;
1096 static int tegra2_audio_sync_clk_enable(struct clk *c)
1098 clk_writel(0, c->reg);
1102 static void tegra2_audio_sync_clk_disable(struct clk *c)
1104 clk_writel(1, c->reg);
1107 static int tegra2_audio_sync_clk_set_parent(struct clk *c, struct clk *p)
1110 const struct clk_mux_sel *sel;
1111 for (sel = c->inputs; sel->input != NULL; sel++) {
1112 if (sel->input == p) {
1113 val = clk_readl(c->reg);
1120 clk_writel(val, c->reg);
1122 if (c->refcnt && c->parent)
1123 clk_disable(c->parent);
1133 static int tegra2_audio_sync_clk_set_rate(struct clk *c, unsigned long rate)
1135 unsigned long parent_rate;
1137 pr_err("%s: clock has no parent\n", __func__);
1140 parent_rate = c->parent->rate;
1141 if (rate != parent_rate) {
1142 pr_err("%s: %s/%ld differs from parent %s/%ld\n",
1145 c->parent->name, parent_rate);
1148 c->rate = parent_rate;
1152 static struct clk_ops tegra_audio_sync_clk_ops = {
1153 .init = tegra2_audio_sync_clk_init,
1154 .enable = tegra2_audio_sync_clk_enable,
1155 .disable = tegra2_audio_sync_clk_disable,
1156 .set_rate = tegra2_audio_sync_clk_set_rate,
1157 .set_parent = tegra2_audio_sync_clk_set_parent,
1160 /* cdev1 and cdev2 (dap_mclk1 and dap_mclk2) ops */
1162 static void tegra2_cdev_clk_init(struct clk *c)
1164 /* We could un-tristate the cdev1 or cdev2 pingroup here; this is
1165 * currently done in the pinmux code. */
1167 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
1168 PERIPH_CLK_TO_ENB_BIT(c)))
1172 static int tegra2_cdev_clk_enable(struct clk *c)
1174 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1175 CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
1179 static void tegra2_cdev_clk_disable(struct clk *c)
1181 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1182 CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
1185 static struct clk_ops tegra_cdev_clk_ops = {
1186 .init = &tegra2_cdev_clk_init,
1187 .enable = &tegra2_cdev_clk_enable,
1188 .disable = &tegra2_cdev_clk_disable,
1191 /* Clock definitions */
1192 static struct clk tegra_clk_32k = {
1199 static struct clk_pll_freq_table tegra_pll_s_freq_table[] = {
1200 {32768, 12000000, 366, 1, 1, 0},
1201 {32768, 13000000, 397, 1, 1, 0},
1202 {32768, 19200000, 586, 1, 1, 0},
1203 {32768, 26000000, 793, 1, 1, 0},
1207 static struct clk tegra_pll_s = {
1209 .flags = PLL_ALT_MISC_REG,
1210 .ops = &tegra_pll_ops,
1211 .parent = &tegra_clk_32k,
1212 .max_rate = 26000000,
1217 .cf_min = 0, /* FIXME */
1218 .cf_max = 0, /* FIXME */
1219 .vco_min = 12000000,
1220 .vco_max = 26000000,
1221 .freq_table = tegra_pll_s_freq_table,
1226 static struct clk_mux_sel tegra_clk_m_sel[] = {
1227 { .input = &tegra_clk_32k, .value = 0},
1228 { .input = &tegra_pll_s, .value = 1},
1232 static struct clk tegra_clk_m = {
1234 .flags = ENABLE_ON_INIT,
1235 .ops = &tegra_clk_m_ops,
1236 .inputs = tegra_clk_m_sel,
1239 .max_rate = 26000000,
1242 static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
1243 { 0, 0, 0, 0, 0, 0 },
1246 static struct clk tegra_pll_c = {
1248 .flags = PLL_HAS_CPCON,
1249 .ops = &tegra_pll_ops,
1251 .parent = &tegra_clk_m,
1252 .max_rate = 600000000,
1254 .input_min = 2000000,
1255 .input_max = 31000000,
1258 .vco_min = 20000000,
1259 .vco_max = 1400000000,
1260 .freq_table = tegra_pll_c_freq_table,
1265 static struct clk tegra_pll_c_out1 = {
1266 .name = "pll_c_out1",
1267 .ops = &tegra_pll_div_ops,
1269 .parent = &tegra_pll_c,
1272 .max_rate = 600000000,
1275 static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
1276 { 12000000, 666000000, 666, 12, 1, 8},
1277 { 13000000, 666000000, 666, 13, 1, 8},
1278 { 19200000, 666000000, 555, 16, 1, 8},
1279 { 26000000, 666000000, 666, 26, 1, 8},
1280 { 12000000, 600000000, 600, 12, 1, 8},
1281 { 13000000, 600000000, 600, 13, 1, 8},
1282 { 19200000, 600000000, 375, 12, 1, 6},
1283 { 26000000, 600000000, 600, 26, 1, 8},
1284 { 0, 0, 0, 0, 0, 0 },
1287 static struct clk tegra_pll_m = {
1289 .flags = PLL_HAS_CPCON,
1290 .ops = &tegra_pll_ops,
1292 .parent = &tegra_clk_m,
1293 .max_rate = 800000000,
1295 .input_min = 2000000,
1296 .input_max = 31000000,
1299 .vco_min = 20000000,
1300 .vco_max = 1200000000,
1301 .freq_table = tegra_pll_m_freq_table,
1306 static struct clk tegra_pll_m_out1 = {
1307 .name = "pll_m_out1",
1308 .ops = &tegra_pll_div_ops,
1310 .parent = &tegra_pll_m,
1313 .max_rate = 600000000,
1316 static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
1317 { 12000000, 216000000, 432, 12, 2, 8},
1318 { 13000000, 216000000, 432, 13, 2, 8},
1319 { 19200000, 216000000, 90, 4, 2, 1},
1320 { 26000000, 216000000, 432, 26, 2, 8},
1321 { 12000000, 432000000, 432, 12, 1, 8},
1322 { 13000000, 432000000, 432, 13, 1, 8},
1323 { 19200000, 432000000, 90, 4, 1, 1},
1324 { 26000000, 432000000, 432, 26, 1, 8},
1325 { 0, 0, 0, 0, 0, 0 },
1328 static struct clk tegra_pll_p = {
1330 .flags = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON,
1331 .ops = &tegra_pll_ops,
1333 .parent = &tegra_clk_m,
1334 .max_rate = 432000000,
1336 .input_min = 2000000,
1337 .input_max = 31000000,
1340 .vco_min = 20000000,
1341 .vco_max = 1400000000,
1342 .freq_table = tegra_pll_p_freq_table,
1347 static struct clk tegra_pll_p_out1 = {
1348 .name = "pll_p_out1",
1349 .ops = &tegra_pll_div_ops,
1350 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1351 .parent = &tegra_pll_p,
1354 .max_rate = 432000000,
1357 static struct clk tegra_pll_p_out2 = {
1358 .name = "pll_p_out2",
1359 .ops = &tegra_pll_div_ops,
1360 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1361 .parent = &tegra_pll_p,
1364 .max_rate = 432000000,
1367 static struct clk tegra_pll_p_out3 = {
1368 .name = "pll_p_out3",
1369 .ops = &tegra_pll_div_ops,
1370 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1371 .parent = &tegra_pll_p,
1374 .max_rate = 432000000,
1377 static struct clk tegra_pll_p_out4 = {
1378 .name = "pll_p_out4",
1379 .ops = &tegra_pll_div_ops,
1380 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1381 .parent = &tegra_pll_p,
1384 .max_rate = 432000000,
1387 static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
1388 { 28800000, 56448000, 49, 25, 1, 1},
1389 { 28800000, 73728000, 64, 25, 1, 1},
1390 { 28800000, 11289600, 49, 25, 1, 1},
1391 { 28800000, 12288000, 64, 25, 1, 1},
1392 { 28800000, 24000000, 5, 6, 1, 1},
1393 { 0, 0, 0, 0, 0, 0 },
1396 static struct clk tegra_pll_a = {
1398 .flags = PLL_HAS_CPCON,
1399 .ops = &tegra_pll_ops,
1401 .parent = &tegra_pll_p_out1,
1402 .max_rate = 56448000,
1404 .input_min = 2000000,
1405 .input_max = 31000000,
1408 .vco_min = 20000000,
1409 .vco_max = 1400000000,
1410 .freq_table = tegra_pll_a_freq_table,
1415 static struct clk tegra_pll_a_out0 = {
1416 .name = "pll_a_out0",
1417 .ops = &tegra_pll_div_ops,
1419 .parent = &tegra_pll_a,
1422 .max_rate = 56448000,
1425 static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
1426 { 12000000, 216000000, 216, 12, 1, 4},
1427 { 13000000, 216000000, 216, 13, 1, 4},
1428 { 19200000, 216000000, 135, 12, 1, 3},
1429 { 26000000, 216000000, 216, 26, 1, 4},
1431 { 12000000, 594000000, 594, 12, 1, 8},
1432 { 13000000, 594000000, 594, 13, 1, 8},
1433 { 19200000, 594000000, 495, 16, 1, 8},
1434 { 26000000, 594000000, 594, 26, 1, 8},
1436 { 12000000, 1000000000, 1000, 12, 1, 12},
1437 { 13000000, 1000000000, 1000, 13, 1, 12},
1438 { 19200000, 1000000000, 625, 12, 1, 8},
1439 { 26000000, 1000000000, 1000, 26, 1, 12},
1441 { 0, 0, 0, 0, 0, 0 },
1444 static struct clk tegra_pll_d = {
1446 .flags = PLL_HAS_CPCON | PLLD,
1447 .ops = &tegra_pll_ops,
1449 .parent = &tegra_clk_m,
1450 .max_rate = 1000000000,
1452 .input_min = 2000000,
1453 .input_max = 40000000,
1456 .vco_min = 40000000,
1457 .vco_max = 1000000000,
1458 .freq_table = tegra_pll_d_freq_table,
1463 static struct clk tegra_pll_d_out0 = {
1464 .name = "pll_d_out0",
1465 .ops = &tegra_pll_div_ops,
1466 .flags = DIV_2 | PLLD,
1467 .parent = &tegra_pll_d,
1468 .max_rate = 500000000,
1471 static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
1472 { 12000000, 480000000, 960, 12, 2, 0},
1473 { 13000000, 480000000, 960, 13, 2, 0},
1474 { 19200000, 480000000, 200, 4, 2, 0},
1475 { 26000000, 480000000, 960, 26, 2, 0},
1476 { 0, 0, 0, 0, 0, 0 },
1479 static struct clk tegra_pll_u = {
1482 .ops = &tegra_pll_ops,
1484 .parent = &tegra_clk_m,
1485 .max_rate = 480000000,
1487 .input_min = 2000000,
1488 .input_max = 40000000,
1491 .vco_min = 480000000,
1492 .vco_max = 960000000,
1493 .freq_table = tegra_pll_u_freq_table,
1498 static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
1500 { 12000000, 1000000000, 1000, 12, 1, 12},
1501 { 13000000, 1000000000, 1000, 13, 1, 12},
1502 { 19200000, 1000000000, 625, 12, 1, 8},
1503 { 26000000, 1000000000, 1000, 26, 1, 12},
1506 { 12000000, 912000000, 912, 12, 1, 12},
1507 { 13000000, 912000000, 912, 13, 1, 12},
1508 { 19200000, 912000000, 760, 16, 1, 8},
1509 { 26000000, 912000000, 912, 26, 1, 12},
1512 { 12000000, 816000000, 816, 12, 1, 12},
1513 { 13000000, 816000000, 816, 13, 1, 12},
1514 { 19200000, 816000000, 680, 16, 1, 8},
1515 { 26000000, 816000000, 816, 26, 1, 12},
1518 { 12000000, 760000000, 760, 12, 1, 12},
1519 { 13000000, 760000000, 760, 13, 1, 12},
1520 { 19200000, 760000000, 950, 24, 1, 8},
1521 { 26000000, 760000000, 760, 26, 1, 12},
1524 { 12000000, 608000000, 760, 12, 1, 12},
1525 { 13000000, 608000000, 760, 13, 1, 12},
1526 { 19200000, 608000000, 380, 12, 1, 8},
1527 { 26000000, 608000000, 760, 26, 1, 12},
1530 { 12000000, 456000000, 456, 12, 1, 12},
1531 { 13000000, 456000000, 456, 13, 1, 12},
1532 { 19200000, 456000000, 380, 16, 1, 8},
1533 { 26000000, 456000000, 456, 26, 1, 12},
1536 { 12000000, 312000000, 312, 12, 1, 12},
1537 { 13000000, 312000000, 312, 13, 1, 12},
1538 { 19200000, 312000000, 260, 16, 1, 8},
1539 { 26000000, 312000000, 312, 26, 1, 12},
1541 { 0, 0, 0, 0, 0, 0 },
1544 static struct clk tegra_pll_x = {
1546 .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG,
1547 .ops = &tegra_pllx_ops,
1549 .parent = &tegra_clk_m,
1550 .max_rate = 1000000000,
1552 .input_min = 2000000,
1553 .input_max = 31000000,
1556 .vco_min = 20000000,
1557 .vco_max = 1200000000,
1558 .freq_table = tegra_pll_x_freq_table,
1563 static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
1564 { 12000000, 100000000, 200, 24, 1, 0 },
1565 { 0, 0, 0, 0, 0, 0 },
1568 static struct clk tegra_pll_e = {
1570 .flags = PLL_ALT_MISC_REG,
1571 .ops = &tegra_plle_ops,
1572 .parent = &tegra_clk_m,
1574 .max_rate = 100000000,
1576 .input_min = 12000000,
1577 .input_max = 12000000,
1578 .freq_table = tegra_pll_e_freq_table,
1582 static struct clk tegra_clk_d = {
1584 .flags = PERIPH_NO_RESET,
1585 .ops = &tegra_clk_double_ops,
1588 .parent = &tegra_clk_m,
1589 .max_rate = 52000000,
1595 /* dap_mclk1, belongs to the cdev1 pingroup. */
1596 static struct clk tegra_dev1_clk = {
1598 .ops = &tegra_cdev_clk_ops,
1600 .max_rate = 26000000,
1606 /* dap_mclk2, belongs to the cdev2 pingroup. */
1607 static struct clk tegra_dev2_clk = {
1609 .ops = &tegra_cdev_clk_ops,
1611 .max_rate = 26000000,
1617 /* initialized before peripheral clocks */
1618 static struct clk_mux_sel mux_audio_sync_clk[8+1];
1619 static const struct audio_sources {
1622 } mux_audio_sync_clk_sources[] = {
1623 { .name = "spdif_in", .value = 0 },
1624 { .name = "i2s1", .value = 1 },
1625 { .name = "i2s2", .value = 2 },
1626 { .name = "pll_a_out0", .value = 4 },
1627 #if 0 /* FIXME: not implemented */
1628 { .name = "ac97", .value = 3 },
1629 { .name = "ext_audio_clk2", .value = 5 },
1630 { .name = "ext_audio_clk1", .value = 6 },
1631 { .name = "ext_vimclk", .value = 7 },
1636 static struct clk tegra_clk_audio = {
1638 .inputs = mux_audio_sync_clk,
1640 .max_rate = 24000000,
1641 .ops = &tegra_audio_sync_clk_ops
1644 static struct clk tegra_clk_audio_2x = {
1646 .flags = PERIPH_NO_RESET,
1647 .max_rate = 48000000,
1648 .ops = &tegra_clk_double_ops,
1651 .parent = &tegra_clk_audio,
1657 struct clk_lookup tegra_audio_clk_lookups[] = {
1658 { .con_id = "audio", .clk = &tegra_clk_audio },
1659 { .con_id = "audio_2x", .clk = &tegra_clk_audio_2x }
1662 /* This is called after peripheral clocks are initialized, as the
1663 * audio_sync clock depends on some of the peripheral clocks.
1666 static void init_audio_sync_clock_mux(void)
1669 struct clk_mux_sel *sel = mux_audio_sync_clk;
1670 const struct audio_sources *src = mux_audio_sync_clk_sources;
1671 struct clk_lookup *lookup;
1673 for (i = 0; src->name; i++, sel++, src++) {
1674 sel->input = tegra_get_clock_by_name(src->name);
1676 pr_err("%s: could not find clk %s\n", __func__,
1678 sel->value = src->value;
1681 lookup = tegra_audio_clk_lookups;
1682 for (i = 0; i < ARRAY_SIZE(tegra_audio_clk_lookups); i++, lookup++) {
1683 clk_init(lookup->clk);
1688 static struct clk_mux_sel mux_cclk[] = {
1689 { .input = &tegra_clk_m, .value = 0},
1690 { .input = &tegra_pll_c, .value = 1},
1691 { .input = &tegra_clk_32k, .value = 2},
1692 { .input = &tegra_pll_m, .value = 3},
1693 { .input = &tegra_pll_p, .value = 4},
1694 { .input = &tegra_pll_p_out4, .value = 5},
1695 { .input = &tegra_pll_p_out3, .value = 6},
1696 { .input = &tegra_clk_d, .value = 7},
1697 { .input = &tegra_pll_x, .value = 8},
1701 static struct clk_mux_sel mux_sclk[] = {
1702 { .input = &tegra_clk_m, .value = 0},
1703 { .input = &tegra_pll_c_out1, .value = 1},
1704 { .input = &tegra_pll_p_out4, .value = 2},
1705 { .input = &tegra_pll_p_out3, .value = 3},
1706 { .input = &tegra_pll_p_out2, .value = 4},
1707 { .input = &tegra_clk_d, .value = 5},
1708 { .input = &tegra_clk_32k, .value = 6},
1709 { .input = &tegra_pll_m_out1, .value = 7},
1713 static struct clk tegra_clk_cclk = {
1717 .ops = &tegra_super_ops,
1718 .max_rate = 1000000000,
1721 static struct clk tegra_clk_sclk = {
1725 .ops = &tegra_super_ops,
1726 .max_rate = 600000000,
1729 static struct clk tegra_clk_virtual_cpu = {
1731 .parent = &tegra_clk_cclk,
1732 .ops = &tegra_cpu_ops,
1733 .max_rate = 1000000000,
1735 .main = &tegra_pll_x,
1736 .backup = &tegra_pll_p,
1740 static struct clk tegra_clk_hclk = {
1743 .parent = &tegra_clk_sclk,
1746 .ops = &tegra_bus_ops,
1747 .max_rate = 240000000,
1750 static struct clk tegra_clk_pclk = {
1753 .parent = &tegra_clk_hclk,
1756 .ops = &tegra_bus_ops,
1757 .max_rate = 108000000,
1760 static struct clk tegra_clk_blink = {
1762 .parent = &tegra_clk_32k,
1764 .ops = &tegra_blink_clk_ops,
1768 static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
1769 { .input = &tegra_pll_m, .value = 0},
1770 { .input = &tegra_pll_c, .value = 1},
1771 { .input = &tegra_pll_p, .value = 2},
1772 { .input = &tegra_pll_a_out0, .value = 3},
1776 static struct clk_mux_sel mux_pllm_pllc_pllp_clkm[] = {
1777 { .input = &tegra_pll_m, .value = 0},
1778 { .input = &tegra_pll_c, .value = 1},
1779 { .input = &tegra_pll_p, .value = 2},
1780 { .input = &tegra_clk_m, .value = 3},
1784 static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
1785 { .input = &tegra_pll_p, .value = 0},
1786 { .input = &tegra_pll_c, .value = 1},
1787 { .input = &tegra_pll_m, .value = 2},
1788 { .input = &tegra_clk_m, .value = 3},
1792 static struct clk_mux_sel mux_pllaout0_audio2x_pllp_clkm[] = {
1793 {.input = &tegra_pll_a_out0, .value = 0},
1794 {.input = &tegra_clk_audio_2x, .value = 1},
1795 {.input = &tegra_pll_p, .value = 2},
1796 {.input = &tegra_clk_m, .value = 3},
1800 static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = {
1801 {.input = &tegra_pll_p, .value = 0},
1802 {.input = &tegra_pll_d_out0, .value = 1},
1803 {.input = &tegra_pll_c, .value = 2},
1804 {.input = &tegra_clk_m, .value = 3},
1808 static struct clk_mux_sel mux_pllp_pllc_audio_clkm_clk32[] = {
1809 {.input = &tegra_pll_p, .value = 0},
1810 {.input = &tegra_pll_c, .value = 1},
1811 {.input = &tegra_clk_audio, .value = 2},
1812 {.input = &tegra_clk_m, .value = 3},
1813 {.input = &tegra_clk_32k, .value = 4},
1817 static struct clk_mux_sel mux_pllp_pllc_pllm[] = {
1818 {.input = &tegra_pll_p, .value = 0},
1819 {.input = &tegra_pll_c, .value = 1},
1820 {.input = &tegra_pll_m, .value = 2},
1824 static struct clk_mux_sel mux_clk_m[] = {
1825 { .input = &tegra_clk_m, .value = 0},
1829 static struct clk_mux_sel mux_pllp_out3[] = {
1830 { .input = &tegra_pll_p_out3, .value = 0},
1834 static struct clk_mux_sel mux_plld[] = {
1835 { .input = &tegra_pll_d, .value = 0},
1839 static struct clk_mux_sel mux_clk_32k[] = {
1840 { .input = &tegra_clk_32k, .value = 0},
1844 static struct clk_mux_sel mux_pclk[] = {
1845 { .input = &tegra_clk_pclk, .value = 0},
1849 #define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
1856 .ops = &tegra_periph_clk_ops, \
1858 .inputs = _inputs, \
1862 .clk_num = _clk_num, \
1866 struct clk tegra_list_clks[] = {
1867 PERIPH_CLK("apbdma", "tegra-dma", NULL, 34, 0, 108000000, mux_pclk, 0),
1868 PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET),
1869 PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0),
1870 PERIPH_CLK("i2s1", "i2s.0", NULL, 11, 0x100, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
1871 PERIPH_CLK("i2s2", "i2s.1", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
1872 /* FIXME: spdif has 2 clocks but 1 enable */
1873 PERIPH_CLK("spdif_out", "spdif_out", NULL, 10, 0x108, 100000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
1874 PERIPH_CLK("spdif_in", "spdif_in", NULL, 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71),
1875 PERIPH_CLK("pwm", "pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_audio_clkm_clk32, MUX | DIV_U71),
1876 PERIPH_CLK("spi", "spi", NULL, 43, 0x114, 40000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1877 PERIPH_CLK("xio", "xio", NULL, 45, 0x120, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1878 PERIPH_CLK("twc", "twc", NULL, 16, 0x12c, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1879 PERIPH_CLK("sbc1", "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1880 PERIPH_CLK("sbc2", "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1881 PERIPH_CLK("sbc3", "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1882 PERIPH_CLK("sbc4", "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1883 PERIPH_CLK("ide", "ide", NULL, 25, 0x144, 100000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */
1884 PERIPH_CLK("ndflash", "tegra_nand", NULL, 13, 0x160, 164000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
1885 /* FIXME: vfir shares an enable with uartb */
1886 PERIPH_CLK("vfir", "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1887 PERIPH_CLK("sdmmc1", "sdhci-tegra.0", NULL, 14, 0x150, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
1888 PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
1889 PERIPH_CLK("sdmmc3", "sdhci-tegra.2", NULL, 69, 0x1bc, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
1890 PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x164, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
1891 PERIPH_CLK("vde", "vde", NULL, 61, 0x1c8, 250000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage and process_id */
1892 PERIPH_CLK("csite", "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* max rate ??? */
1893 /* FIXME: what is la? */
1894 PERIPH_CLK("la", "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1895 PERIPH_CLK("owr", "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1896 PERIPH_CLK("nor", "nor", NULL, 42, 0x1d0, 92000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */
1897 PERIPH_CLK("mipi", "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
1898 PERIPH_CLK("i2c1", "tegra-i2c.0", NULL, 12, 0x124, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
1899 PERIPH_CLK("i2c2", "tegra-i2c.1", NULL, 54, 0x198, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
1900 PERIPH_CLK("i2c3", "tegra-i2c.2", NULL, 67, 0x1b8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
1901 PERIPH_CLK("dvc", "tegra-i2c.3", NULL, 47, 0x128, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
1902 PERIPH_CLK("i2c1_i2c", "tegra-i2c.0", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
1903 PERIPH_CLK("i2c2_i2c", "tegra-i2c.1", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
1904 PERIPH_CLK("i2c3_i2c", "tegra-i2c.2", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
1905 PERIPH_CLK("dvc_i2c", "tegra-i2c.3", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
1906 PERIPH_CLK("uarta", "uart.0", NULL, 6, 0x178, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
1907 PERIPH_CLK("uartb", "uart.1", NULL, 7, 0x17c, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
1908 PERIPH_CLK("uartc", "uart.2", NULL, 55, 0x1a0, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
1909 PERIPH_CLK("uartd", "uart.3", NULL, 65, 0x1c0, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
1910 PERIPH_CLK("uarte", "uart.4", NULL, 66, 0x1c4, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
1911 PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_MANUAL_RESET), /* scales with voltage and process_id */
1912 PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
1913 /* FIXME: vi and vi_sensor share an enable */
1914 PERIPH_CLK("vi", "tegra_camera", "vi", 20, 0x148, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
1915 PERIPH_CLK("vi_sensor", "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET), /* scales with voltage and process_id */
1916 PERIPH_CLK("epp", "epp", NULL, 19, 0x16c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
1917 PERIPH_CLK("mpe", "mpe", NULL, 60, 0x170, 250000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
1918 PERIPH_CLK("host1x", "host1x", NULL, 28, 0x180, 166000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
1919 /* FIXME: cve and tvo share an enable */
1920 PERIPH_CLK("cve", "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
1921 PERIPH_CLK("tvo", "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
1922 PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, 600000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
1923 PERIPH_CLK("tvdac", "tvdac", NULL, 53, 0x194, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
1924 PERIPH_CLK("disp1", "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* scales with voltage and process_id */
1925 PERIPH_CLK("disp2", "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* scales with voltage and process_id */
1926 PERIPH_CLK("usbd", "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
1927 PERIPH_CLK("usb2", "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
1928 PERIPH_CLK("usb3", "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
1929 PERIPH_CLK("emc", "emc", NULL, 57, 0x19c, 800000000, mux_pllm_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_EMC_ENB),
1930 PERIPH_CLK("dsi", "dsi", NULL, 48, 0, 500000000, mux_plld, 0), /* scales with voltage */
1931 PERIPH_CLK("csi", "tegra_camera", "csi", 52, 0, 72000000, mux_pllp_out3, 0),
1932 PERIPH_CLK("isp", "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0), /* same frequency as VI */
1933 PERIPH_CLK("csus", "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET),
1934 PERIPH_CLK("pex", NULL, "pex", 70, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET),
1935 PERIPH_CLK("afi", NULL, "afi", 72, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET),
1936 PERIPH_CLK("pcie_xclk", NULL, "pcie_xclk", 74, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET),
1939 #define CLK_DUPLICATE(_name, _dev, _con) \
1948 /* Some clocks may be used by different drivers depending on the board
1949 * configuration. List those here to register them twice in the clock lookup
1950 * table under two names.
1952 struct clk_duplicate tegra_clk_duplicates[] = {
1953 CLK_DUPLICATE("uarta", "tegra_uart.0", NULL),
1954 CLK_DUPLICATE("uartb", "tegra_uart.1", NULL),
1955 CLK_DUPLICATE("uartc", "tegra_uart.2", NULL),
1956 CLK_DUPLICATE("uartd", "tegra_uart.3", NULL),
1957 CLK_DUPLICATE("uarte", "tegra_uart.4", NULL),
1958 CLK_DUPLICATE("usbd", "utmip-pad", NULL),
1959 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
1960 CLK_DUPLICATE("usbd", "tegra-otg", NULL),
1961 CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
1962 CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
1963 CLK_DUPLICATE("pwm", "tegra_pwm.0", NULL),
1964 CLK_DUPLICATE("pwm", "tegra_pwm.1", NULL),
1965 CLK_DUPLICATE("pwm", "tegra_pwm.2", NULL),
1966 CLK_DUPLICATE("pwm", "tegra_pwm.3", NULL),
1969 #define CLK(dev, con, ck) \
1976 struct clk *tegra_ptr_clks[] = {
2003 &tegra_clk_virtual_cpu,
2007 static void tegra2_init_one_clock(struct clk *c)
2010 if (!c->lookup.dev_id && !c->lookup.con_id)
2011 c->lookup.con_id = c->name;
2013 clkdev_add(&c->lookup);
2016 void __init tegra2_init_clocks(void)
2021 for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
2022 tegra2_init_one_clock(tegra_ptr_clks[i]);
2024 for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
2025 tegra2_init_one_clock(&tegra_list_clks[i]);
2027 for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
2028 c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
2030 pr_err("%s: Unknown duplicate clock %s\n", __func__,
2031 tegra_clk_duplicates[i].name);
2035 tegra_clk_duplicates[i].lookup.clk = c;
2036 clkdev_add(&tegra_clk_duplicates[i].lookup);
2039 init_audio_sync_clock_mux();
2043 static u32 clk_rst_suspend[RST_DEVICES_NUM + CLK_OUT_ENB_NUM +
2044 PERIPH_CLK_SOURCE_NUM + 19];
2046 void tegra_clk_suspend(void)
2048 unsigned long off, i;
2049 u32 *ctx = clk_rst_suspend;
2051 *ctx++ = clk_readl(OSC_CTRL) & OSC_CTRL_MASK;
2052 *ctx++ = clk_readl(tegra_pll_p.reg + PLL_BASE);
2053 *ctx++ = clk_readl(tegra_pll_p.reg + PLL_MISC(&tegra_pll_p));
2054 *ctx++ = clk_readl(tegra_pll_c.reg + PLL_BASE);
2055 *ctx++ = clk_readl(tegra_pll_c.reg + PLL_MISC(&tegra_pll_c));
2056 *ctx++ = clk_readl(tegra_pll_a.reg + PLL_BASE);
2057 *ctx++ = clk_readl(tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
2059 *ctx++ = clk_readl(tegra_pll_m_out1.reg);
2060 *ctx++ = clk_readl(tegra_pll_p_out1.reg);
2061 *ctx++ = clk_readl(tegra_pll_p_out3.reg);
2062 *ctx++ = clk_readl(tegra_pll_a_out0.reg);
2063 *ctx++ = clk_readl(tegra_pll_c_out1.reg);
2065 *ctx++ = clk_readl(tegra_clk_cclk.reg);
2066 *ctx++ = clk_readl(tegra_clk_cclk.reg + SUPER_CLK_DIVIDER);
2068 *ctx++ = clk_readl(tegra_clk_sclk.reg);
2069 *ctx++ = clk_readl(tegra_clk_sclk.reg + SUPER_CLK_DIVIDER);
2070 *ctx++ = clk_readl(tegra_clk_pclk.reg);
2072 for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC;
2074 if (off == PERIPH_CLK_SOURCE_EMC)
2076 *ctx++ = clk_readl(off);
2080 for (i = 0; i < RST_DEVICES_NUM; i++, off += 4)
2081 *ctx++ = clk_readl(off);
2084 for (i = 0; i < CLK_OUT_ENB_NUM; i++, off += 4)
2085 *ctx++ = clk_readl(off);
2087 *ctx++ = clk_readl(MISC_CLK_ENB);
2088 *ctx++ = clk_readl(CLK_MASK_ARM);
2091 void tegra_clk_resume(void)
2093 unsigned long off, i;
2094 const u32 *ctx = clk_rst_suspend;
2097 val = clk_readl(OSC_CTRL) & ~OSC_CTRL_MASK;
2099 clk_writel(val, OSC_CTRL);
2101 clk_writel(*ctx++, tegra_pll_p.reg + PLL_BASE);
2102 clk_writel(*ctx++, tegra_pll_p.reg + PLL_MISC(&tegra_pll_p));
2103 clk_writel(*ctx++, tegra_pll_c.reg + PLL_BASE);
2104 clk_writel(*ctx++, tegra_pll_c.reg + PLL_MISC(&tegra_pll_c));
2105 clk_writel(*ctx++, tegra_pll_a.reg + PLL_BASE);
2106 clk_writel(*ctx++, tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
2109 clk_writel(*ctx++, tegra_pll_m_out1.reg);
2110 clk_writel(*ctx++, tegra_pll_p_out1.reg);
2111 clk_writel(*ctx++, tegra_pll_p_out3.reg);
2112 clk_writel(*ctx++, tegra_pll_a_out0.reg);
2113 clk_writel(*ctx++, tegra_pll_c_out1.reg);
2115 clk_writel(*ctx++, tegra_clk_cclk.reg);
2116 clk_writel(*ctx++, tegra_clk_cclk.reg + SUPER_CLK_DIVIDER);
2118 clk_writel(*ctx++, tegra_clk_sclk.reg);
2119 clk_writel(*ctx++, tegra_clk_sclk.reg + SUPER_CLK_DIVIDER);
2120 clk_writel(*ctx++, tegra_clk_pclk.reg);
2122 /* enable all clocks before configuring clock sources */
2123 clk_writel(0xbffffff9ul, CLK_OUT_ENB);
2124 clk_writel(0xfefffff7ul, CLK_OUT_ENB + 4);
2125 clk_writel(0x77f01bfful, CLK_OUT_ENB + 8);
2128 for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC;
2130 if (off == PERIPH_CLK_SOURCE_EMC)
2132 clk_writel(*ctx++, off);
2137 for (i = 0; i < RST_DEVICES_NUM; i++, off += 4)
2138 clk_writel(*ctx++, off);
2142 for (i = 0; i < CLK_OUT_ENB_NUM; i++, off += 4)
2143 clk_writel(*ctx++, off);
2146 clk_writel(*ctx++, MISC_CLK_ENB);
2147 clk_writel(*ctx++, CLK_MASK_ARM);