2 * arch/arm/mach-tegra/tegra2_clocks.c
4 * Copyright (C) 2010 Google, Inc.
7 * Colin Cross <ccross@google.com>
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/list.h>
23 #include <linux/spinlock.h>
24 #include <linux/delay.h>
26 #include <linux/hrtimer.h>
27 #include <linux/clkdev.h>
29 #include <mach/iomap.h>
30 #include <mach/suspend.h>
35 #define RST_DEVICES 0x004
36 #define RST_DEVICES_SET 0x300
37 #define RST_DEVICES_CLR 0x304
38 #define RST_DEVICES_NUM 3
40 #define CLK_OUT_ENB 0x010
41 #define CLK_OUT_ENB_SET 0x320
42 #define CLK_OUT_ENB_CLR 0x324
43 #define CLK_OUT_ENB_NUM 3
45 #define CLK_MASK_ARM 0x44
46 #define MISC_CLK_ENB 0x48
49 #define OSC_CTRL_OSC_FREQ_MASK (3<<30)
50 #define OSC_CTRL_OSC_FREQ_13MHZ (0<<30)
51 #define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30)
52 #define OSC_CTRL_OSC_FREQ_12MHZ (2<<30)
53 #define OSC_CTRL_OSC_FREQ_26MHZ (3<<30)
54 #define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
56 #define OSC_FREQ_DET 0x58
57 #define OSC_FREQ_DET_TRIG (1<<31)
59 #define OSC_FREQ_DET_STATUS 0x5C
60 #define OSC_FREQ_DET_BUSY (1<<31)
61 #define OSC_FREQ_DET_CNT_MASK 0xFFFF
63 #define PERIPH_CLK_SOURCE_I2S1 0x100
64 #define PERIPH_CLK_SOURCE_EMC 0x19c
65 #define PERIPH_CLK_SOURCE_OSC 0x1fc
66 #define PERIPH_CLK_SOURCE_NUM \
67 ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4)
69 #define PERIPH_CLK_SOURCE_MASK (3<<30)
70 #define PERIPH_CLK_SOURCE_SHIFT 30
71 #define PERIPH_CLK_SOURCE_ENABLE (1<<28)
72 #define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF
73 #define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF
74 #define PERIPH_CLK_SOURCE_DIV_SHIFT 0
77 #define PLL_BASE_BYPASS (1<<31)
78 #define PLL_BASE_ENABLE (1<<30)
79 #define PLL_BASE_REF_ENABLE (1<<29)
80 #define PLL_BASE_OVERRIDE (1<<28)
81 #define PLL_BASE_DIVP_MASK (0x7<<20)
82 #define PLL_BASE_DIVP_SHIFT 20
83 #define PLL_BASE_DIVN_MASK (0x3FF<<8)
84 #define PLL_BASE_DIVN_SHIFT 8
85 #define PLL_BASE_DIVM_MASK (0x1F)
86 #define PLL_BASE_DIVM_SHIFT 0
88 #define PLL_OUT_RATIO_MASK (0xFF<<8)
89 #define PLL_OUT_RATIO_SHIFT 8
90 #define PLL_OUT_OVERRIDE (1<<2)
91 #define PLL_OUT_CLKEN (1<<1)
92 #define PLL_OUT_RESET_DISABLE (1<<0)
94 #define PLL_MISC(c) (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)
96 #define PLL_MISC_DCCON_SHIFT 20
97 #define PLL_MISC_CPCON_SHIFT 8
98 #define PLL_MISC_CPCON_MASK (0xF<<PLL_MISC_CPCON_SHIFT)
99 #define PLL_MISC_LFCON_SHIFT 4
100 #define PLL_MISC_LFCON_MASK (0xF<<PLL_MISC_LFCON_SHIFT)
101 #define PLL_MISC_VCOCON_SHIFT 0
102 #define PLL_MISC_VCOCON_MASK (0xF<<PLL_MISC_VCOCON_SHIFT)
104 #define PLLU_BASE_POST_DIV (1<<20)
106 #define PLLD_MISC_CLKENABLE (1<<30)
107 #define PLLD_MISC_DIV_RST (1<<23)
108 #define PLLD_MISC_DCCON_SHIFT 12
110 #define PLLE_MISC_READY (1 << 15)
112 #define PERIPH_CLK_TO_ENB_REG(c) ((c->clk_num / 32) * 4)
113 #define PERIPH_CLK_TO_ENB_SET_REG(c) ((c->clk_num / 32) * 8)
114 #define PERIPH_CLK_TO_ENB_BIT(c) (1 << (c->clk_num % 32))
116 #define SUPER_CLK_MUX 0x00
117 #define SUPER_STATE_SHIFT 28
118 #define SUPER_STATE_MASK (0xF << SUPER_STATE_SHIFT)
119 #define SUPER_STATE_STANDBY (0x0 << SUPER_STATE_SHIFT)
120 #define SUPER_STATE_IDLE (0x1 << SUPER_STATE_SHIFT)
121 #define SUPER_STATE_RUN (0x2 << SUPER_STATE_SHIFT)
122 #define SUPER_STATE_IRQ (0x3 << SUPER_STATE_SHIFT)
123 #define SUPER_STATE_FIQ (0x4 << SUPER_STATE_SHIFT)
124 #define SUPER_SOURCE_MASK 0xF
125 #define SUPER_FIQ_SOURCE_SHIFT 12
126 #define SUPER_IRQ_SOURCE_SHIFT 8
127 #define SUPER_RUN_SOURCE_SHIFT 4
128 #define SUPER_IDLE_SOURCE_SHIFT 0
130 #define SUPER_CLK_DIVIDER 0x04
132 #define BUS_CLK_DISABLE (1<<3)
133 #define BUS_CLK_DIV_MASK 0x3
136 #define PMC_CTRL_BLINK_ENB (1 << 7)
138 #define PMC_DPD_PADS_ORIDE 0x1c
139 #define PMC_DPD_PADS_ORIDE_BLINK_ENB (1 << 20)
141 #define PMC_BLINK_TIMER_DATA_ON_SHIFT 0
142 #define PMC_BLINK_TIMER_DATA_ON_MASK 0x7fff
143 #define PMC_BLINK_TIMER_ENB (1 << 15)
144 #define PMC_BLINK_TIMER_DATA_OFF_SHIFT 16
145 #define PMC_BLINK_TIMER_DATA_OFF_MASK 0xffff
147 static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
148 static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
150 #define clk_writel(value, reg) \
151 __raw_writel(value, (u32)reg_clk_base + (reg))
152 #define clk_readl(reg) \
153 __raw_readl((u32)reg_clk_base + (reg))
154 #define pmc_writel(value, reg) \
155 __raw_writel(value, (u32)reg_pmc_base + (reg))
156 #define pmc_readl(reg) \
157 __raw_readl((u32)reg_pmc_base + (reg))
159 unsigned long clk_measure_input_freq(void)
161 u32 clock_autodetect;
162 clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET);
163 do {} while (clk_readl(OSC_FREQ_DET_STATUS) & OSC_FREQ_DET_BUSY);
164 clock_autodetect = clk_readl(OSC_FREQ_DET_STATUS);
165 if (clock_autodetect >= 732 - 3 && clock_autodetect <= 732 + 3) {
167 } else if (clock_autodetect >= 794 - 3 && clock_autodetect <= 794 + 3) {
169 } else if (clock_autodetect >= 1172 - 3 && clock_autodetect <= 1172 + 3) {
171 } else if (clock_autodetect >= 1587 - 3 && clock_autodetect <= 1587 + 3) {
174 pr_err("%s: Unexpected clock autodetect value %d", __func__, clock_autodetect);
180 static int clk_div71_get_divider(unsigned long parent_rate, unsigned long rate)
182 s64 divider_u71 = parent_rate * 2;
183 divider_u71 += rate - 1;
184 do_div(divider_u71, rate);
186 if (divider_u71 - 2 < 0)
189 if (divider_u71 - 2 > 255)
192 return divider_u71 - 2;
195 static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
199 divider_u16 = parent_rate;
200 divider_u16 += rate - 1;
201 do_div(divider_u16, rate);
203 if (divider_u16 - 1 < 0)
206 if (divider_u16 - 1 > 255)
209 return divider_u16 - 1;
212 /* clk_m functions */
213 static unsigned long tegra2_clk_m_autodetect_rate(struct clk *c)
215 u32 auto_clock_control = clk_readl(OSC_CTRL) & ~OSC_CTRL_OSC_FREQ_MASK;
217 c->rate = clk_measure_input_freq();
220 auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
223 auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ;
226 auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ;
229 auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ;
232 pr_err("%s: Unexpected clock rate %ld", __func__, c->rate);
235 clk_writel(auto_clock_control, OSC_CTRL);
239 static void tegra2_clk_m_init(struct clk *c)
241 pr_debug("%s on clock %s\n", __func__, c->name);
242 tegra2_clk_m_autodetect_rate(c);
245 static int tegra2_clk_m_enable(struct clk *c)
247 pr_debug("%s on clock %s\n", __func__, c->name);
251 static void tegra2_clk_m_disable(struct clk *c)
253 pr_debug("%s on clock %s\n", __func__, c->name);
257 static struct clk_ops tegra_clk_m_ops = {
258 .init = tegra2_clk_m_init,
259 .enable = tegra2_clk_m_enable,
260 .disable = tegra2_clk_m_disable,
263 void tegra2_periph_reset_assert(struct clk *c)
265 BUG_ON(!c->ops->reset);
266 c->ops->reset(c, true);
269 void tegra2_periph_reset_deassert(struct clk *c)
271 BUG_ON(!c->ops->reset);
272 c->ops->reset(c, false);
275 /* super clock functions */
276 /* "super clocks" on tegra have two-stage muxes and a clock skipping
277 * super divider. We will ignore the clock skipping divider, since we
278 * can't lower the voltage when using the clock skip, but we can if we
279 * lower the PLL frequency.
281 static void tegra2_super_clk_init(struct clk *c)
286 const struct clk_mux_sel *sel;
287 val = clk_readl(c->reg + SUPER_CLK_MUX);
289 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
290 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
291 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
292 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
293 source = (val >> shift) & SUPER_SOURCE_MASK;
294 for (sel = c->inputs; sel->input != NULL; sel++) {
295 if (sel->value == source)
298 BUG_ON(sel->input == NULL);
299 c->parent = sel->input;
302 static int tegra2_super_clk_enable(struct clk *c)
304 clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
308 static void tegra2_super_clk_disable(struct clk *c)
310 pr_debug("%s on clock %s\n", __func__, c->name);
312 /* oops - don't disable the CPU clock! */
316 static int tegra2_super_clk_set_parent(struct clk *c, struct clk *p)
319 const struct clk_mux_sel *sel;
322 val = clk_readl(c->reg + SUPER_CLK_MUX);;
323 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
324 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
325 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
326 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
327 for (sel = c->inputs; sel->input != NULL; sel++) {
328 if (sel->input == p) {
329 val &= ~(SUPER_SOURCE_MASK << shift);
330 val |= sel->value << shift;
333 clk_enable_locked(p);
335 clk_writel(val, c->reg);
337 if (c->refcnt && c->parent)
338 clk_disable_locked(c->parent);
347 static struct clk_ops tegra_super_ops = {
348 .init = tegra2_super_clk_init,
349 .enable = tegra2_super_clk_enable,
350 .disable = tegra2_super_clk_disable,
351 .set_parent = tegra2_super_clk_set_parent,
354 /* virtual cpu clock functions */
355 /* some clocks can not be stopped (cpu, memory bus) while the SoC is running.
356 To change the frequency of these clocks, the parent pll may need to be
357 reprogrammed, so the clock must be moved off the pll, the pll reprogrammed,
358 and then the clock moved back to the pll. To hide this sequence, a virtual
361 static void tegra2_cpu_clk_init(struct clk *c)
365 static int tegra2_cpu_clk_enable(struct clk *c)
370 static void tegra2_cpu_clk_disable(struct clk *c)
372 pr_debug("%s on clock %s\n", __func__, c->name);
374 /* oops - don't disable the CPU clock! */
378 static int tegra2_cpu_clk_set_rate(struct clk *c, unsigned long rate)
381 ret = clk_set_parent_locked(c->parent, c->backup);
383 pr_err("Failed to switch cpu to clock %s\n", c->backup->name);
387 if (rate == c->backup->rate)
390 ret = clk_set_rate_locked(c->main, rate);
392 pr_err("Failed to change cpu pll to %lu\n", rate);
396 ret = clk_set_parent_locked(c->parent, c->main);
398 pr_err("Failed to switch cpu to clock %s\n", c->main->name);
406 static struct clk_ops tegra_cpu_ops = {
407 .init = tegra2_cpu_clk_init,
408 .enable = tegra2_cpu_clk_enable,
409 .disable = tegra2_cpu_clk_disable,
410 .set_rate = tegra2_cpu_clk_set_rate,
413 /* bus clock functions */
414 static void tegra2_bus_clk_init(struct clk *c)
416 u32 val = clk_readl(c->reg);
417 c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON;
418 c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1;
422 static int tegra2_bus_clk_enable(struct clk *c)
424 u32 val = clk_readl(c->reg);
425 val &= ~(BUS_CLK_DISABLE << c->reg_shift);
426 clk_writel(val, c->reg);
430 static void tegra2_bus_clk_disable(struct clk *c)
432 u32 val = clk_readl(c->reg);
433 val |= BUS_CLK_DISABLE << c->reg_shift;
434 clk_writel(val, c->reg);
437 static int tegra2_bus_clk_set_rate(struct clk *c, unsigned long rate)
439 u32 val = clk_readl(c->reg);
440 unsigned long parent_rate = c->parent->rate;
442 for (i = 1; i <= 4; i++) {
443 if (rate == parent_rate / i) {
444 val &= ~(BUS_CLK_DIV_MASK << c->reg_shift);
445 val |= (i - 1) << c->reg_shift;
446 clk_writel(val, c->reg);
455 static struct clk_ops tegra_bus_ops = {
456 .init = tegra2_bus_clk_init,
457 .enable = tegra2_bus_clk_enable,
458 .disable = tegra2_bus_clk_disable,
459 .set_rate = tegra2_bus_clk_set_rate,
462 /* Blink output functions */
464 static void tegra2_blink_clk_init(struct clk *c)
468 val = pmc_readl(PMC_CTRL);
469 c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF;
471 val = pmc_readl(c->reg);
473 if (val & PMC_BLINK_TIMER_ENB) {
476 on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
477 PMC_BLINK_TIMER_DATA_ON_MASK;
478 val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
479 val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
481 /* each tick in the blink timer is 4 32KHz clocks */
488 static int tegra2_blink_clk_enable(struct clk *c)
492 val = pmc_readl(PMC_DPD_PADS_ORIDE);
493 pmc_writel(val | PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
495 val = pmc_readl(PMC_CTRL);
496 pmc_writel(val | PMC_CTRL_BLINK_ENB, PMC_CTRL);
501 static void tegra2_blink_clk_disable(struct clk *c)
505 val = pmc_readl(PMC_CTRL);
506 pmc_writel(val & ~PMC_CTRL_BLINK_ENB, PMC_CTRL);
508 val = pmc_readl(PMC_DPD_PADS_ORIDE);
509 pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
512 static int tegra2_blink_clk_set_rate(struct clk *c, unsigned long rate)
514 if (rate >= c->parent->rate) {
516 pmc_writel(0, c->reg);
521 on_off = DIV_ROUND_UP(c->parent->rate / 8, rate);
524 val = (on_off & PMC_BLINK_TIMER_DATA_ON_MASK) <<
525 PMC_BLINK_TIMER_DATA_ON_SHIFT;
526 on_off &= PMC_BLINK_TIMER_DATA_OFF_MASK;
527 on_off <<= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
529 val |= PMC_BLINK_TIMER_ENB;
530 pmc_writel(val, c->reg);
536 static struct clk_ops tegra_blink_clk_ops = {
537 .init = &tegra2_blink_clk_init,
538 .enable = &tegra2_blink_clk_enable,
539 .disable = &tegra2_blink_clk_disable,
540 .set_rate = &tegra2_blink_clk_set_rate,
544 static int tegra2_pll_clk_wait_for_lock(struct clk *c)
546 udelay(c->pll_lock_delay);
551 static void tegra2_pll_clk_init(struct clk *c)
553 u32 val = clk_readl(c->reg + PLL_BASE);
555 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
557 if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
558 pr_warning("Clock %s has unknown fixed frequency\n", c->name);
561 } else if (val & PLL_BASE_BYPASS) {
565 c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
566 c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
568 c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
570 c->div *= (val & PLL_BASE_DIVP_MASK) ? 2 : 1;
574 static int tegra2_pll_clk_enable(struct clk *c)
577 pr_debug("%s on clock %s\n", __func__, c->name);
579 val = clk_readl(c->reg + PLL_BASE);
580 val &= ~PLL_BASE_BYPASS;
581 val |= PLL_BASE_ENABLE;
582 clk_writel(val, c->reg + PLL_BASE);
584 tegra2_pll_clk_wait_for_lock(c);
589 static void tegra2_pll_clk_disable(struct clk *c)
592 pr_debug("%s on clock %s\n", __func__, c->name);
594 val = clk_readl(c->reg);
595 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
596 clk_writel(val, c->reg);
599 static int tegra2_pll_clk_set_rate(struct clk *c, unsigned long rate)
602 unsigned long input_rate;
603 const struct clk_pll_table *sel;
605 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
607 input_rate = c->parent->rate;
608 for (sel = c->pll_table; sel->input_rate != 0; sel++) {
609 if (sel->input_rate == input_rate && sel->output_rate == rate) {
611 c->div = sel->m * sel->p;
613 val = clk_readl(c->reg + PLL_BASE);
614 if (c->flags & PLL_FIXED)
615 val |= PLL_BASE_OVERRIDE;
616 val &= ~(PLL_BASE_DIVP_MASK | PLL_BASE_DIVN_MASK |
618 val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
619 (sel->n << PLL_BASE_DIVN_SHIFT);
620 BUG_ON(sel->p < 1 || sel->p > 2);
621 if (c->flags & PLLU) {
623 val |= PLLU_BASE_POST_DIV;
626 val |= 1 << PLL_BASE_DIVP_SHIFT;
628 clk_writel(val, c->reg + PLL_BASE);
630 if (c->flags & PLL_HAS_CPCON) {
631 val = clk_readl(c->reg + PLL_MISC(c));
632 val &= ~PLL_MISC_CPCON_MASK;
633 val |= sel->cpcon << PLL_MISC_CPCON_SHIFT;
634 clk_writel(val, c->reg + PLL_MISC(c));
638 tegra2_pll_clk_enable(c);
646 static struct clk_ops tegra_pll_ops = {
647 .init = tegra2_pll_clk_init,
648 .enable = tegra2_pll_clk_enable,
649 .disable = tegra2_pll_clk_disable,
650 .set_rate = tegra2_pll_clk_set_rate,
653 static void tegra2_pllx_clk_init(struct clk *c)
655 tegra2_pll_clk_init(c);
657 if (tegra_sku_id() == 7)
658 c->max_rate = 750000000;
661 static struct clk_ops tegra_pllx_ops = {
662 .init = tegra2_pllx_clk_init,
663 .enable = tegra2_pll_clk_enable,
664 .disable = tegra2_pll_clk_disable,
665 .set_rate = tegra2_pll_clk_set_rate,
668 static int tegra2_plle_clk_enable(struct clk *c)
672 pr_debug("%s on clock %s\n", __func__, c->name);
676 val = clk_readl(c->reg + PLL_BASE);
677 if (!(val & PLLE_MISC_READY))
680 val = clk_readl(c->reg + PLL_BASE);
681 val |= PLL_BASE_ENABLE | PLL_BASE_BYPASS;
682 clk_writel(val, c->reg + PLL_BASE);
687 static struct clk_ops tegra_plle_ops = {
688 .init = tegra2_pll_clk_init,
689 .enable = tegra2_plle_clk_enable,
690 .set_rate = tegra2_pll_clk_set_rate,
693 /* Clock divider ops */
694 static void tegra2_pll_div_clk_init(struct clk *c)
696 u32 val = clk_readl(c->reg);
698 val >>= c->reg_shift;
699 c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
700 if (!(val & PLL_OUT_RESET_DISABLE))
703 if (c->flags & DIV_U71) {
704 divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
705 c->div = (divu71 + 2);
707 } else if (c->flags & DIV_2) {
716 static int tegra2_pll_div_clk_enable(struct clk *c)
721 pr_debug("%s: %s\n", __func__, c->name);
722 if (c->flags & DIV_U71) {
723 val = clk_readl(c->reg);
724 new_val = val >> c->reg_shift;
727 new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
729 val &= ~(0xFFFF << c->reg_shift);
730 val |= new_val << c->reg_shift;
731 clk_writel(val, c->reg);
733 } else if (c->flags & DIV_2) {
734 BUG_ON(!(c->flags & PLLD));
735 val = clk_readl(c->reg);
736 val &= ~PLLD_MISC_DIV_RST;
737 clk_writel(val, c->reg);
743 static void tegra2_pll_div_clk_disable(struct clk *c)
748 pr_debug("%s: %s\n", __func__, c->name);
749 if (c->flags & DIV_U71) {
750 val = clk_readl(c->reg);
751 new_val = val >> c->reg_shift;
754 new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE);
756 val &= ~(0xFFFF << c->reg_shift);
757 val |= new_val << c->reg_shift;
758 clk_writel(val, c->reg);
759 } else if (c->flags & DIV_2) {
760 BUG_ON(!(c->flags & PLLD));
761 val = clk_readl(c->reg);
762 val |= PLLD_MISC_DIV_RST;
763 clk_writel(val, c->reg);
767 static int tegra2_pll_div_clk_set_rate(struct clk *c, unsigned long rate)
772 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
773 if (c->flags & DIV_U71) {
774 divider_u71 = clk_div71_get_divider(c->parent->rate, rate);
775 if (divider_u71 >= 0) {
776 val = clk_readl(c->reg);
777 new_val = val >> c->reg_shift;
779 if (c->flags & DIV_U71_FIXED)
780 new_val |= PLL_OUT_OVERRIDE;
781 new_val &= ~PLL_OUT_RATIO_MASK;
782 new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT;
784 val &= ~(0xFFFF << c->reg_shift);
785 val |= new_val << c->reg_shift;
786 clk_writel(val, c->reg);
787 c->div = divider_u71 + 2;
791 } else if (c->flags & DIV_2) {
792 if (c->parent->rate == rate * 2)
798 static long tegra2_pll_div_clk_round_rate(struct clk *c, unsigned long rate)
801 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
803 if (c->flags & DIV_U71) {
804 divider = clk_div71_get_divider(c->parent->rate, rate);
807 return c->parent->rate * 2 / (divider + 2);
808 } else if (c->flags & DIV_2) {
809 return c->parent->rate / 2;
814 static struct clk_ops tegra_pll_div_ops = {
815 .init = tegra2_pll_div_clk_init,
816 .enable = tegra2_pll_div_clk_enable,
817 .disable = tegra2_pll_div_clk_disable,
818 .set_rate = tegra2_pll_div_clk_set_rate,
819 .round_rate = tegra2_pll_div_clk_round_rate,
824 static void tegra2_periph_clk_init(struct clk *c)
826 u32 val = clk_readl(c->reg);
827 const struct clk_mux_sel *mux = 0;
828 const struct clk_mux_sel *sel;
829 if (c->flags & MUX) {
830 for (sel = c->inputs; sel->input != NULL; sel++) {
831 if (val >> PERIPH_CLK_SOURCE_SHIFT == sel->value)
836 c->parent = mux->input;
838 c->parent = c->inputs[0].input;
841 if (c->flags & DIV_U71) {
842 u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
845 } else if (c->flags & DIV_U16) {
846 u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
855 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
856 PERIPH_CLK_TO_ENB_BIT(c)))
858 if (!(c->flags & PERIPH_NO_RESET))
859 if (clk_readl(RST_DEVICES + PERIPH_CLK_TO_ENB_REG(c)) &
860 PERIPH_CLK_TO_ENB_BIT(c))
864 static int tegra2_periph_clk_enable(struct clk *c)
867 pr_debug("%s on clock %s\n", __func__, c->name);
869 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
870 CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
871 if (!(c->flags & PERIPH_NO_RESET) && !(c->flags & PERIPH_MANUAL_RESET))
872 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
873 RST_DEVICES_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
874 if (c->flags & PERIPH_EMC_ENB) {
875 /* The EMC peripheral clock has 2 extra enable bits */
876 /* FIXME: Do they need to be disabled? */
877 val = clk_readl(c->reg);
879 clk_writel(val, c->reg);
884 static void tegra2_periph_clk_disable(struct clk *c)
886 pr_debug("%s on clock %s\n", __func__, c->name);
888 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
889 CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
892 static void tegra2_periph_clk_reset(struct clk *c, bool assert)
894 unsigned long base = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
896 pr_debug("%s %s on clock %s\n", __func__,
897 assert ? "assert" : "deassert", c->name);
898 if (!(c->flags & PERIPH_NO_RESET))
899 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
900 base + PERIPH_CLK_TO_ENB_SET_REG(c));
903 static int tegra2_periph_clk_set_parent(struct clk *c, struct clk *p)
906 const struct clk_mux_sel *sel;
907 pr_debug("%s: %s %s\n", __func__, c->name, p->name);
908 for (sel = c->inputs; sel->input != NULL; sel++) {
909 if (sel->input == p) {
910 val = clk_readl(c->reg);
911 val &= ~PERIPH_CLK_SOURCE_MASK;
912 val |= (sel->value) << PERIPH_CLK_SOURCE_SHIFT;
915 clk_enable_locked(p);
917 clk_writel(val, c->reg);
919 if (c->refcnt && c->parent)
920 clk_disable_locked(c->parent);
930 static int tegra2_periph_clk_set_rate(struct clk *c, unsigned long rate)
934 pr_debug("%s: %lu\n", __func__, rate);
935 if (c->flags & DIV_U71) {
936 divider = clk_div71_get_divider(c->parent->rate, rate);
938 val = clk_readl(c->reg);
939 val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK;
941 clk_writel(val, c->reg);
942 c->div = divider + 2;
946 } else if (c->flags & DIV_U16) {
947 divider = clk_div16_get_divider(c->parent->rate, rate);
949 val = clk_readl(c->reg);
950 val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK;
952 clk_writel(val, c->reg);
953 c->div = divider + 1;
957 } else if (c->parent->rate <= rate) {
965 static long tegra2_periph_clk_round_rate(struct clk *c,
969 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
971 if (c->flags & DIV_U71) {
972 divider = clk_div71_get_divider(c->parent->rate, rate);
976 return c->parent->rate * 2 / (divider + 2);
977 } else if (c->flags & DIV_U16) {
978 divider = clk_div16_get_divider(c->parent->rate, rate);
981 return c->parent->rate / (divider + 1);
986 static struct clk_ops tegra_periph_clk_ops = {
987 .init = &tegra2_periph_clk_init,
988 .enable = &tegra2_periph_clk_enable,
989 .disable = &tegra2_periph_clk_disable,
990 .set_parent = &tegra2_periph_clk_set_parent,
991 .set_rate = &tegra2_periph_clk_set_rate,
992 .round_rate = &tegra2_periph_clk_round_rate,
993 .reset = &tegra2_periph_clk_reset,
996 /* Clock doubler ops */
997 static void tegra2_clk_double_init(struct clk *c)
1002 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
1003 PERIPH_CLK_TO_ENB_BIT(c)))
1007 static int tegra2_clk_double_set_rate(struct clk *c, unsigned long rate)
1009 if (rate != 2 * c->parent->rate)
1016 static struct clk_ops tegra_clk_double_ops = {
1017 .init = &tegra2_clk_double_init,
1018 .enable = &tegra2_periph_clk_enable,
1019 .disable = &tegra2_periph_clk_disable,
1020 .set_rate = &tegra2_clk_double_set_rate,
1023 /* Audio sync clock ops */
1024 static void tegra2_audio_sync_clk_init(struct clk *c)
1027 const struct clk_mux_sel *sel;
1028 u32 val = clk_readl(c->reg);
1029 c->state = (val & (1<<4)) ? OFF : ON;
1031 for (sel = c->inputs; sel->input != NULL; sel++)
1032 if (sel->value == source)
1034 BUG_ON(sel->input == NULL);
1035 c->parent = sel->input;
1038 static int tegra2_audio_sync_clk_enable(struct clk *c)
1040 clk_writel(0, c->reg);
1044 static void tegra2_audio_sync_clk_disable(struct clk *c)
1046 clk_writel(1, c->reg);
1049 static int tegra2_audio_sync_clk_set_parent(struct clk *c, struct clk *p)
1052 const struct clk_mux_sel *sel;
1053 for (sel = c->inputs; sel->input != NULL; sel++) {
1054 if (sel->input == p) {
1055 val = clk_readl(c->reg);
1060 clk_enable_locked(p);
1062 clk_writel(val, c->reg);
1064 if (c->refcnt && c->parent)
1065 clk_disable_locked(c->parent);
1075 static int tegra2_audio_sync_clk_set_rate(struct clk *c, unsigned long rate)
1077 unsigned long parent_rate;
1079 pr_err("%s: clock has no parent\n", __func__);
1082 parent_rate = c->parent->rate;
1083 if (rate != parent_rate) {
1084 pr_err("%s: %s/%ld differs from parent %s/%ld\n",
1087 c->parent->name, parent_rate);
1090 c->rate = parent_rate;
1094 static struct clk_ops tegra_audio_sync_clk_ops = {
1095 .init = tegra2_audio_sync_clk_init,
1096 .enable = tegra2_audio_sync_clk_enable,
1097 .disable = tegra2_audio_sync_clk_disable,
1098 .set_rate = tegra2_audio_sync_clk_set_rate,
1099 .set_parent = tegra2_audio_sync_clk_set_parent,
1102 /* cdev1 and cdev2 (dap_mclk1 and dap_mclk2) ops */
1104 static void tegra2_cdev_clk_init(struct clk *c)
1106 /* We could un-tristate the cdev1 or cdev2 pingroup here; this is
1107 * currently done in the pinmux code. */
1109 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
1110 PERIPH_CLK_TO_ENB_BIT(c)))
1114 static int tegra2_cdev_clk_enable(struct clk *c)
1116 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1117 CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
1121 static void tegra2_cdev_clk_disable(struct clk *c)
1123 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1124 CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
1127 static struct clk_ops tegra_cdev_clk_ops = {
1128 .init = &tegra2_cdev_clk_init,
1129 .enable = &tegra2_cdev_clk_enable,
1130 .disable = &tegra2_cdev_clk_disable,
1133 /* Clock definitions */
1134 static struct clk tegra_clk_32k = {
1141 static struct clk_pll_table tegra_pll_s_table[] = {
1142 {32768, 12000000, 366, 1, 1, 0},
1143 {32768, 13000000, 397, 1, 1, 0},
1144 {32768, 19200000, 586, 1, 1, 0},
1145 {32768, 26000000, 793, 1, 1, 0},
1149 static struct clk tegra_pll_s = {
1151 .flags = PLL_ALT_MISC_REG,
1152 .ops = &tegra_pll_ops,
1156 .parent = &tegra_clk_32k,
1157 .cf_min = 0, /* FIXME */
1158 .cf_max = 0, /* FIXME */
1159 .vco_min = 12000000,
1160 .vco_max = 26000000,
1161 .pll_table = tegra_pll_s_table,
1162 .max_rate = 26000000,
1163 .pll_lock_delay = 300,
1166 static struct clk_mux_sel tegra_clk_m_sel[] = {
1167 { .input = &tegra_clk_32k, .value = 0},
1168 { .input = &tegra_pll_s, .value = 1},
1171 static struct clk tegra_clk_m = {
1173 .flags = ENABLE_ON_INIT,
1174 .ops = &tegra_clk_m_ops,
1175 .inputs = tegra_clk_m_sel,
1177 .reg_mask = (1<<28),
1179 .max_rate = 26000000,
1182 static struct clk_pll_table tegra_pll_c_table[] = {
1183 { 0, 0, 0, 0, 0, 0 },
1186 static struct clk tegra_pll_c = {
1188 .flags = PLL_HAS_CPCON,
1189 .ops = &tegra_pll_ops,
1191 .input_min = 2000000,
1192 .input_max = 31000000,
1193 .parent = &tegra_clk_m,
1196 .vco_min = 20000000,
1197 .vco_max = 1400000000,
1198 .pll_table = tegra_pll_c_table,
1199 .max_rate = 600000000,
1200 .pll_lock_delay = 300,
1203 static struct clk tegra_pll_c_out1 = {
1204 .name = "pll_c_out1",
1205 .ops = &tegra_pll_div_ops,
1207 .parent = &tegra_pll_c,
1210 .max_rate = 600000000,
1213 static struct clk_pll_table tegra_pll_m_table[] = {
1214 { 12000000, 666000000, 666, 12, 1, 8},
1215 { 13000000, 666000000, 666, 13, 1, 8},
1216 { 19200000, 666000000, 555, 16, 1, 8},
1217 { 26000000, 666000000, 666, 26, 1, 8},
1218 { 12000000, 600000000, 600, 12, 1, 8},
1219 { 13000000, 600000000, 600, 13, 1, 8},
1220 { 19200000, 600000000, 375, 12, 1, 6},
1221 { 26000000, 600000000, 600, 26, 1, 8},
1222 { 0, 0, 0, 0, 0, 0 },
1225 static struct clk tegra_pll_m = {
1227 .flags = PLL_HAS_CPCON,
1228 .ops = &tegra_pll_ops,
1230 .input_min = 2000000,
1231 .input_max = 31000000,
1232 .parent = &tegra_clk_m,
1235 .vco_min = 20000000,
1236 .vco_max = 1200000000,
1237 .pll_table = tegra_pll_m_table,
1238 .max_rate = 800000000,
1239 .pll_lock_delay = 300,
1242 static struct clk tegra_pll_m_out1 = {
1243 .name = "pll_m_out1",
1244 .ops = &tegra_pll_div_ops,
1246 .parent = &tegra_pll_m,
1249 .max_rate = 600000000,
1252 static struct clk_pll_table tegra_pll_p_table[] = {
1253 { 12000000, 216000000, 432, 12, 2, 8},
1254 { 13000000, 216000000, 432, 13, 2, 8},
1255 { 19200000, 216000000, 90, 4, 2, 1},
1256 { 26000000, 216000000, 432, 26, 2, 8},
1257 { 12000000, 432000000, 432, 12, 1, 8},
1258 { 13000000, 432000000, 432, 13, 1, 8},
1259 { 19200000, 432000000, 90, 4, 1, 1},
1260 { 26000000, 432000000, 432, 26, 1, 8},
1261 { 0, 0, 0, 0, 0, 0 },
1264 static struct clk tegra_pll_p = {
1266 .flags = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON,
1267 .ops = &tegra_pll_ops,
1269 .input_min = 2000000,
1270 .input_max = 31000000,
1271 .parent = &tegra_clk_m,
1274 .vco_min = 20000000,
1275 .vco_max = 1400000000,
1276 .pll_table = tegra_pll_p_table,
1277 .max_rate = 432000000,
1278 .pll_lock_delay = 300,
1281 static struct clk tegra_pll_p_out1 = {
1282 .name = "pll_p_out1",
1283 .ops = &tegra_pll_div_ops,
1284 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1285 .parent = &tegra_pll_p,
1288 .max_rate = 432000000,
1291 static struct clk tegra_pll_p_out2 = {
1292 .name = "pll_p_out2",
1293 .ops = &tegra_pll_div_ops,
1294 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1295 .parent = &tegra_pll_p,
1298 .max_rate = 432000000,
1301 static struct clk tegra_pll_p_out3 = {
1302 .name = "pll_p_out3",
1303 .ops = &tegra_pll_div_ops,
1304 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1305 .parent = &tegra_pll_p,
1308 .max_rate = 432000000,
1311 static struct clk tegra_pll_p_out4 = {
1312 .name = "pll_p_out4",
1313 .ops = &tegra_pll_div_ops,
1314 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1315 .parent = &tegra_pll_p,
1318 .max_rate = 432000000,
1321 static struct clk_pll_table tegra_pll_a_table[] = {
1322 { 28800000, 56448000, 49, 25, 1, 1},
1323 { 28800000, 73728000, 64, 25, 1, 1},
1324 { 28800000, 11289600, 49, 25, 1, 1},
1325 { 28800000, 12288000, 64, 25, 1, 1},
1326 { 28800000, 24000000, 5, 6, 1, 1},
1327 { 0, 0, 0, 0, 0, 0 },
1330 static struct clk tegra_pll_a = {
1332 .flags = PLL_HAS_CPCON,
1333 .ops = &tegra_pll_ops,
1335 .input_min = 2000000,
1336 .input_max = 31000000,
1337 .parent = &tegra_pll_p_out1,
1340 .vco_min = 20000000,
1341 .vco_max = 1400000000,
1342 .pll_table = tegra_pll_a_table,
1343 .max_rate = 56448000,
1344 .pll_lock_delay = 300,
1347 static struct clk tegra_pll_a_out0 = {
1348 .name = "pll_a_out0",
1349 .ops = &tegra_pll_div_ops,
1351 .parent = &tegra_pll_a,
1354 .max_rate = 56448000,
1357 static struct clk_pll_table tegra_pll_d_table[] = {
1358 { 12000000, 216000000, 216, 12, 1, 4},
1359 { 13000000, 216000000, 216, 13, 1, 4},
1360 { 19200000, 216000000, 135, 12, 1, 3},
1361 { 26000000, 216000000, 216, 26, 1, 4},
1363 { 12000000, 594000000, 594, 12, 1, 8},
1364 { 13000000, 594000000, 594, 13, 1, 8},
1365 { 19200000, 594000000, 495, 16, 1, 8},
1366 { 26000000, 594000000, 594, 26, 1, 8},
1368 { 12000000, 1000000000, 1000, 12, 1, 12},
1369 { 13000000, 1000000000, 1000, 13, 1, 12},
1370 { 19200000, 1000000000, 625, 12, 1, 8},
1371 { 26000000, 1000000000, 1000, 26, 1, 12},
1373 { 0, 0, 0, 0, 0, 0 },
1376 static struct clk tegra_pll_d = {
1378 .flags = PLL_HAS_CPCON | PLLD,
1379 .ops = &tegra_pll_ops,
1381 .input_min = 2000000,
1382 .input_max = 40000000,
1383 .parent = &tegra_clk_m,
1386 .vco_min = 40000000,
1387 .vco_max = 1000000000,
1388 .pll_table = tegra_pll_d_table,
1389 .max_rate = 1000000000,
1390 .pll_lock_delay = 1000,
1393 static struct clk tegra_pll_d_out0 = {
1394 .name = "pll_d_out0",
1395 .ops = &tegra_pll_div_ops,
1396 .flags = DIV_2 | PLLD,
1397 .parent = &tegra_pll_d,
1398 .max_rate = 500000000,
1401 static struct clk_pll_table tegra_pll_u_table[] = {
1402 { 12000000, 480000000, 960, 12, 2, 0},
1403 { 13000000, 480000000, 960, 13, 2, 0},
1404 { 19200000, 480000000, 200, 4, 2, 0},
1405 { 26000000, 480000000, 960, 26, 2, 0},
1406 { 0, 0, 0, 0, 0, 0 },
1409 static struct clk tegra_pll_u = {
1412 .ops = &tegra_pll_ops,
1414 .input_min = 2000000,
1415 .input_max = 40000000,
1416 .parent = &tegra_clk_m,
1419 .vco_min = 480000000,
1420 .vco_max = 960000000,
1421 .pll_table = tegra_pll_u_table,
1422 .max_rate = 480000000,
1423 .pll_lock_delay = 1000,
1426 static struct clk_pll_table tegra_pll_x_table[] = {
1428 { 12000000, 1000000000, 1000, 12, 1, 12},
1429 { 13000000, 1000000000, 1000, 13, 1, 12},
1430 { 19200000, 1000000000, 625, 12, 1, 8},
1431 { 26000000, 1000000000, 1000, 26, 1, 12},
1434 { 12000000, 912000000, 912, 12, 1, 12},
1435 { 13000000, 912000000, 912, 13, 1, 12},
1436 { 19200000, 912000000, 760, 16, 1, 8},
1437 { 26000000, 912000000, 912, 26, 1, 12},
1440 { 12000000, 816000000, 816, 12, 1, 12},
1441 { 13000000, 816000000, 816, 13, 1, 12},
1442 { 19200000, 816000000, 680, 16, 1, 8},
1443 { 26000000, 816000000, 816, 26, 1, 12},
1446 { 12000000, 760000000, 760, 12, 1, 12},
1447 { 13000000, 760000000, 760, 13, 1, 12},
1448 { 19200000, 760000000, 950, 24, 1, 8},
1449 { 26000000, 760000000, 760, 26, 1, 12},
1452 { 12000000, 608000000, 760, 12, 1, 12},
1453 { 13000000, 608000000, 760, 13, 1, 12},
1454 { 19200000, 608000000, 380, 12, 1, 8},
1455 { 26000000, 608000000, 760, 26, 1, 12},
1458 { 12000000, 456000000, 456, 12, 1, 12},
1459 { 13000000, 456000000, 456, 13, 1, 12},
1460 { 19200000, 456000000, 380, 16, 1, 8},
1461 { 26000000, 456000000, 456, 26, 1, 12},
1464 { 12000000, 312000000, 312, 12, 1, 12},
1465 { 13000000, 312000000, 312, 13, 1, 12},
1466 { 19200000, 312000000, 260, 16, 1, 8},
1467 { 26000000, 312000000, 312, 26, 1, 12},
1469 { 0, 0, 0, 0, 0, 0 },
1472 static struct clk tegra_pll_x = {
1474 .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG,
1475 .ops = &tegra_pllx_ops,
1477 .input_min = 2000000,
1478 .input_max = 31000000,
1479 .parent = &tegra_clk_m,
1482 .vco_min = 20000000,
1483 .vco_max = 1200000000,
1484 .pll_table = tegra_pll_x_table,
1485 .max_rate = 1000000000,
1486 .pll_lock_delay = 300,
1489 static struct clk_pll_table tegra_pll_e_table[] = {
1490 { 12000000, 100000000, 200, 24, 1, 0 },
1491 { 0, 0, 0, 0, 0, 0 },
1494 static struct clk tegra_pll_e = {
1496 .flags = PLL_ALT_MISC_REG,
1497 .ops = &tegra_plle_ops,
1498 .input_min = 12000000,
1499 .input_max = 12000000,
1500 .max_rate = 100000000,
1501 .parent = &tegra_clk_m,
1503 .pll_table = tegra_pll_e_table,
1506 static struct clk tegra_clk_d = {
1508 .flags = PERIPH_NO_RESET,
1509 .ops = &tegra_clk_double_ops,
1513 .parent = &tegra_clk_m,
1514 .max_rate = 52000000,
1517 /* dap_mclk1, belongs to the cdev1 pingroup. */
1518 static struct clk tegra_dev1_clk = {
1520 .ops = &tegra_cdev_clk_ops,
1523 .max_rate = 26000000,
1526 /* dap_mclk2, belongs to the cdev2 pingroup. */
1527 static struct clk tegra_dev2_clk = {
1529 .ops = &tegra_cdev_clk_ops,
1532 .max_rate = 26000000,
1535 /* initialized before peripheral clocks */
1536 static struct clk_mux_sel mux_audio_sync_clk[8+1];
1537 static const struct audio_sources {
1540 } mux_audio_sync_clk_sources[] = {
1541 { .name = "spdif_in", .value = 0 },
1542 { .name = "i2s1", .value = 1 },
1543 { .name = "i2s2", .value = 2 },
1544 { .name = "pll_a_out0", .value = 4 },
1545 #if 0 /* FIXME: not implemented */
1546 { .name = "ac97", .value = 3 },
1547 { .name = "ext_audio_clk2", .value = 5 },
1548 { .name = "ext_audio_clk1", .value = 6 },
1549 { .name = "ext_vimclk", .value = 7 },
1554 static struct clk tegra_clk_audio = {
1556 .inputs = mux_audio_sync_clk,
1558 .max_rate = 24000000,
1559 .ops = &tegra_audio_sync_clk_ops
1562 static struct clk tegra_clk_audio_2x = {
1564 .flags = PERIPH_NO_RESET,
1565 .max_rate = 48000000,
1566 .ops = &tegra_clk_double_ops,
1570 .parent = &tegra_clk_audio,
1573 struct clk_lookup tegra_audio_clk_lookups[] = {
1574 { .con_id = "audio", .clk = &tegra_clk_audio },
1575 { .con_id = "audio_2x", .clk = &tegra_clk_audio_2x }
1578 /* This is called after peripheral clocks are initialized, as the
1579 * audio_sync clock depends on some of the peripheral clocks.
1582 static void init_audio_sync_clock_mux(void)
1585 struct clk_mux_sel *sel = mux_audio_sync_clk;
1586 const struct audio_sources *src = mux_audio_sync_clk_sources;
1587 struct clk_lookup *lookup;
1589 for (i = 0; src->name; i++, sel++, src++) {
1590 sel->input = tegra_get_clock_by_name(src->name);
1592 pr_err("%s: could not find clk %s\n", __func__,
1594 sel->value = src->value;
1597 lookup = tegra_audio_clk_lookups;
1598 for (i = 0; i < ARRAY_SIZE(tegra_audio_clk_lookups); i++, lookup++) {
1599 clk_init(lookup->clk);
1604 static struct clk_mux_sel mux_cclk[] = {
1605 { .input = &tegra_clk_m, .value = 0},
1606 { .input = &tegra_pll_c, .value = 1},
1607 { .input = &tegra_clk_32k, .value = 2},
1608 { .input = &tegra_pll_m, .value = 3},
1609 { .input = &tegra_pll_p, .value = 4},
1610 { .input = &tegra_pll_p_out4, .value = 5},
1611 { .input = &tegra_pll_p_out3, .value = 6},
1612 { .input = &tegra_clk_d, .value = 7},
1613 { .input = &tegra_pll_x, .value = 8},
1617 static struct clk_mux_sel mux_sclk[] = {
1618 { .input = &tegra_clk_m, .value = 0},
1619 { .input = &tegra_pll_c_out1, .value = 1},
1620 { .input = &tegra_pll_p_out4, .value = 2},
1621 { .input = &tegra_pll_p_out3, .value = 3},
1622 { .input = &tegra_pll_p_out2, .value = 4},
1623 { .input = &tegra_clk_d, .value = 5},
1624 { .input = &tegra_clk_32k, .value = 6},
1625 { .input = &tegra_pll_m_out1, .value = 7},
1629 static struct clk tegra_clk_cclk = {
1633 .ops = &tegra_super_ops,
1634 .max_rate = 1000000000,
1637 static struct clk tegra_clk_sclk = {
1641 .ops = &tegra_super_ops,
1642 .max_rate = 600000000,
1645 static struct clk tegra_clk_virtual_cpu = {
1647 .parent = &tegra_clk_cclk,
1648 .main = &tegra_pll_x,
1649 .backup = &tegra_pll_p,
1650 .ops = &tegra_cpu_ops,
1651 .max_rate = 1000000000,
1654 static struct clk tegra_clk_hclk = {
1657 .parent = &tegra_clk_sclk,
1660 .ops = &tegra_bus_ops,
1661 .max_rate = 240000000,
1664 static struct clk tegra_clk_pclk = {
1667 .parent = &tegra_clk_hclk,
1670 .ops = &tegra_bus_ops,
1671 .max_rate = 108000000,
1674 static struct clk tegra_clk_blink = {
1676 .parent = &tegra_clk_32k,
1678 .ops = &tegra_blink_clk_ops,
1682 static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
1683 { .input = &tegra_pll_m, .value = 0},
1684 { .input = &tegra_pll_c, .value = 1},
1685 { .input = &tegra_pll_p, .value = 2},
1686 { .input = &tegra_pll_a_out0, .value = 3},
1690 static struct clk_mux_sel mux_pllm_pllc_pllp_clkm[] = {
1691 { .input = &tegra_pll_m, .value = 0},
1692 { .input = &tegra_pll_c, .value = 1},
1693 { .input = &tegra_pll_p, .value = 2},
1694 { .input = &tegra_clk_m, .value = 3},
1698 static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
1699 { .input = &tegra_pll_p, .value = 0},
1700 { .input = &tegra_pll_c, .value = 1},
1701 { .input = &tegra_pll_m, .value = 2},
1702 { .input = &tegra_clk_m, .value = 3},
1706 static struct clk_mux_sel mux_pllaout0_audio2x_pllp_clkm[] = {
1707 {.input = &tegra_pll_a_out0, .value = 0},
1708 {.input = &tegra_clk_audio_2x, .value = 1},
1709 {.input = &tegra_pll_p, .value = 2},
1710 {.input = &tegra_clk_m, .value = 3},
1714 static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = {
1715 {.input = &tegra_pll_p, .value = 0},
1716 {.input = &tegra_pll_d_out0, .value = 1},
1717 {.input = &tegra_pll_c, .value = 2},
1718 {.input = &tegra_clk_m, .value = 3},
1722 static struct clk_mux_sel mux_pllp_pllc_audio_clkm_clk32[] = {
1723 {.input = &tegra_pll_p, .value = 0},
1724 {.input = &tegra_pll_c, .value = 1},
1725 {.input = &tegra_clk_audio, .value = 2},
1726 {.input = &tegra_clk_m, .value = 3},
1727 {.input = &tegra_clk_32k, .value = 4},
1731 static struct clk_mux_sel mux_pllp_pllc_pllm[] = {
1732 {.input = &tegra_pll_p, .value = 0},
1733 {.input = &tegra_pll_c, .value = 1},
1734 {.input = &tegra_pll_m, .value = 2},
1738 static struct clk_mux_sel mux_clk_m[] = {
1739 { .input = &tegra_clk_m, .value = 0},
1743 static struct clk_mux_sel mux_pllp_out3[] = {
1744 { .input = &tegra_pll_p_out3, .value = 0},
1748 static struct clk_mux_sel mux_plld[] = {
1749 { .input = &tegra_pll_d, .value = 0},
1753 static struct clk_mux_sel mux_clk_32k[] = {
1754 { .input = &tegra_clk_32k, .value = 0},
1758 static struct clk_mux_sel mux_pclk[] = {
1759 { .input = &tegra_clk_pclk, .value = 0},
1763 #define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
1770 .ops = &tegra_periph_clk_ops, \
1771 .clk_num = _clk_num, \
1773 .inputs = _inputs, \
1778 struct clk tegra_list_clks[] = {
1779 PERIPH_CLK("apbdma", "tegra-dma", NULL, 34, 0, 108000000, mux_pclk, 0),
1780 PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET),
1781 PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0),
1782 PERIPH_CLK("i2s1", "i2s.0", NULL, 11, 0x100, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
1783 PERIPH_CLK("i2s2", "i2s.1", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
1784 /* FIXME: spdif has 2 clocks but 1 enable */
1785 PERIPH_CLK("spdif_out", "spdif_out", NULL, 10, 0x108, 100000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
1786 PERIPH_CLK("spdif_in", "spdif_in", NULL, 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71),
1787 PERIPH_CLK("pwm", "pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_audio_clkm_clk32, MUX | DIV_U71),
1788 PERIPH_CLK("spi", "spi", NULL, 43, 0x114, 40000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1789 PERIPH_CLK("xio", "xio", NULL, 45, 0x120, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1790 PERIPH_CLK("twc", "twc", NULL, 16, 0x12c, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1791 PERIPH_CLK("sbc1", "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1792 PERIPH_CLK("sbc2", "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1793 PERIPH_CLK("sbc3", "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1794 PERIPH_CLK("sbc4", "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1795 PERIPH_CLK("ide", "ide", NULL, 25, 0x144, 100000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */
1796 PERIPH_CLK("ndflash", "tegra_nand", NULL, 13, 0x160, 164000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
1797 /* FIXME: vfir shares an enable with uartb */
1798 PERIPH_CLK("vfir", "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1799 PERIPH_CLK("sdmmc1", "sdhci-tegra.0", NULL, 14, 0x150, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
1800 PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
1801 PERIPH_CLK("sdmmc3", "sdhci-tegra.2", NULL, 69, 0x1bc, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
1802 PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x164, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
1803 PERIPH_CLK("vde", "vde", NULL, 61, 0x1c8, 250000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage and process_id */
1804 PERIPH_CLK("csite", "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* max rate ??? */
1805 /* FIXME: what is la? */
1806 PERIPH_CLK("la", "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1807 PERIPH_CLK("owr", "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1808 PERIPH_CLK("nor", "nor", NULL, 42, 0x1d0, 92000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */
1809 PERIPH_CLK("mipi", "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
1810 PERIPH_CLK("i2c1", "tegra-i2c.0", NULL, 12, 0x124, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
1811 PERIPH_CLK("i2c2", "tegra-i2c.1", NULL, 54, 0x198, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
1812 PERIPH_CLK("i2c3", "tegra-i2c.2", NULL, 67, 0x1b8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
1813 PERIPH_CLK("dvc", "tegra-i2c.3", NULL, 47, 0x128, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
1814 PERIPH_CLK("i2c1_i2c", "tegra-i2c.0", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
1815 PERIPH_CLK("i2c2_i2c", "tegra-i2c.1", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
1816 PERIPH_CLK("i2c3_i2c", "tegra-i2c.2", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
1817 PERIPH_CLK("dvc_i2c", "tegra-i2c.3", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
1818 PERIPH_CLK("uarta", "uart.0", NULL, 6, 0x178, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
1819 PERIPH_CLK("uartb", "uart.1", NULL, 7, 0x17c, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
1820 PERIPH_CLK("uartc", "uart.2", NULL, 55, 0x1a0, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
1821 PERIPH_CLK("uartd", "uart.3", NULL, 65, 0x1c0, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
1822 PERIPH_CLK("uarte", "uart.4", NULL, 66, 0x1c4, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
1823 PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_MANUAL_RESET), /* scales with voltage and process_id */
1824 PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
1825 /* FIXME: vi and vi_sensor share an enable */
1826 PERIPH_CLK("vi", "tegra_camera", "vi", 20, 0x148, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
1827 PERIPH_CLK("vi_sensor", "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET), /* scales with voltage and process_id */
1828 PERIPH_CLK("epp", "epp", NULL, 19, 0x16c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
1829 PERIPH_CLK("mpe", "mpe", NULL, 60, 0x170, 250000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
1830 PERIPH_CLK("host1x", "host1x", NULL, 28, 0x180, 166000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
1831 /* FIXME: cve and tvo share an enable */
1832 PERIPH_CLK("cve", "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
1833 PERIPH_CLK("tvo", "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
1834 PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, 600000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
1835 PERIPH_CLK("tvdac", "tvdac", NULL, 53, 0x194, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
1836 PERIPH_CLK("disp1", "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* scales with voltage and process_id */
1837 PERIPH_CLK("disp2", "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* scales with voltage and process_id */
1838 PERIPH_CLK("usbd", "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
1839 PERIPH_CLK("usb2", "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
1840 PERIPH_CLK("usb3", "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
1841 PERIPH_CLK("emc", "emc", NULL, 57, 0x19c, 800000000, mux_pllm_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_EMC_ENB),
1842 PERIPH_CLK("dsi", "dsi", NULL, 48, 0, 500000000, mux_plld, 0), /* scales with voltage */
1843 PERIPH_CLK("csi", "tegra_camera", "csi", 52, 0, 72000000, mux_pllp_out3, 0),
1844 PERIPH_CLK("isp", "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0), /* same frequency as VI */
1845 PERIPH_CLK("csus", "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET),
1846 PERIPH_CLK("pex", NULL, "pex", 70, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET),
1847 PERIPH_CLK("afi", NULL, "afi", 72, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET),
1848 PERIPH_CLK("pcie_xclk", NULL, "pcie_xclk", 74, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET),
1851 #define CLK_DUPLICATE(_name, _dev, _con) \
1860 /* Some clocks may be used by different drivers depending on the board
1861 * configuration. List those here to register them twice in the clock lookup
1862 * table under two names.
1864 struct clk_duplicate tegra_clk_duplicates[] = {
1865 CLK_DUPLICATE("uarta", "tegra_uart.0", NULL),
1866 CLK_DUPLICATE("uartb", "tegra_uart.1", NULL),
1867 CLK_DUPLICATE("uartc", "tegra_uart.2", NULL),
1868 CLK_DUPLICATE("uartd", "tegra_uart.3", NULL),
1869 CLK_DUPLICATE("uarte", "tegra_uart.4", NULL),
1870 CLK_DUPLICATE("usbd", "utmip-pad", NULL),
1871 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
1872 CLK_DUPLICATE("usbd", "tegra-otg", NULL),
1873 CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
1874 CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
1875 CLK_DUPLICATE("pwm", "tegra_pwm.0", NULL),
1876 CLK_DUPLICATE("pwm", "tegra_pwm.1", NULL),
1877 CLK_DUPLICATE("pwm", "tegra_pwm.2", NULL),
1878 CLK_DUPLICATE("pwm", "tegra_pwm.3", NULL),
1881 #define CLK(dev, con, ck) \
1888 struct clk *tegra_ptr_clks[] = {
1915 &tegra_clk_virtual_cpu,
1919 static void tegra2_init_one_clock(struct clk *c)
1922 if (!c->lookup.dev_id && !c->lookup.con_id)
1923 c->lookup.con_id = c->name;
1925 clkdev_add(&c->lookup);
1928 void __init tegra2_init_clocks(void)
1933 for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
1934 tegra2_init_one_clock(tegra_ptr_clks[i]);
1936 for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
1937 tegra2_init_one_clock(&tegra_list_clks[i]);
1939 for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
1940 c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
1942 pr_err("%s: Unknown duplicate clock %s\n", __func__,
1943 tegra_clk_duplicates[i].name);
1947 tegra_clk_duplicates[i].lookup.clk = c;
1948 clkdev_add(&tegra_clk_duplicates[i].lookup);
1951 init_audio_sync_clock_mux();
1955 static u32 clk_rst_suspend[RST_DEVICES_NUM + CLK_OUT_ENB_NUM +
1956 PERIPH_CLK_SOURCE_NUM + 19];
1958 void tegra_clk_suspend(void)
1960 unsigned long off, i;
1961 u32 *ctx = clk_rst_suspend;
1963 *ctx++ = clk_readl(OSC_CTRL) & OSC_CTRL_MASK;
1964 *ctx++ = clk_readl(tegra_pll_p.reg + PLL_BASE);
1965 *ctx++ = clk_readl(tegra_pll_p.reg + PLL_MISC(&tegra_pll_p));
1966 *ctx++ = clk_readl(tegra_pll_c.reg + PLL_BASE);
1967 *ctx++ = clk_readl(tegra_pll_c.reg + PLL_MISC(&tegra_pll_c));
1968 *ctx++ = clk_readl(tegra_pll_a.reg + PLL_BASE);
1969 *ctx++ = clk_readl(tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
1971 *ctx++ = clk_readl(tegra_pll_m_out1.reg);
1972 *ctx++ = clk_readl(tegra_pll_p_out1.reg);
1973 *ctx++ = clk_readl(tegra_pll_p_out3.reg);
1974 *ctx++ = clk_readl(tegra_pll_a_out0.reg);
1975 *ctx++ = clk_readl(tegra_pll_c_out1.reg);
1977 *ctx++ = clk_readl(tegra_clk_cclk.reg);
1978 *ctx++ = clk_readl(tegra_clk_cclk.reg + SUPER_CLK_DIVIDER);
1980 *ctx++ = clk_readl(tegra_clk_sclk.reg);
1981 *ctx++ = clk_readl(tegra_clk_sclk.reg + SUPER_CLK_DIVIDER);
1982 *ctx++ = clk_readl(tegra_clk_pclk.reg);
1984 for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC;
1986 if (off == PERIPH_CLK_SOURCE_EMC)
1988 *ctx++ = clk_readl(off);
1992 for (i = 0; i < RST_DEVICES_NUM; i++, off += 4)
1993 *ctx++ = clk_readl(off);
1996 for (i = 0; i < CLK_OUT_ENB_NUM; i++, off += 4)
1997 *ctx++ = clk_readl(off);
1999 *ctx++ = clk_readl(MISC_CLK_ENB);
2000 *ctx++ = clk_readl(CLK_MASK_ARM);
2003 void tegra_clk_resume(void)
2005 unsigned long off, i;
2006 const u32 *ctx = clk_rst_suspend;
2009 val = clk_readl(OSC_CTRL) & ~OSC_CTRL_MASK;
2011 clk_writel(val, OSC_CTRL);
2013 clk_writel(*ctx++, tegra_pll_p.reg + PLL_BASE);
2014 clk_writel(*ctx++, tegra_pll_p.reg + PLL_MISC(&tegra_pll_p));
2015 clk_writel(*ctx++, tegra_pll_c.reg + PLL_BASE);
2016 clk_writel(*ctx++, tegra_pll_c.reg + PLL_MISC(&tegra_pll_c));
2017 clk_writel(*ctx++, tegra_pll_a.reg + PLL_BASE);
2018 clk_writel(*ctx++, tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
2021 clk_writel(*ctx++, tegra_pll_m_out1.reg);
2022 clk_writel(*ctx++, tegra_pll_p_out1.reg);
2023 clk_writel(*ctx++, tegra_pll_p_out3.reg);
2024 clk_writel(*ctx++, tegra_pll_a_out0.reg);
2025 clk_writel(*ctx++, tegra_pll_c_out1.reg);
2027 clk_writel(*ctx++, tegra_clk_cclk.reg);
2028 clk_writel(*ctx++, tegra_clk_cclk.reg + SUPER_CLK_DIVIDER);
2030 clk_writel(*ctx++, tegra_clk_sclk.reg);
2031 clk_writel(*ctx++, tegra_clk_sclk.reg + SUPER_CLK_DIVIDER);
2032 clk_writel(*ctx++, tegra_clk_pclk.reg);
2034 /* enable all clocks before configuring clock sources */
2035 clk_writel(0xbffffff9ul, CLK_OUT_ENB);
2036 clk_writel(0xfefffff7ul, CLK_OUT_ENB + 4);
2037 clk_writel(0x77f01bfful, CLK_OUT_ENB + 8);
2040 for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC;
2042 if (off == PERIPH_CLK_SOURCE_EMC)
2044 clk_writel(*ctx++, off);
2049 for (i = 0; i < RST_DEVICES_NUM; i++, off += 4)
2050 clk_writel(*ctx++, off);
2054 for (i = 0; i < CLK_OUT_ENB_NUM; i++, off += 4)
2055 clk_writel(*ctx++, off);
2058 clk_writel(*ctx++, MISC_CLK_ENB);
2059 clk_writel(*ctx++, CLK_MASK_ARM);