2 * Lowlevel clock handling for Telechips TCC8xxx SoCs
4 * Copyright (C) 2010 by Hans J. Koch <hjk@linutronix.de>
6 * Licensed under the terms of the GPL v2
10 #include <linux/delay.h>
11 #include <linux/err.h>
13 #include <linux/module.h>
14 #include <linux/spinlock.h>
16 #include <asm/clkdev.h>
18 #include <mach/clock.h>
19 #include <mach/irqs.h>
20 #include <mach/tcc8k-regs.h>
24 #define BCLKCTR0 (CKC_BASE + BCLKCTR0_OFFS)
25 #define BCLKCTR1 (CKC_BASE + BCLKCTR1_OFFS)
27 #define ACLKREF (CKC_BASE + ACLKREF_OFFS)
28 #define ACLKUART0 (CKC_BASE + ACLKUART0_OFFS)
29 #define ACLKUART1 (CKC_BASE + ACLKUART1_OFFS)
30 #define ACLKUART2 (CKC_BASE + ACLKUART2_OFFS)
31 #define ACLKUART3 (CKC_BASE + ACLKUART3_OFFS)
32 #define ACLKUART4 (CKC_BASE + ACLKUART4_OFFS)
33 #define ACLKI2C (CKC_BASE + ACLKI2C_OFFS)
34 #define ACLKADC (CKC_BASE + ACLKADC_OFFS)
35 #define ACLKUSBH (CKC_BASE + ACLKUSBH_OFFS)
36 #define ACLKLCD (CKC_BASE + ACLKLCD_OFFS)
37 #define ACLKSDH0 (CKC_BASE + ACLKSDH0_OFFS)
38 #define ACLKSDH1 (CKC_BASE + ACLKSDH1_OFFS)
39 #define ACLKSPI0 (CKC_BASE + ACLKSPI0_OFFS)
40 #define ACLKSPI1 (CKC_BASE + ACLKSPI1_OFFS)
41 #define ACLKSPDIF (CKC_BASE + ACLKSPDIF_OFFS)
42 #define ACLKC3DEC (CKC_BASE + ACLKC3DEC_OFFS)
43 #define ACLKCAN0 (CKC_BASE + ACLKCAN0_OFFS)
44 #define ACLKCAN1 (CKC_BASE + ACLKCAN1_OFFS)
45 #define ACLKGSB0 (CKC_BASE + ACLKGSB0_OFFS)
46 #define ACLKGSB1 (CKC_BASE + ACLKGSB1_OFFS)
47 #define ACLKGSB2 (CKC_BASE + ACLKGSB2_OFFS)
48 #define ACLKGSB3 (CKC_BASE + ACLKGSB3_OFFS)
49 #define ACLKUSBH (CKC_BASE + ACLKUSBH_OFFS)
50 #define ACLKTCT (CKC_BASE + ACLKTCT_OFFS)
51 #define ACLKTCX (CKC_BASE + ACLKTCX_OFFS)
52 #define ACLKTCZ (CKC_BASE + ACLKTCZ_OFFS)
54 /* Crystal frequencies */
55 static unsigned long xi_rate, xti_rate;
57 static void __iomem *pll_cfg_addr(int pll)
60 case 0: return (CKC_BASE + PLL0CFG_OFFS);
61 case 1: return (CKC_BASE + PLL1CFG_OFFS);
62 case 2: return (CKC_BASE + PLL2CFG_OFFS);
68 static int pll_enable(int pll, int enable)
71 void __iomem *addr = pll_cfg_addr(pll);
73 reg = __raw_readl(addr);
79 __raw_writel(reg, addr);
83 static int xi_enable(int enable)
87 reg = __raw_readl(CKC_BASE + CLKCTRL_OFFS);
93 __raw_writel(reg, CKC_BASE + CLKCTRL_OFFS);
97 static int root_clk_enable(enum root_clks src)
100 case CLK_SRC_PLL0: return pll_enable(0, 1);
101 case CLK_SRC_PLL1: return pll_enable(1, 1);
102 case CLK_SRC_PLL2: return pll_enable(2, 1);
103 case CLK_SRC_XI: return xi_enable(1);
110 static int root_clk_disable(enum root_clks root_src)
113 case CLK_SRC_PLL0: return pll_enable(0, 0);
114 case CLK_SRC_PLL1: return pll_enable(1, 0);
115 case CLK_SRC_PLL2: return pll_enable(2, 0);
116 case CLK_SRC_XI: return xi_enable(0);
123 static int enable_clk(struct clk *clk)
127 if (clk->root_id != CLK_SRC_NOROOT)
128 return root_clk_enable(clk->root_id);
131 reg = __raw_readl(clk->aclkreg);
133 __raw_writel(reg, clk->aclkreg);
136 reg = __raw_readl(clk->bclkctr);
137 reg |= 1 << clk->bclk_shift;
138 __raw_writel(reg, clk->bclkctr);
143 static void disable_clk(struct clk *clk)
147 if (clk->root_id != CLK_SRC_NOROOT) {
148 root_clk_disable(clk->root_id);
153 reg = __raw_readl(clk->bclkctr);
154 reg &= ~(1 << clk->bclk_shift);
155 __raw_writel(reg, clk->bclkctr);
158 reg = __raw_readl(clk->aclkreg);
160 __raw_writel(reg, clk->aclkreg);
164 static unsigned long get_rate_pll(int pll)
167 unsigned long s, m, p;
168 void __iomem *addr = pll_cfg_addr(pll);
170 reg = __raw_readl(addr);
171 s = (reg >> 16) & 0x07;
172 m = (reg >> 8) & 0xff;
175 return (m * xi_rate) / (p * (1 << s));
178 static unsigned long get_rate_pll_div(int pll)
181 unsigned long div = 0;
186 addr = CKC_BASE + CLKDIVC0_OFFS;
187 reg = __raw_readl(addr);
188 if (reg & CLKDIVC0_P0E)
189 div = (reg >> 24) & 0x3f;
192 addr = CKC_BASE + CLKDIVC0_OFFS;
193 reg = __raw_readl(addr);
194 if (reg & CLKDIVC0_P1E)
195 div = (reg >> 16) & 0x3f;
198 addr = CKC_BASE + CLKDIVC1_OFFS;
199 reg = __raw_readl(addr);
200 if (reg & CLKDIVC1_P2E)
201 div = __raw_readl(addr) & 0x3f;
204 return get_rate_pll(pll) / (div + 1);
207 static unsigned long get_rate_xi_div(void)
209 unsigned long div = 0;
210 u32 reg = __raw_readl(CKC_BASE + CLKDIVC0_OFFS);
212 if (reg & CLKDIVC0_XE)
213 div = (reg >> 8) & 0x3f;
215 return xi_rate / (div + 1);
218 static unsigned long get_rate_xti_div(void)
220 unsigned long div = 0;
221 u32 reg = __raw_readl(CKC_BASE + CLKDIVC0_OFFS);
223 if (reg & CLKDIVC0_XTE)
226 return xti_rate / (div + 1);
229 static unsigned long root_clk_get_rate(enum root_clks src)
232 case CLK_SRC_PLL0: return get_rate_pll(0);
233 case CLK_SRC_PLL1: return get_rate_pll(1);
234 case CLK_SRC_PLL2: return get_rate_pll(2);
235 case CLK_SRC_PLL0DIV: return get_rate_pll_div(0);
236 case CLK_SRC_PLL1DIV: return get_rate_pll_div(1);
237 case CLK_SRC_PLL2DIV: return get_rate_pll_div(2);
238 case CLK_SRC_XI: return xi_rate;
239 case CLK_SRC_XTI: return xti_rate;
240 case CLK_SRC_XIDIV: return get_rate_xi_div();
241 case CLK_SRC_XTIDIV: return get_rate_xti_div();
246 static unsigned long aclk_get_rate(struct clk *clk)
252 reg = __raw_readl(clk->aclkreg);
254 src = (reg >> ACLK_SEL_SHIFT) & CLK_SRC_MASK;
255 return root_clk_get_rate(src) / (div + 1);
258 static unsigned long aclk_best_div(struct clk *clk, unsigned long rate)
260 unsigned long div, src, freq, r1, r2;
262 src = __raw_readl(clk->aclkreg) >> ACLK_SEL_SHIFT;
264 freq = root_clk_get_rate(src);
265 div = freq / rate + 1;
267 r2 = freq / (div + 1);
270 if ((rate - r2) < (r1 - rate))
276 static unsigned long aclk_round_rate(struct clk *clk, unsigned long rate)
280 src = __raw_readl(clk->aclkreg) >> ACLK_SEL_SHIFT;
283 return root_clk_get_rate(src) / aclk_best_div(clk, rate);
286 static int aclk_set_rate(struct clk *clk, unsigned long rate)
290 reg = __raw_readl(clk->aclkreg) & ~ACLK_DIV_MASK;
291 reg |= aclk_best_div(clk, rate);
295 static unsigned long get_rate_sys(struct clk *clk)
299 src = __raw_readl(CKC_BASE + CLKCTRL_OFFS) & CLK_SRC_MASK;
300 return root_clk_get_rate(src);
303 static unsigned long get_rate_bus(struct clk *clk)
307 div = (__raw_readl(CKC_BASE + CLKCTRL_OFFS) >> 4) & 0xff;
308 return get_rate_sys(clk) / (div + 1);
311 static unsigned long get_rate_cpu(struct clk *clk)
313 unsigned int reg, div, fsys, fbus;
315 fbus = get_rate_bus(clk);
316 reg = __raw_readl(CKC_BASE + CLKCTRL_OFFS);
319 fsys = get_rate_sys(clk);
320 div = (reg >> 16) & 0x0f;
321 return fbus + ((fsys - fbus) * (div + 1)) / 16;
324 static unsigned long get_rate_root(struct clk *clk)
326 return root_clk_get_rate(clk->root_id);
329 static int aclk_set_parent(struct clk *clock, struct clk *parent)
333 if (clock->parent == parent)
336 clock->parent = parent;
341 if (parent->root_id == CLK_SRC_NOROOT)
343 reg = __raw_readl(clock->aclkreg);
344 reg &= ~ACLK_SEL_MASK;
345 reg |= (parent->root_id << ACLK_SEL_SHIFT) & ACLK_SEL_MASK;
346 __raw_writel(reg, clock->aclkreg);
351 #define DEFINE_ROOT_CLOCK(name, ri, p) \
352 static struct clk name = { \
354 .get_rate = get_rate_root, \
355 .enable = enable_clk, \
356 .disable = disable_clk, \
360 #define DEFINE_SPECIAL_CLOCK(name, gr, p) \
361 static struct clk name = { \
362 .root_id = CLK_SRC_NOROOT, \
367 #define DEFINE_ACLOCK(name, bc, bs, ar) \
368 static struct clk name = { \
369 .root_id = CLK_SRC_NOROOT, \
373 .get_rate = aclk_get_rate, \
374 .set_rate = aclk_set_rate, \
375 .round_rate = aclk_round_rate, \
376 .enable = enable_clk, \
377 .disable = disable_clk, \
378 .set_parent = aclk_set_parent, \
381 #define DEFINE_BCLOCK(name, bc, bs, gr, p) \
382 static struct clk name = { \
383 .root_id = CLK_SRC_NOROOT, \
387 .enable = enable_clk, \
388 .disable = disable_clk, \
392 DEFINE_ROOT_CLOCK(xi, CLK_SRC_XI, NULL)
393 DEFINE_ROOT_CLOCK(xti, CLK_SRC_XTI, NULL)
394 DEFINE_ROOT_CLOCK(xidiv, CLK_SRC_XIDIV, &xi)
395 DEFINE_ROOT_CLOCK(xtidiv, CLK_SRC_XTIDIV, &xti)
396 DEFINE_ROOT_CLOCK(pll0, CLK_SRC_PLL0, &xi)
397 DEFINE_ROOT_CLOCK(pll1, CLK_SRC_PLL1, &xi)
398 DEFINE_ROOT_CLOCK(pll2, CLK_SRC_PLL2, &xi)
399 DEFINE_ROOT_CLOCK(pll0div, CLK_SRC_PLL0DIV, &pll0)
400 DEFINE_ROOT_CLOCK(pll1div, CLK_SRC_PLL1DIV, &pll1)
401 DEFINE_ROOT_CLOCK(pll2div, CLK_SRC_PLL2DIV, &pll2)
403 /* The following 3 clocks are special and are initialized explicitly later */
404 DEFINE_SPECIAL_CLOCK(sys, get_rate_sys, NULL)
405 DEFINE_SPECIAL_CLOCK(bus, get_rate_bus, &sys)
406 DEFINE_SPECIAL_CLOCK(cpu, get_rate_cpu, &sys)
408 DEFINE_ACLOCK(tct, NULL, 0, ACLKTCT)
409 DEFINE_ACLOCK(tcx, NULL, 0, ACLKTCX)
410 DEFINE_ACLOCK(tcz, NULL, 0, ACLKTCZ)
411 DEFINE_ACLOCK(ref, NULL, 0, ACLKREF)
412 DEFINE_ACLOCK(uart0, BCLKCTR0, 5, ACLKUART0)
413 DEFINE_ACLOCK(uart1, BCLKCTR0, 23, ACLKUART1)
414 DEFINE_ACLOCK(uart2, BCLKCTR0, 6, ACLKUART2)
415 DEFINE_ACLOCK(uart3, BCLKCTR0, 8, ACLKUART3)
416 DEFINE_ACLOCK(uart4, BCLKCTR1, 6, ACLKUART4)
417 DEFINE_ACLOCK(i2c, BCLKCTR0, 7, ACLKI2C)
418 DEFINE_ACLOCK(adc, BCLKCTR0, 10, ACLKADC)
419 DEFINE_ACLOCK(usbh0, BCLKCTR0, 11, ACLKUSBH)
420 DEFINE_ACLOCK(lcd, BCLKCTR0, 13, ACLKLCD)
421 DEFINE_ACLOCK(sd0, BCLKCTR0, 17, ACLKSDH0)
422 DEFINE_ACLOCK(sd1, BCLKCTR1, 5, ACLKSDH1)
423 DEFINE_ACLOCK(spi0, BCLKCTR0, 24, ACLKSPI0)
424 DEFINE_ACLOCK(spi1, BCLKCTR0, 30, ACLKSPI1)
425 DEFINE_ACLOCK(spdif, BCLKCTR1, 2, ACLKSPDIF)
426 DEFINE_ACLOCK(c3dec, BCLKCTR1, 9, ACLKC3DEC)
427 DEFINE_ACLOCK(can0, BCLKCTR1, 10, ACLKCAN0)
428 DEFINE_ACLOCK(can1, BCLKCTR1, 11, ACLKCAN1)
429 DEFINE_ACLOCK(gsb0, BCLKCTR1, 13, ACLKGSB0)
430 DEFINE_ACLOCK(gsb1, BCLKCTR1, 14, ACLKGSB1)
431 DEFINE_ACLOCK(gsb2, BCLKCTR1, 15, ACLKGSB2)
432 DEFINE_ACLOCK(gsb3, BCLKCTR1, 16, ACLKGSB3)
433 DEFINE_ACLOCK(usbh1, BCLKCTR1, 20, ACLKUSBH)
435 DEFINE_BCLOCK(dai0, BCLKCTR0, 0, NULL, NULL)
436 DEFINE_BCLOCK(pic, BCLKCTR0, 1, NULL, NULL)
437 DEFINE_BCLOCK(tc, BCLKCTR0, 2, NULL, NULL)
438 DEFINE_BCLOCK(gpio, BCLKCTR0, 3, NULL, NULL)
439 DEFINE_BCLOCK(usbd, BCLKCTR0, 4, NULL, NULL)
440 DEFINE_BCLOCK(ecc, BCLKCTR0, 9, NULL, NULL)
441 DEFINE_BCLOCK(gdma0, BCLKCTR0, 12, NULL, NULL)
442 DEFINE_BCLOCK(rtc, BCLKCTR0, 15, NULL, NULL)
443 DEFINE_BCLOCK(nfc, BCLKCTR0, 16, NULL, NULL)
444 DEFINE_BCLOCK(g2d, BCLKCTR0, 18, NULL, NULL)
445 DEFINE_BCLOCK(gdma1, BCLKCTR0, 22, NULL, NULL)
446 DEFINE_BCLOCK(mscl, BCLKCTR0, 25, NULL, NULL)
447 DEFINE_BCLOCK(bdma, BCLKCTR1, 0, NULL, NULL)
448 DEFINE_BCLOCK(adma0, BCLKCTR1, 1, NULL, NULL)
449 DEFINE_BCLOCK(scfg, BCLKCTR1, 3, NULL, NULL)
450 DEFINE_BCLOCK(cid, BCLKCTR1, 4, NULL, NULL)
451 DEFINE_BCLOCK(dai1, BCLKCTR1, 7, NULL, NULL)
452 DEFINE_BCLOCK(adma1, BCLKCTR1, 8, NULL, NULL)
453 DEFINE_BCLOCK(gps, BCLKCTR1, 12, NULL, NULL)
454 DEFINE_BCLOCK(gdma2, BCLKCTR1, 17, NULL, NULL)
455 DEFINE_BCLOCK(gdma3, BCLKCTR1, 18, NULL, NULL)
456 DEFINE_BCLOCK(ddrc, BCLKCTR1, 19, NULL, NULL)
458 #define _REGISTER_CLOCK(d, n, c) \
465 static struct clk_lookup lookups[] = {
466 _REGISTER_CLOCK(NULL, "bus", bus)
467 _REGISTER_CLOCK(NULL, "cpu", cpu)
468 _REGISTER_CLOCK(NULL, "tct", tct)
469 _REGISTER_CLOCK(NULL, "tcx", tcx)
470 _REGISTER_CLOCK(NULL, "tcz", tcz)
471 _REGISTER_CLOCK(NULL, "ref", ref)
472 _REGISTER_CLOCK(NULL, "dai0", dai0)
473 _REGISTER_CLOCK(NULL, "pic", pic)
474 _REGISTER_CLOCK(NULL, "tc", tc)
475 _REGISTER_CLOCK(NULL, "gpio", gpio)
476 _REGISTER_CLOCK(NULL, "usbd", usbd)
477 _REGISTER_CLOCK("tcc-uart.0", NULL, uart0)
478 _REGISTER_CLOCK("tcc-uart.2", NULL, uart2)
479 _REGISTER_CLOCK("tcc-i2c", NULL, i2c)
480 _REGISTER_CLOCK("tcc-uart.3", NULL, uart3)
481 _REGISTER_CLOCK(NULL, "ecc", ecc)
482 _REGISTER_CLOCK(NULL, "adc", adc)
483 _REGISTER_CLOCK("tcc-usbh.0", "usb", usbh0)
484 _REGISTER_CLOCK(NULL, "gdma0", gdma0)
485 _REGISTER_CLOCK(NULL, "lcd", lcd)
486 _REGISTER_CLOCK(NULL, "rtc", rtc)
487 _REGISTER_CLOCK(NULL, "nfc", nfc)
488 _REGISTER_CLOCK("tcc-mmc.0", NULL, sd0)
489 _REGISTER_CLOCK(NULL, "g2d", g2d)
490 _REGISTER_CLOCK(NULL, "gdma1", gdma1)
491 _REGISTER_CLOCK("tcc-uart.1", NULL, uart1)
492 _REGISTER_CLOCK("tcc-spi.0", NULL, spi0)
493 _REGISTER_CLOCK(NULL, "mscl", mscl)
494 _REGISTER_CLOCK("tcc-spi.1", NULL, spi1)
495 _REGISTER_CLOCK(NULL, "bdma", bdma)
496 _REGISTER_CLOCK(NULL, "adma0", adma0)
497 _REGISTER_CLOCK(NULL, "spdif", spdif)
498 _REGISTER_CLOCK(NULL, "scfg", scfg)
499 _REGISTER_CLOCK(NULL, "cid", cid)
500 _REGISTER_CLOCK("tcc-mmc.1", NULL, sd1)
501 _REGISTER_CLOCK("tcc-uart.4", NULL, uart4)
502 _REGISTER_CLOCK(NULL, "dai1", dai1)
503 _REGISTER_CLOCK(NULL, "adma1", adma1)
504 _REGISTER_CLOCK(NULL, "c3dec", c3dec)
505 _REGISTER_CLOCK("tcc-can.0", NULL, can0)
506 _REGISTER_CLOCK("tcc-can.1", NULL, can1)
507 _REGISTER_CLOCK(NULL, "gps", gps)
508 _REGISTER_CLOCK("tcc-gsb.0", NULL, gsb0)
509 _REGISTER_CLOCK("tcc-gsb.1", NULL, gsb1)
510 _REGISTER_CLOCK("tcc-gsb.2", NULL, gsb2)
511 _REGISTER_CLOCK("tcc-gsb.3", NULL, gsb3)
512 _REGISTER_CLOCK(NULL, "gdma2", gdma2)
513 _REGISTER_CLOCK(NULL, "gdma3", gdma3)
514 _REGISTER_CLOCK(NULL, "ddrc", ddrc)
515 _REGISTER_CLOCK("tcc-usbh.1", "usb", usbh1)
518 static struct clk *root_clk_by_index(enum root_clks src)
521 case CLK_SRC_PLL0: return &pll0;
522 case CLK_SRC_PLL1: return &pll1;
523 case CLK_SRC_PLL2: return &pll2;
524 case CLK_SRC_PLL0DIV: return &pll0div;
525 case CLK_SRC_PLL1DIV: return &pll1div;
526 case CLK_SRC_PLL2DIV: return &pll2div;
527 case CLK_SRC_XI: return ξ
528 case CLK_SRC_XTI: return &xti;
529 case CLK_SRC_XIDIV: return &xidiv;
530 case CLK_SRC_XTIDIV: return &xtidiv;
531 default: return NULL;
535 static void find_aclk_parent(struct clk *clk)
543 src = __raw_readl(clk->aclkreg) >> ACLK_SEL_SHIFT;
546 clock = root_clk_by_index(src);
551 clk->set_parent = aclk_set_parent;
554 void __init tcc_clocks_init(unsigned long xi_freq, unsigned long xti_freq)
561 /* fixup parents and add the clock */
562 for (i = 0; i < ARRAY_SIZE(lookups); i++) {
563 find_aclk_parent(lookups[i].clk);
564 clkdev_add(&lookups[i]);
566 tcc8k_timer_init(&tcz, (void __iomem *)TIMER_BASE, INT_TC32);