arch/arm/mach-stmp37xx/include/mach/regs-pinctrl.h

   1 /*
   2  * STMP pinmux register definitions
   3  *
   4  * Copyright (c) 2008 Freescale Semiconductor
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  19  */
  20 #ifndef _INCLUDE_ASM_ARCH_REGS_PINCTRL_H
  21 #define _INCLUDE_ASM_ARCH_REGS_PINCTRL_H
  22
  23 #include <mach/stmp3xxx_regs.h>
  24
  25 #ifndef REGS_PINCTRL_BASE
  26 #define REGS_PINCTRL_BASE (REGS_BASE + 0x00018000)
  27 #endif /* REGS_PINCTRL_BASE */
  28
  29 HW_REGISTER(HW_PINCTRL_CTRL, REGS_PINCTRL_BASE, 0)
  30
  31 #define HW_PINCTRL_MUXSEL0_ADDR (REGS_PINCTRL_BASE + 0x100)
  32 HW_REGISTER(HW_PINCTRL_MUXSEL0, REGS_PINCTRL_BASE, 0x100)
  33 #define HW_PINCTRL_MUXSEL1_ADDR (REGS_PINCTRL_BASE + 0x110)
  34 HW_REGISTER(HW_PINCTRL_MUXSEL1, REGS_PINCTRL_BASE, 0x110)
  35 #define HW_PINCTRL_MUXSEL2_ADDR (REGS_PINCTRL_BASE + 0x120)
  36 HW_REGISTER(HW_PINCTRL_MUXSEL2, REGS_PINCTRL_BASE, 0x120)
  37 #define HW_PINCTRL_MUXSEL3_ADDR (REGS_PINCTRL_BASE + 0x130)
  38 HW_REGISTER(HW_PINCTRL_MUXSEL3, REGS_PINCTRL_BASE, 0x130)
  39 #define BM_PINCTRL_MUXSEL3_BANK1_PIN28      0x03000000
  40 #define HW_PINCTRL_MUXSEL4_ADDR (REGS_PINCTRL_BASE + 0x140)
  41 HW_REGISTER(HW_PINCTRL_MUXSEL4, REGS_PINCTRL_BASE, 0x140)
  42 #define BM_PINCTRL_MUXSEL4_BANK2_PIN03      0x000000C0
  43 #define BM_PINCTRL_MUXSEL4_BANK2_PIN04      0x00000300
  44 #define HW_PINCTRL_MUXSEL5_ADDR (REGS_PINCTRL_BASE + 0x150)
  45 HW_REGISTER(HW_PINCTRL_MUXSEL5, REGS_PINCTRL_BASE, 0x150)
  46 #define HW_PINCTRL_MUXSEL6_ADDR (REGS_PINCTRL_BASE + 0x160)
  47 HW_REGISTER(HW_PINCTRL_MUXSEL6, REGS_PINCTRL_BASE, 0x160)
  48 #define HW_PINCTRL_MUXSEL7_ADDR (REGS_PINCTRL_BASE + 0x170)
  49 HW_REGISTER(HW_PINCTRL_MUXSEL7, REGS_PINCTRL_BASE, 0x170)
  50
  51 HW_REGISTER(HW_PINCTRL_DRIVE0, REGS_PINCTRL_BASE, 0x200)
  52 #define HW_PINCTRL_DRIVE0_ADDR (REGS_PINCTRL_BASE + 0x200)
  53 HW_REGISTER(HW_PINCTRL_DRIVE1, REGS_PINCTRL_BASE, 0x210)
  54 #define HW_PINCTRL_DRIVE1_ADDR (REGS_PINCTRL_BASE + 0x210)
  55 HW_REGISTER(HW_PINCTRL_DRIVE2, REGS_PINCTRL_BASE, 0x220)
  56 #define HW_PINCTRL_DRIVE2_ADDR (REGS_PINCTRL_BASE + 0x220)
  57 HW_REGISTER(HW_PINCTRL_DRIVE3, REGS_PINCTRL_BASE, 0x230)
  58 #define HW_PINCTRL_DRIVE3_ADDR (REGS_PINCTRL_BASE + 0x230)
  59 HW_REGISTER(HW_PINCTRL_DRIVE4, REGS_PINCTRL_BASE, 0x240)
  60 #define HW_PINCTRL_DRIVE4_ADDR (REGS_PINCTRL_BASE + 0x240)
  61 HW_REGISTER(HW_PINCTRL_DRIVE5, REGS_PINCTRL_BASE, 0x250)
  62 #define HW_PINCTRL_DRIVE5_ADDR (REGS_PINCTRL_BASE + 0x250)
  63 HW_REGISTER(HW_PINCTRL_DRIVE6, REGS_PINCTRL_BASE, 0x260)
  64 #define HW_PINCTRL_DRIVE6_ADDR (REGS_PINCTRL_BASE + 0x260)
  65 HW_REGISTER(HW_PINCTRL_DRIVE7, REGS_PINCTRL_BASE, 0x270)
  66 #define HW_PINCTRL_DRIVE7_ADDR (REGS_PINCTRL_BASE + 0x270)
  67 HW_REGISTER(HW_PINCTRL_DRIVE8, REGS_PINCTRL_BASE, 0x280)
  68 #define HW_PINCTRL_DRIVE8_ADDR (REGS_PINCTRL_BASE + 0x280)
  69 HW_REGISTER(HW_PINCTRL_DRIVE9, REGS_PINCTRL_BASE, 0x290)
  70 #define HW_PINCTRL_DRIVE9_ADDR (REGS_PINCTRL_BASE + 0x290)
  71 HW_REGISTER(HW_PINCTRL_DRIVE10, REGS_PINCTRL_BASE, 0x2a0)
  72 #define HW_PINCTRL_DRIVE10_ADDR (REGS_PINCTRL_BASE + 0x2a0)
  73 HW_REGISTER(HW_PINCTRL_DRIVE11, REGS_PINCTRL_BASE, 0x2b0)
  74 #define HW_PINCTRL_DRIVE11_ADDR (REGS_PINCTRL_BASE + 0x2b0)
  75 HW_REGISTER(HW_PINCTRL_DRIVE12, REGS_PINCTRL_BASE, 0x2c0)
  76 #define HW_PINCTRL_DRIVE12_ADDR (REGS_PINCTRL_BASE + 0x2c0)
  77 HW_REGISTER(HW_PINCTRL_DRIVE13, REGS_PINCTRL_BASE, 0x2d0)
  78 #define HW_PINCTRL_DRIVE13_ADDR (REGS_PINCTRL_BASE + 0x2d0)
  79 HW_REGISTER(HW_PINCTRL_DRIVE14, REGS_PINCTRL_BASE, 0x2e0)
  80 #define HW_PINCTRL_DRIVE14_ADDR (REGS_PINCTRL_BASE + 0x2e0)
  81
  82
  83 HW_REGISTER(HW_PINCTRL_PULL0, REGS_PINCTRL_BASE, 0x300)
  84 #define HW_PINCTRL_PULL0_ADDR (REGS_PINCTRL_BASE + 0x300)
  85 #define BM_PINCTRL_PULL0_BANK0_PIN01      0x00000002
  86 #define BM_PINCTRL_PULL0_BANK0_PIN02      0x00000004
  87 #define BM_PINCTRL_PULL0_BANK0_PIN03      0x00000008
  88 #define BM_PINCTRL_PULL0_BANK0_PIN04      0x00000010
  89 #define BM_PINCTRL_PULL0_BANK0_PIN20      0x00100000
  90 HW_REGISTER(HW_PINCTRL_PULL1, REGS_PINCTRL_BASE, 0x310)
  91 #define HW_PINCTRL_PULL1_ADDR (REGS_PINCTRL_BASE + 0x310)
  92 #define BM_PINCTRL_PULL1_BANK1_PIN22      0x00400000
  93 #define BM_PINCTRL_PULL1_BANK1_PIN24      0x01000000
  94 #define BM_PINCTRL_PULL1_BANK1_PIN25      0x02000000
  95 #define BM_PINCTRL_PULL1_BANK1_PIN26      0x04000000
  96 #define BM_PINCTRL_PULL1_BANK1_PIN27      0x08000000
  97 HW_REGISTER(HW_PINCTRL_PULL2, REGS_PINCTRL_BASE, 0x320)
  98 #define HW_PINCTRL_PULL2_ADDR (REGS_PINCTRL_BASE + 0x320)
  99 HW_REGISTER(HW_PINCTRL_PULL3, REGS_PINCTRL_BASE, 0x330)
 100 #define HW_PINCTRL_PULL3_ADDR (REGS_PINCTRL_BASE + 0x330)
 101
 102 #define HW_PINCTRL_DOUT0_ADDR (REGS_PINCTRL_BASE + 0x400)
 103 HW_REGISTER(HW_PINCTRL_DOUT0, REGS_PINCTRL_BASE, 0x400)
 104 #define HW_PINCTRL_DOUT1_ADDR (REGS_PINCTRL_BASE + 0x410)
 105 HW_REGISTER(HW_PINCTRL_DOUT1, REGS_PINCTRL_BASE, 0x410)
 106 #define HW_PINCTRL_DOUT2_ADDR (REGS_PINCTRL_BASE + 0x420)
 107 HW_REGISTER(HW_PINCTRL_DOUT2, REGS_PINCTRL_BASE, 0x420)
 108
 109 #define HW_PINCTRL_DIN0_ADDR (REGS_PINCTRL_BASE + 0x500)
 110 HW_REGISTER_RO(HW_PINCTRL_DIN0, REGS_PINCTRL_BASE, 0x500)
 111 #define HW_PINCTRL_DIN1_ADDR (REGS_PINCTRL_BASE + 0x510)
 112 HW_REGISTER_RO(HW_PINCTRL_DIN1, REGS_PINCTRL_BASE, 0x510)
 113 #define HW_PINCTRL_DIN2_ADDR (REGS_PINCTRL_BASE + 0x520)
 114 HW_REGISTER_RO(HW_PINCTRL_DIN2, REGS_PINCTRL_BASE, 0x520)
 115
 116 #define HW_PINCTRL_DOE0_ADDR (REGS_PINCTRL_BASE + 0x600)
 117 HW_REGISTER(HW_PINCTRL_DOE0, REGS_PINCTRL_BASE, 0x600)
 118 #define HW_PINCTRL_DOE1_ADDR (REGS_PINCTRL_BASE + 0x610)
 119 HW_REGISTER(HW_PINCTRL_DOE1, REGS_PINCTRL_BASE, 0x610)
 120 #define HW_PINCTRL_DOE2_ADDR (REGS_PINCTRL_BASE + 0x620)
 121 HW_REGISTER(HW_PINCTRL_DOE2, REGS_PINCTRL_BASE, 0x620)
 122
 123 HW_REGISTER(HW_PINCTRL_PIN2IRQ0, REGS_PINCTRL_BASE, 0x700)
 124 #define HW_PINCTRL_PIN2IRQ0_ADDR (REGS_PINCTRL_BASE + 0x700)
 125 HW_REGISTER(HW_PINCTRL_PIN2IRQ1, REGS_PINCTRL_BASE, 0x710)
 126 #define HW_PINCTRL_PIN2IRQ1_ADDR (REGS_PINCTRL_BASE + 0x710)
 127 HW_REGISTER(HW_PINCTRL_PIN2IRQ2, REGS_PINCTRL_BASE, 0x720)
 128 #define HW_PINCTRL_PIN2IRQ2_ADDR (REGS_PINCTRL_BASE + 0x720)
 129
 130 HW_REGISTER(HW_PINCTRL_IRQEN0, REGS_PINCTRL_BASE, 0x800)
 131 #define HW_PINCTRL_IRQEN0_ADDR (REGS_PINCTRL_BASE + 0x800)
 132 HW_REGISTER(HW_PINCTRL_IRQEN1, REGS_PINCTRL_BASE, 0x810)
 133 #define HW_PINCTRL_IRQEN1_ADDR (REGS_PINCTRL_BASE + 0x810)
 134 HW_REGISTER(HW_PINCTRL_IRQEN2, REGS_PINCTRL_BASE, 0x820)
 135 #define HW_PINCTRL_IRQEN2_ADDR (REGS_PINCTRL_BASE + 0x820)
 136
 137 HW_REGISTER(HW_PINCTRL_IRQLEVEL0, REGS_PINCTRL_BASE, 0x900)
 138 #define HW_PINCTRL_IRQLEVEL0_ADDR (REGS_PINCTRL_BASE + 0x900)
 139 HW_REGISTER(HW_PINCTRL_IRQLEVEL1, REGS_PINCTRL_BASE, 0x910)
 140 #define HW_PINCTRL_IRQLEVEL1_ADDR (REGS_PINCTRL_BASE + 0x910)
 141 HW_REGISTER(HW_PINCTRL_IRQLEVEL2, REGS_PINCTRL_BASE, 0x920)
 142 #define HW_PINCTRL_IRQLEVEL2_ADDR (REGS_PINCTRL_BASE + 0x920)
 143
 144 HW_REGISTER(HW_PINCTRL_IRQPOL0, REGS_PINCTRL_BASE, 0xA00)
 145 #define HW_PINCTRL_IRQPOL0_ADDR (REGS_PINCTRL_BASE + 0xa00)
 146 HW_REGISTER(HW_PINCTRL_IRQPOL1, REGS_PINCTRL_BASE, 0xA10)
 147 #define HW_PINCTRL_IRQPOL1_ADDR (REGS_PINCTRL_BASE + 0xa10)
 148 HW_REGISTER(HW_PINCTRL_IRQPOL2, REGS_PINCTRL_BASE, 0xA20)
 149 #define HW_PINCTRL_IRQPOL2_ADDR (REGS_PINCTRL_BASE + 0xa20)
 150
 151 HW_REGISTER(HW_PINCTRL_IRQSTAT0, REGS_PINCTRL_BASE, 0xB00)
 152 #define HW_PINCTRL_IRQSTAT0_ADDR (REGS_PINCTRL_BASE + 0xb00)
 153 HW_REGISTER(HW_PINCTRL_IRQSTAT1, REGS_PINCTRL_BASE, 0xB10)
 154 #define HW_PINCTRL_IRQSTAT1_ADDR (REGS_PINCTRL_BASE + 0xb10)
 155 HW_REGISTER(HW_PINCTRL_IRQSTAT2, REGS_PINCTRL_BASE, 0xB20)
 156 #define HW_PINCTRL_IRQSTAT2_ADDR (REGS_PINCTRL_BASE + 0xb20)
 157
 158 #endif /* _INCLUDE_ASM_ARCH_REGS_PINCTRL_H */
 159