arch/arm/mach-stmp37xx/include/mach/regs-apbh.h

   1 /*
   2  * STMP APBH Register Definitions
   3  *
   4  * Copyright (c) 2008 Freescale Semiconductor
   5  * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  20  */
  21 #ifndef _INCLUDE_ASM_ARCH_REGS_APBH_H
  22 #define _INCLUDE_ASM_ARCH_REGS_APBH_H
  23
  24 #include <mach/stmp3xxx_regs.h>
  25
  26 #ifndef REGS_APBH_BASE
  27 #define REGS_APBH_BASE (REGS_BASE + 0x00004000)
  28 #endif
  29
  30 HW_REGISTER(HW_APBH_CTRL0, REGS_APBH_BASE, 0x00)
  31 #define BP_APBH_CTRL0_SFTRST      31
  32 #define BM_APBH_CTRL0_SFTRST      0x80000000
  33 #define BP_APBH_CTRL0_CLKGATE      30
  34 #define BM_APBH_CTRL0_CLKGATE      0x40000000
  35 #define BP_APBH_CTRL0_RESET_CHANNEL      16
  36 #define BM_APBH_CTRL0_RESET_CHANNEL      0x00FF0000
  37 #define BF_APBH_CTRL0_RESET_CHANNEL(v)   \
  38         (((v) << BP_APBH_CTRL0_RESET_CHANNEL) & BM_APBH_CTRL0_RESET_CHANNEL)
  39 HW_REGISTER(HW_APBH_CTRL1, REGS_APBH_BASE, 0x10)
  40 #define BP_APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN      9
  41 #define BM_APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN      0x00000200
  42 #define BP_APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN      8
  43 #define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN      0x00000100
  44 #define BP_APBH_CTRL1_CH7_CMDCMPLT_IRQ      7
  45 #define BM_APBH_CTRL1_CH7_CMDCMPLT_IRQ      0x00000080
  46 #define BP_APBH_CTRL1_CH1_CMDCMPLT_IRQ      1
  47 #define BM_APBH_CTRL1_CH1_CMDCMPLT_IRQ      0x00000002
  48 #define BP_APBH_CTRL1_CH0_CMDCMPLT_IRQ      0
  49 #define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ      0x00000001
  50 #define BP_APBH_CTRL1_CH1_ERR_IRQ           17
  51 #define BM_APBH_CTRL1_CH1_ERR_IRQ          0x00020000
  52 HW_REGISTER_0(HW_APBH_DEVSEL, REGS_APBH_BASE, 0x20)
  53 HW_REGISTER_RO_INDEXED(HW_APBH_CHn_CURCMDAR, REGS_APBH_BASE, 0x40, 0x70)
  54 HW_REGISTER_0_INDEXED(HW_APBH_CHn_NXTCMDAR, REGS_APBH_BASE, 0x50, 0x70)
  55 #define BP_APBH_CHn_NXTCMDAR_CMD_ADDR      0
  56 #define BM_APBH_CHn_NXTCMDAR_CMD_ADDR      0xFFFFFFFF
  57 #define BF_APBH_CHn_NXTCMDAR_CMD_ADDR(v)   ((u32) v)
  58 HW_REGISTER_RO_INDEXED(HW_APBH_CHn_CMD, REGS_APBH_BASE, 0x60, 0x70)
  59 #define BM_APBH_CHn_CMD_XFER_COUNT              0xFFFF0000
  60 #define BP_APBH_CHn_CMD_XFER_COUNT              16
  61 #define BF_APBH_CHn_CMD_XFER_COUNT(v)           \
  62         (((v) << BP_APBH_CHn_CMD_XFER_COUNT) & BM_APBH_CHn_CMD_XFER_COUNT)
  63 #define BM_APBH_CHn_CMD_CMDWORDS                0x0000F000
  64 #define BP_APBH_CHn_CMD_CMDWORDS                12
  65 #define BF_APBH_CHn_CMD_CMDWORDS(v)             \
  66         (((v) << BP_APBH_CHn_CMD_CMDWORDS) & BM_APBH_CHn_CMD_CMDWORDS)
  67 #define BM_APBH_CHn_CMD_WAIT4ENDCMD             0x00000080
  68 #define BM_APBH_CHn_CMD_SEMAPHORE               0x00000040
  69 #define BP_APBH_CHn_CMD_SEMAPHORE               6
  70 #define BF_APBH_CHn_CMD_SEMAPHORE(v)            \
  71         (((v) << BP_APBH_CHn_CMD_SEMAPHORE) & BM_APBH_CHn_CMD_SEMAPHORE)
  72 #define BM_APBH_CHn_CMD_NANDWAIT4READY   0x00000020
  73 #define BP_APBH_CHn_CMD_NANDLOCK                4
  74 #define BM_APBH_CHn_CMD_NANDLOCK                0x00000010
  75 #define BF_APBH_CHn_CMD_NANDLOCK(v)             \
  76         (((v) << BP_APBH_CHn_CMD_NANDLOCK) & BM_APBH_CHn_CMD_NANDLOCK)
  77 #define BM_APBH_CHn_CMD_IRQONCMPLT              0x00000008
  78 #define BM_APBH_CHn_CMD_CHAIN           0x00000004
  79 #define BM_APBH_CHn_CMD_DMA_READ                0x00000003
  80 #define BP_APBH_CHn_CMD_DMA_READ                0
  81 #define BF_APBH_CHn_CMD_DMA_READ(v)             \
  82         (((v) << BP_APBH_CHn_CMD_DMA_READ) & BM_APBH_CHn_CMD_DMA_READ)
  83 #define BF_APBH_CHn_CMD_COMMAND(v)              \
  84         (((v) << BP_APBH_CHn_CMD_DMA_READ) & BM_APBH_CHn_CMD_DMA_READ)
  85 #define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER  0x0
  86 #define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE    0x1
  87 #define BV_APBH_CHn_CMD_COMMAND__DMA_READ     0x2
  88 #define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE    0x3
  89 HW_REGISTER_INDEXED(HW_APBH_CHn_BAR, REGS_APBH_BASE, 0x70, 0x70)
  90 HW_REGISTER_0_INDEXED(HW_APBH_CHn_SEMA, REGS_APBH_BASE, 0x80, 0x70)
  91 #define BP_APBH_CHn_SEMA_INCREMENT_SEMA      0
  92 #define BM_APBH_CHn_SEMA_INCREMENT_SEMA      0x000000FF
  93 #define BF_APBH_CHn_SEMA_INCREMENT_SEMA(v)   \
  94         (((v) << BP_APBH_CHn_SEMA_INCREMENT_SEMA) & \
  95         BM_APBH_CHn_SEMA_INCREMENT_SEMA)
  96 #define BP_APBH_CHn_SEMA_PHORE      16
  97 #define BM_APBH_CHn_SEMA_PHORE      0x00FF0000
  98 HW_REGISTER_RO_INDEXED(HW_APBH_CHn_DEBUG1, REGS_APBH_BASE, 0x90, 0x70)
  99 HW_REGISTER_RO_INDEXED(HW_APBH_CHn_DEBUG2, REGS_APBH_BASE, 0xA0, 0x70)
 100 HW_REGISTER_RO(HW_APBH_VERSION, REGS_APBH_BASE, 0x3F0)
 101
 102 #endif /* _INCLUDE_ASM_ARCH_REGS_APBH_H */