arch/arm/mach-stm32mp/include/mach/stm32.h

   1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
   2 /*
   3  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
   4  */
   5
   6 #ifndef _MACH_STM32_H_
   7 #define _MACH_STM32_H_
   8
   9 #include <linux/sizes.h>
  10 #ifndef __ASSEMBLY__
  11 #include <linux/bitops.h>
  12
  13 enum boot_device {
  14         BOOT_FLASH_SD = 0x10,
  15         BOOT_FLASH_SD_1 = 0x11,
  16         BOOT_FLASH_SD_2 = 0x12,
  17         BOOT_FLASH_SD_3 = 0x13,
  18
  19         BOOT_FLASH_EMMC = 0x20,
  20         BOOT_FLASH_EMMC_1 = 0x21,
  21         BOOT_FLASH_EMMC_2 = 0x22,
  22         BOOT_FLASH_EMMC_3 = 0x23,
  23
  24         BOOT_FLASH_NAND = 0x30,
  25         BOOT_FLASH_NAND_FMC = 0x31,
  26
  27         BOOT_FLASH_NOR = 0x40,
  28         BOOT_FLASH_NOR_QSPI = 0x41,
  29
  30         BOOT_SERIAL_UART = 0x50,
  31         BOOT_SERIAL_UART_1 = 0x51,
  32         BOOT_SERIAL_UART_2 = 0x52,
  33         BOOT_SERIAL_UART_3 = 0x53,
  34         BOOT_SERIAL_UART_4 = 0x54,
  35         BOOT_SERIAL_UART_5 = 0x55,
  36         BOOT_SERIAL_UART_6 = 0x56,
  37         BOOT_SERIAL_UART_7 = 0x57,
  38         BOOT_SERIAL_UART_8 = 0x58,
  39
  40         BOOT_SERIAL_USB = 0x60,
  41         BOOT_SERIAL_USB_OTG = 0x62,
  42
  43         BOOT_FLASH_SPINAND = 0x70,
  44         BOOT_FLASH_SPINAND_1 = 0x71,
  45 };
  46
  47 #define TAMP_BOOT_MODE_MASK             GENMASK(15, 8)
  48 #define TAMP_BOOT_MODE_SHIFT            8
  49 #define TAMP_BOOT_AUTH_MASK             GENMASK(23, 16)
  50 #define TAMP_BOOT_AUTH_SHIFT            16
  51 #define TAMP_BOOT_DEVICE_MASK           GENMASK(7, 4)
  52 #define TAMP_BOOT_INSTANCE_MASK         GENMASK(3, 0)
  53 #define TAMP_BOOT_AUTH_ST_MASK          GENMASK(7, 4)
  54 #define TAMP_BOOT_PARTITION_MASK        GENMASK(3, 0)
  55 #define TAMP_BOOT_FORCED_MASK           GENMASK(7, 0)
  56
  57 enum forced_boot_mode {
  58         BOOT_NORMAL = 0x00,
  59         BOOT_FASTBOOT = 0x01,
  60         BOOT_RECOVERY = 0x02,
  61         BOOT_STM32PROG = 0x03,
  62         BOOT_UMS_MMC0 = 0x10,
  63         BOOT_UMS_MMC1 = 0x11,
  64         BOOT_UMS_MMC2 = 0x12,
  65 };
  66
  67 #endif
  68
  69 /*
  70  * Peripheral memory map
  71  * only address used before device tree parsing
  72  */
  73
  74 #if defined(CONFIG_STM32MP15x) || defined(CONFIG_STM32MP13x)
  75 #define STM32_RCC_BASE                  0x50000000
  76 #define STM32_PWR_BASE                  0x50001000
  77 #define STM32_SYSCFG_BASE               0x50020000
  78 #ifdef CONFIG_STM32MP15x
  79 #define STM32_DBGMCU_BASE               0x50081000
  80 #endif
  81 #define STM32_FMC2_BASE                 0x58002000
  82 #define STM32_IWDG2_BASE                0x5A002000
  83 #define STM32_DDRCTRL_BASE              0x5A003000
  84 #define STM32_DDRPHYC_BASE              0x5A004000
  85 #define STM32_IWDG1_BASE                0x5C003000
  86 #define STM32_TZC_BASE                  0x5C006000
  87 #define STM32_ETZPC_BASE                0x5C007000
  88 #define STM32_STGEN_BASE                0x5C008000
  89 #define STM32_TAMP_BASE                 0x5C00A000
  90
  91 #ifdef CONFIG_STM32MP15x
  92 #define STM32_USART1_BASE               0x5C000000
  93 #define STM32_USART2_BASE               0x4000E000
  94 #endif
  95 #ifdef CONFIG_STM32MP13x
  96 #define STM32_USART1_BASE               0x4c000000
  97 #define STM32_USART2_BASE               0x4c001000
  98 #endif
  99 #define STM32_USART3_BASE               0x4000F000
 100 #define STM32_UART4_BASE                0x40010000
 101 #define STM32_UART5_BASE                0x40011000
 102 #define STM32_USART6_BASE               0x44003000
 103 #define STM32_UART7_BASE                0x40018000
 104 #define STM32_UART8_BASE                0x40019000
 105
 106 #define STM32_SDMMC1_BASE               0x58005000
 107 #define STM32_SDMMC2_BASE               0x58007000
 108 #define STM32_SDMMC3_BASE               0x48004000
 109
 110 #ifdef CONFIG_STM32MP15x
 111 #define STM32_SYSRAM_BASE               0x2FFC0000
 112 #define STM32_SYSRAM_SIZE               SZ_256K
 113 #endif
 114
 115 #define STM32_DDR_BASE                  0xC0000000
 116 #define STM32_DDR_SIZE                  SZ_1G
 117
 118 #ifndef __ASSEMBLY__
 119 /*
 120  * enumerated for boot interface from Bootrom, used in TAMP_BOOT_CONTEXT
 121  * - boot device = bit 8:4
 122  * - boot instance = bit 3:0
 123  */
 124 #define BOOT_TYPE_MASK          0xF0
 125 #define BOOT_TYPE_SHIFT         4
 126 #define BOOT_INSTANCE_MASK      0x0F
 127 #define BOOT_INSTANCE_SHIFT     0
 128
 129 /* TAMP registers */
 130 #define TAMP_BACKUP_REGISTER(x)         (STM32_TAMP_BASE + 0x100 + 4 * x)
 131
 132 #ifdef CONFIG_STM32MP15x
 133 #define TAMP_BACKUP_MAGIC_NUMBER        TAMP_BACKUP_REGISTER(4)
 134 #define TAMP_BACKUP_BRANCH_ADDRESS      TAMP_BACKUP_REGISTER(5)
 135 #define TAMP_FWU_BOOT_INFO_REG          TAMP_BACKUP_REGISTER(10)
 136 #define TAMP_COPRO_RSC_TBL_ADDRESS      TAMP_BACKUP_REGISTER(17)
 137 #define TAMP_COPRO_STATE                TAMP_BACKUP_REGISTER(18)
 138 #define TAMP_BOOT_CONTEXT               TAMP_BACKUP_REGISTER(20)
 139 #define TAMP_BOOTCOUNT                  TAMP_BACKUP_REGISTER(21)
 140
 141 #define TAMP_FWU_BOOT_IDX_MASK          GENMASK(3, 0)
 142
 143 #define TAMP_FWU_BOOT_IDX_OFFSET        0
 144 #define TAMP_COPRO_STATE_OFF            0
 145 #define TAMP_COPRO_STATE_INIT           1
 146 #define TAMP_COPRO_STATE_CRUN           2
 147 #define TAMP_COPRO_STATE_CSTOP          3
 148 #define TAMP_COPRO_STATE_STANDBY        4
 149 #define TAMP_COPRO_STATE_CRASH          5
 150 #endif
 151
 152 #ifdef CONFIG_STM32MP13x
 153 #define TAMP_BOOTCOUNT                  TAMP_BACKUP_REGISTER(31)
 154 #define TAMP_BOOT_CONTEXT               TAMP_BACKUP_REGISTER(30)
 155 #endif
 156
 157 #endif /* __ASSEMBLY__ */
 158 #endif /* CONFIG_STM32MP15X || CONFIG_STM32MP13X */
 159
 160 #if CONFIG_STM32MP25X
 161 #define STM32_RCC_BASE                  0x44200000
 162 #define STM32_TAMP_BASE                 0x46010000
 163
 164 #define STM32_DDR_BASE                  0x80000000
 165
 166 #define STM32_DDR_SIZE                  SZ_4G
 167
 168 /* TAMP registers x = 0 to 127 : hardcoded description, waiting NVMEM node in DT */
 169 #define TAMP_BACKUP_REGISTER(x)         (STM32_TAMP_BASE + 0x100 + 4 * (x))
 170
 171 /* TAMP registers zone 3 RIF 1 (RW) at 96*/
 172 #define TAMP_BOOT_CONTEXT               TAMP_BACKUP_REGISTER(96)
 173 #endif /* STM32MP25X */
 174
 175 /* offset used for BSEC driver: misc_read and misc_write */
 176 #define STM32_BSEC_SHADOW_OFFSET        0x0
 177 #define STM32_BSEC_SHADOW(id)           (STM32_BSEC_SHADOW_OFFSET + (id) * 4)
 178 #define STM32_BSEC_OTP_OFFSET           0x80000000
 179 #define STM32_BSEC_OTP(id)              (STM32_BSEC_OTP_OFFSET + (id) * 4)
 180 #define STM32_BSEC_LOCK_OFFSET          0xC0000000
 181 #define STM32_BSEC_LOCK(id)             (STM32_BSEC_LOCK_OFFSET + (id) * 4)
 182
 183 /* BSEC OTP index */
 184 #ifdef CONFIG_STM32MP15x
 185 #define BSEC_OTP_RPN    1
 186 #define BSEC_OTP_SERIAL 13
 187 #define BSEC_OTP_PKG    16
 188 #define BSEC_OTP_MAC    57
 189 #define BSEC_OTP_BOARD  59
 190 #endif
 191 #ifdef CONFIG_STM32MP13x
 192 #define BSEC_OTP_RPN    1
 193 #define BSEC_OTP_SERIAL 13
 194 #define BSEC_OTP_MAC    57
 195 #define BSEC_OTP_BOARD  60
 196 #endif
 197 #ifdef CONFIG_STM32MP25X
 198 #define BSEC_OTP_SERIAL 5
 199 #define BSEC_OTP_RPN    9
 200 #define BSEC_OTP_PKG    246
 201 #endif
 202
 203 #ifndef __ASSEMBLY__
 204 #include <asm/types.h>
 205
 206 /* enumerated used to identify the SYSCON driver instance */
 207 enum {
 208         STM32MP_SYSCON_UNKNOWN,
 209         STM32MP_SYSCON_SYSCFG,
 210 };
 211 #endif /* __ASSEMBLY__*/
 212
 213 #endif /* _MACH_STM32_H_ */