2 * arch/arm/mach-spear3xx/spear320.c
4 * SPEAr320 machine source file
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
14 #include <linux/ptrace.h>
16 #include <plat/shirq.h>
17 #include <mach/generic.h>
18 #include <mach/hardware.h>
19 #include <mach/spear.h>
21 /* pad multiplexing support */
22 /* muxing registers */
23 #define PAD_MUX_CONFIG_REG 0x0C
24 #define MODE_CONFIG_REG 0x10
27 #define AUTO_NET_SMII_MODE (1 << 0)
28 #define AUTO_NET_MII_MODE (1 << 1)
29 #define AUTO_EXP_MODE (1 << 2)
30 #define SMALL_PRINTERS_MODE (1 << 3)
33 struct pmx_mode spear320_auto_net_smii_mode = {
34 .id = AUTO_NET_SMII_MODE,
35 .name = "Automation Networking SMII Mode",
39 struct pmx_mode spear320_auto_net_mii_mode = {
40 .id = AUTO_NET_MII_MODE,
41 .name = "Automation Networking MII Mode",
45 struct pmx_mode spear320_auto_exp_mode = {
47 .name = "Automation Expanded Mode",
51 struct pmx_mode spear320_small_printers_mode = {
52 .id = SMALL_PRINTERS_MODE,
53 .name = "Small Printers Mode",
58 static struct pmx_dev_mode pmx_clcd_modes[] = {
60 .ids = AUTO_NET_SMII_MODE,
65 struct pmx_dev spear320_pmx_clcd = {
67 .modes = pmx_clcd_modes,
68 .mode_count = ARRAY_SIZE(pmx_clcd_modes),
72 static struct pmx_dev_mode pmx_emi_modes[] = {
75 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
79 struct pmx_dev spear320_pmx_emi = {
81 .modes = pmx_emi_modes,
82 .mode_count = ARRAY_SIZE(pmx_emi_modes),
86 static struct pmx_dev_mode pmx_fsmc_modes[] = {
93 struct pmx_dev spear320_pmx_fsmc = {
95 .modes = pmx_fsmc_modes,
96 .mode_count = ARRAY_SIZE(pmx_fsmc_modes),
100 static struct pmx_dev_mode pmx_spp_modes[] = {
102 .ids = SMALL_PRINTERS_MODE,
107 struct pmx_dev spear320_pmx_spp = {
109 .modes = pmx_spp_modes,
110 .mode_count = ARRAY_SIZE(pmx_spp_modes),
114 static struct pmx_dev_mode pmx_sdhci_modes[] = {
116 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE |
118 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
122 struct pmx_dev spear320_pmx_sdhci = {
124 .modes = pmx_sdhci_modes,
125 .mode_count = ARRAY_SIZE(pmx_sdhci_modes),
129 static struct pmx_dev_mode pmx_i2s_modes[] = {
131 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
132 .mask = PMX_UART0_MODEM_MASK,
136 struct pmx_dev spear320_pmx_i2s = {
138 .modes = pmx_i2s_modes,
139 .mode_count = ARRAY_SIZE(pmx_i2s_modes),
143 static struct pmx_dev_mode pmx_uart1_modes[] = {
146 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
150 struct pmx_dev spear320_pmx_uart1 = {
152 .modes = pmx_uart1_modes,
153 .mode_count = ARRAY_SIZE(pmx_uart1_modes),
157 static struct pmx_dev_mode pmx_uart1_modem_modes[] = {
159 .ids = AUTO_EXP_MODE,
160 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK |
163 .ids = SMALL_PRINTERS_MODE,
164 .mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK |
165 PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK,
169 struct pmx_dev spear320_pmx_uart1_modem = {
170 .name = "uart1_modem",
171 .modes = pmx_uart1_modem_modes,
172 .mode_count = ARRAY_SIZE(pmx_uart1_modem_modes),
176 static struct pmx_dev_mode pmx_uart2_modes[] = {
179 .mask = PMX_FIRDA_MASK,
183 struct pmx_dev spear320_pmx_uart2 = {
185 .modes = pmx_uart2_modes,
186 .mode_count = ARRAY_SIZE(pmx_uart2_modes),
190 static struct pmx_dev_mode pmx_touchscreen_modes[] = {
192 .ids = AUTO_NET_SMII_MODE,
193 .mask = PMX_SSP_CS_MASK,
197 struct pmx_dev spear320_pmx_touchscreen = {
198 .name = "touchscreen",
199 .modes = pmx_touchscreen_modes,
200 .mode_count = ARRAY_SIZE(pmx_touchscreen_modes),
204 static struct pmx_dev_mode pmx_can_modes[] = {
206 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE,
207 .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
208 PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
212 struct pmx_dev spear320_pmx_can = {
214 .modes = pmx_can_modes,
215 .mode_count = ARRAY_SIZE(pmx_can_modes),
219 static struct pmx_dev_mode pmx_sdhci_led_modes[] = {
221 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
222 .mask = PMX_SSP_CS_MASK,
226 struct pmx_dev spear320_pmx_sdhci_led = {
228 .modes = pmx_sdhci_led_modes,
229 .mode_count = ARRAY_SIZE(pmx_sdhci_led_modes),
233 static struct pmx_dev_mode pmx_pwm0_modes[] = {
235 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
236 .mask = PMX_UART0_MODEM_MASK,
238 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
239 .mask = PMX_MII_MASK,
243 struct pmx_dev spear320_pmx_pwm0 = {
245 .modes = pmx_pwm0_modes,
246 .mode_count = ARRAY_SIZE(pmx_pwm0_modes),
250 static struct pmx_dev_mode pmx_pwm1_modes[] = {
252 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
253 .mask = PMX_UART0_MODEM_MASK,
255 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
256 .mask = PMX_MII_MASK,
260 struct pmx_dev spear320_pmx_pwm1 = {
262 .modes = pmx_pwm1_modes,
263 .mode_count = ARRAY_SIZE(pmx_pwm1_modes),
267 static struct pmx_dev_mode pmx_pwm2_modes[] = {
269 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
270 .mask = PMX_SSP_CS_MASK,
272 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
273 .mask = PMX_MII_MASK,
277 struct pmx_dev spear320_pmx_pwm2 = {
279 .modes = pmx_pwm2_modes,
280 .mode_count = ARRAY_SIZE(pmx_pwm2_modes),
284 static struct pmx_dev_mode pmx_pwm3_modes[] = {
286 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
287 .mask = PMX_MII_MASK,
291 struct pmx_dev spear320_pmx_pwm3 = {
293 .modes = pmx_pwm3_modes,
294 .mode_count = ARRAY_SIZE(pmx_pwm3_modes),
298 static struct pmx_dev_mode pmx_ssp1_modes[] = {
300 .ids = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
301 .mask = PMX_MII_MASK,
305 struct pmx_dev spear320_pmx_ssp1 = {
307 .modes = pmx_ssp1_modes,
308 .mode_count = ARRAY_SIZE(pmx_ssp1_modes),
312 static struct pmx_dev_mode pmx_ssp2_modes[] = {
314 .ids = AUTO_NET_SMII_MODE,
315 .mask = PMX_MII_MASK,
319 struct pmx_dev spear320_pmx_ssp2 = {
321 .modes = pmx_ssp2_modes,
322 .mode_count = ARRAY_SIZE(pmx_ssp2_modes),
326 static struct pmx_dev_mode pmx_mii1_modes[] = {
328 .ids = AUTO_NET_MII_MODE,
333 struct pmx_dev spear320_pmx_mii1 = {
335 .modes = pmx_mii1_modes,
336 .mode_count = ARRAY_SIZE(pmx_mii1_modes),
340 static struct pmx_dev_mode pmx_smii0_modes[] = {
342 .ids = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
343 .mask = PMX_MII_MASK,
347 struct pmx_dev spear320_pmx_smii0 = {
349 .modes = pmx_smii0_modes,
350 .mode_count = ARRAY_SIZE(pmx_smii0_modes),
354 static struct pmx_dev_mode pmx_smii1_modes[] = {
356 .ids = AUTO_NET_SMII_MODE | SMALL_PRINTERS_MODE,
357 .mask = PMX_MII_MASK,
361 struct pmx_dev spear320_pmx_smii1 = {
363 .modes = pmx_smii1_modes,
364 .mode_count = ARRAY_SIZE(pmx_smii1_modes),
368 static struct pmx_dev_mode pmx_i2c1_modes[] = {
370 .ids = AUTO_EXP_MODE,
375 struct pmx_dev spear320_pmx_i2c1 = {
377 .modes = pmx_i2c1_modes,
378 .mode_count = ARRAY_SIZE(pmx_i2c1_modes),
382 /* pmx driver structure */
383 static struct pmx_driver pmx_driver = {
384 .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x00000007},
385 .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
388 /* spear3xx shared irq */
389 static struct shirq_dev_config shirq_ras1_config[] = {
391 .virq = SPEAR320_VIRQ_EMI,
392 .status_mask = SPEAR320_EMI_IRQ_MASK,
393 .clear_mask = SPEAR320_EMI_IRQ_MASK,
395 .virq = SPEAR320_VIRQ_CLCD,
396 .status_mask = SPEAR320_CLCD_IRQ_MASK,
397 .clear_mask = SPEAR320_CLCD_IRQ_MASK,
399 .virq = SPEAR320_VIRQ_SPP,
400 .status_mask = SPEAR320_SPP_IRQ_MASK,
401 .clear_mask = SPEAR320_SPP_IRQ_MASK,
405 static struct spear_shirq shirq_ras1 = {
406 .irq = SPEAR3XX_IRQ_GEN_RAS_1,
407 .dev_config = shirq_ras1_config,
408 .dev_count = ARRAY_SIZE(shirq_ras1_config),
411 .status_reg = SPEAR320_INT_STS_MASK_REG,
412 .status_reg_mask = SPEAR320_SHIRQ_RAS1_MASK,
413 .clear_reg = SPEAR320_INT_CLR_MASK_REG,
418 static struct shirq_dev_config shirq_ras3_config[] = {
420 .virq = SPEAR320_VIRQ_PLGPIO,
421 .enb_mask = SPEAR320_GPIO_IRQ_MASK,
422 .status_mask = SPEAR320_GPIO_IRQ_MASK,
423 .clear_mask = SPEAR320_GPIO_IRQ_MASK,
425 .virq = SPEAR320_VIRQ_I2S_PLAY,
426 .enb_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
427 .status_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
428 .clear_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
430 .virq = SPEAR320_VIRQ_I2S_REC,
431 .enb_mask = SPEAR320_I2S_REC_IRQ_MASK,
432 .status_mask = SPEAR320_I2S_REC_IRQ_MASK,
433 .clear_mask = SPEAR320_I2S_REC_IRQ_MASK,
437 static struct spear_shirq shirq_ras3 = {
438 .irq = SPEAR3XX_IRQ_GEN_RAS_3,
439 .dev_config = shirq_ras3_config,
440 .dev_count = ARRAY_SIZE(shirq_ras3_config),
442 .enb_reg = SPEAR320_INT_ENB_MASK_REG,
444 .status_reg = SPEAR320_INT_STS_MASK_REG,
445 .status_reg_mask = SPEAR320_SHIRQ_RAS3_MASK,
446 .clear_reg = SPEAR320_INT_CLR_MASK_REG,
451 static struct shirq_dev_config shirq_intrcomm_ras_config[] = {
453 .virq = SPEAR320_VIRQ_CANU,
454 .status_mask = SPEAR320_CAN_U_IRQ_MASK,
455 .clear_mask = SPEAR320_CAN_U_IRQ_MASK,
457 .virq = SPEAR320_VIRQ_CANL,
458 .status_mask = SPEAR320_CAN_L_IRQ_MASK,
459 .clear_mask = SPEAR320_CAN_L_IRQ_MASK,
461 .virq = SPEAR320_VIRQ_UART1,
462 .status_mask = SPEAR320_UART1_IRQ_MASK,
463 .clear_mask = SPEAR320_UART1_IRQ_MASK,
465 .virq = SPEAR320_VIRQ_UART2,
466 .status_mask = SPEAR320_UART2_IRQ_MASK,
467 .clear_mask = SPEAR320_UART2_IRQ_MASK,
469 .virq = SPEAR320_VIRQ_SSP1,
470 .status_mask = SPEAR320_SSP1_IRQ_MASK,
471 .clear_mask = SPEAR320_SSP1_IRQ_MASK,
473 .virq = SPEAR320_VIRQ_SSP2,
474 .status_mask = SPEAR320_SSP2_IRQ_MASK,
475 .clear_mask = SPEAR320_SSP2_IRQ_MASK,
477 .virq = SPEAR320_VIRQ_SMII0,
478 .status_mask = SPEAR320_SMII0_IRQ_MASK,
479 .clear_mask = SPEAR320_SMII0_IRQ_MASK,
481 .virq = SPEAR320_VIRQ_MII1_SMII1,
482 .status_mask = SPEAR320_MII1_SMII1_IRQ_MASK,
483 .clear_mask = SPEAR320_MII1_SMII1_IRQ_MASK,
485 .virq = SPEAR320_VIRQ_WAKEUP_SMII0,
486 .status_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK,
487 .clear_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK,
489 .virq = SPEAR320_VIRQ_WAKEUP_MII1_SMII1,
490 .status_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK,
491 .clear_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK,
493 .virq = SPEAR320_VIRQ_I2C1,
494 .status_mask = SPEAR320_I2C1_IRQ_MASK,
495 .clear_mask = SPEAR320_I2C1_IRQ_MASK,
499 static struct spear_shirq shirq_intrcomm_ras = {
500 .irq = SPEAR3XX_IRQ_INTRCOMM_RAS_ARM,
501 .dev_config = shirq_intrcomm_ras_config,
502 .dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
505 .status_reg = SPEAR320_INT_STS_MASK_REG,
506 .status_reg_mask = SPEAR320_SHIRQ_INTRCOMM_RAS_MASK,
507 .clear_reg = SPEAR320_INT_CLR_MASK_REG,
512 /* Add spear320 specific devices here */
514 /* spear320 routines */
515 void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
521 /* call spear3xx family common init function */
524 /* shared irq registration */
525 base = ioremap(SPEAR320_SOC_CONFIG_BASE, SZ_4K);
528 shirq_ras1.regs.base = base;
529 ret = spear_shirq_register(&shirq_ras1);
531 printk(KERN_ERR "Error registering Shared IRQ 1\n");
534 shirq_ras3.regs.base = base;
535 ret = spear_shirq_register(&shirq_ras3);
537 printk(KERN_ERR "Error registering Shared IRQ 3\n");
540 shirq_intrcomm_ras.regs.base = base;
541 ret = spear_shirq_register(&shirq_intrcomm_ras);
543 printk(KERN_ERR "Error registering Shared IRQ 4\n");
546 /* pmx initialization */
547 pmx_driver.base = base;
548 pmx_driver.mode = pmx_mode;
549 pmx_driver.devs = pmx_devs;
550 pmx_driver.devs_count = pmx_dev_count;
552 ret = pmx_register(&pmx_driver);
554 printk(KERN_ERR "padmux: registration failed. err no: %d\n",