arch/arm/mach-socfpga/spl_s10.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
   4  *
   5  */
   6
   7 #include <hang.h>
   8 #include <init.h>
   9 #include <asm/io.h>
  10 #include <asm/u-boot.h>
  11 #include <asm/utils.h>
  12 #include <common.h>
  13 #include <debug_uart.h>
  14 #include <image.h>
  15 #include <spl.h>
  16 #include <asm/arch/clock_manager.h>
  17 #include <asm/arch/firewall.h>
  18 #include <asm/arch/mailbox_s10.h>
  19 #include <asm/arch/misc.h>
  20 #include <asm/arch/reset_manager.h>
  21 #include <asm/arch/system_manager.h>
  22 #include <watchdog.h>
  23 #include <dm/uclass.h>
  24
  25 DECLARE_GLOBAL_DATA_PTR;
  26
  27 u32 spl_boot_device(void)
  28 {
  29         /* TODO: Get from SDM or handoff */
  30         return BOOT_DEVICE_MMC1;
  31 }
  32
  33 #ifdef CONFIG_SPL_MMC_SUPPORT
  34 u32 spl_mmc_boot_mode(const u32 boot_device)
  35 {
  36 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
  37         return MMCSD_MODE_FS;
  38 #else
  39         return MMCSD_MODE_RAW;
  40 #endif
  41 }
  42 #endif
  43
  44 void board_init_f(ulong dummy)
  45 {
  46         const struct cm_config *cm_default_cfg = cm_get_default_config();
  47         int ret;
  48
  49         ret = spl_early_init();
  50         if (ret)
  51                 hang();
  52
  53         socfpga_get_managers_addr();
  54
  55 #ifdef CONFIG_HW_WATCHDOG
  56         /* Ensure watchdog is paused when debugging is happening */
  57         writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,
  58                socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG);
  59
  60         /* Enable watchdog before initializing the HW */
  61         socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
  62         socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
  63         hw_watchdog_init();
  64 #endif
  65
  66         /* ensure all processors are not released prior Linux boot */
  67         writeq(0, CPU_RELEASE_ADDR);
  68
  69         socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
  70         timer_init();
  71
  72         sysmgr_pinmux_init();
  73
  74         /* configuring the HPS clocks */
  75         cm_basic_init(cm_default_cfg);
  76
  77 #ifdef CONFIG_DEBUG_UART
  78         socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
  79         debug_uart_init();
  80 #endif
  81
  82         preloader_console_init();
  83         cm_print_clock_quick_summary();
  84
  85         firewall_setup();
  86
  87         /* disable ocram security at CCU for non secure access */
  88         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADMASK_MEM_RAM0),
  89                      CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
  90         clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADMASK_MEM_RAM0),
  91                      CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
  92
  93 #if CONFIG_IS_ENABLED(ALTERA_SDRAM)
  94                 struct udevice *dev;
  95
  96                 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
  97                 if (ret) {
  98                         debug("DRAM init failed: %d\n", ret);
  99                         hang();
 100                 }
 101 #endif
 102
 103         mbox_init();
 104
 105 #ifdef CONFIG_CADENCE_QSPI
 106         mbox_qspi_open();
 107 #endif
 108 }