1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019 Intel Corporation <www.intel.com>
9 #include <asm/u-boot.h>
10 #include <asm/utils.h>
15 #include <asm/arch/clock_manager.h>
16 #include <asm/arch/firewall.h>
17 #include <asm/arch/mailbox_s10.h>
18 #include <asm/arch/misc.h>
19 #include <asm/arch/reset_manager.h>
20 #include <asm/arch/system_manager.h>
22 #include <dm/uclass.h>
24 DECLARE_GLOBAL_DATA_PTR;
26 u32 spl_boot_device(void)
28 return BOOT_DEVICE_MMC1;
31 #ifdef CONFIG_SPL_MMC_SUPPORT
32 u32 spl_mmc_boot_mode(const u32 boot_device)
34 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
37 return MMCSD_MODE_RAW;
42 void board_init_f(ulong dummy)
47 ret = spl_early_init();
51 socfpga_get_managers_addr();
53 #ifdef CONFIG_HW_WATCHDOG
54 /* Ensure watchdog is paused when debugging is happening */
55 writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,
56 socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG);
58 /* Enable watchdog before initializing the HW */
59 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
60 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
64 /* ensure all processors are not released prior Linux boot */
65 writeq(0, CPU_RELEASE_ADDR);
71 ret = uclass_get_device(UCLASS_CLK, 0, &dev);
73 debug("Clock init failed: %d\n", ret);
77 preloader_console_init();
78 cm_print_clock_quick_summary();
81 ret = uclass_get_device(UCLASS_CACHE, 0, &dev);
83 debug("CCU init failed: %d\n", ret);
87 #if CONFIG_IS_ENABLED(ALTERA_SDRAM)
88 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
90 debug("DRAM init failed: %d\n", ret);
97 #ifdef CONFIG_CADENCE_QSPI