2 * sh73a0 processor support
4 * Copyright (C) 2010 Takashi Yoshii
5 * Copyright (C) 2010 Magnus Damm
6 * Copyright (C) 2008 Yoshihiro Shimoda
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/interrupt.h>
24 #include <linux/irq.h>
25 #include <linux/platform_device.h>
26 #include <linux/of_platform.h>
27 #include <linux/delay.h>
28 #include <linux/input.h>
30 #include <linux/serial_sci.h>
31 #include <linux/sh_dma.h>
32 #include <linux/sh_intc.h>
33 #include <linux/sh_timer.h>
34 #include <mach/dma-register.h>
35 #include <mach/hardware.h>
36 #include <mach/irqs.h>
37 #include <mach/sh73a0.h>
38 #include <mach/common.h>
39 #include <asm/mach-types.h>
40 #include <asm/mach/map.h>
41 #include <asm/mach/arch.h>
42 #include <asm/mach/time.h>
44 static struct map_desc sh73a0_io_desc[] __initdata = {
45 /* create a 1:1 entity map for 0xe6xxxxxx
46 * used by CPGA, INTC and PFC.
49 .virtual = 0xe6000000,
50 .pfn = __phys_to_pfn(0xe6000000),
52 .type = MT_DEVICE_NONSHARED
56 void __init sh73a0_map_io(void)
58 iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc));
61 static struct resource sh73a0_pfc_resources[] = {
65 .flags = IORESOURCE_MEM,
70 .flags = IORESOURCE_MEM,
74 static struct platform_device sh73a0_pfc_device = {
77 .resource = sh73a0_pfc_resources,
78 .num_resources = ARRAY_SIZE(sh73a0_pfc_resources),
81 void __init sh73a0_pinmux_init(void)
83 platform_device_register(&sh73a0_pfc_device);
86 static struct plat_sci_port scif0_platform_data = {
87 .mapbase = 0xe6c40000,
88 .flags = UPF_BOOT_AUTOCONF,
89 .scscr = SCSCR_RE | SCSCR_TE,
90 .scbrr_algo_id = SCBRR_ALGO_4,
92 .irqs = { gic_spi(72), gic_spi(72),
93 gic_spi(72), gic_spi(72) },
96 static struct platform_device scif0_device = {
100 .platform_data = &scif0_platform_data,
104 static struct plat_sci_port scif1_platform_data = {
105 .mapbase = 0xe6c50000,
106 .flags = UPF_BOOT_AUTOCONF,
107 .scscr = SCSCR_RE | SCSCR_TE,
108 .scbrr_algo_id = SCBRR_ALGO_4,
110 .irqs = { gic_spi(73), gic_spi(73),
111 gic_spi(73), gic_spi(73) },
114 static struct platform_device scif1_device = {
118 .platform_data = &scif1_platform_data,
122 static struct plat_sci_port scif2_platform_data = {
123 .mapbase = 0xe6c60000,
124 .flags = UPF_BOOT_AUTOCONF,
125 .scscr = SCSCR_RE | SCSCR_TE,
126 .scbrr_algo_id = SCBRR_ALGO_4,
128 .irqs = { gic_spi(74), gic_spi(74),
129 gic_spi(74), gic_spi(74) },
132 static struct platform_device scif2_device = {
136 .platform_data = &scif2_platform_data,
140 static struct plat_sci_port scif3_platform_data = {
141 .mapbase = 0xe6c70000,
142 .flags = UPF_BOOT_AUTOCONF,
143 .scscr = SCSCR_RE | SCSCR_TE,
144 .scbrr_algo_id = SCBRR_ALGO_4,
146 .irqs = { gic_spi(75), gic_spi(75),
147 gic_spi(75), gic_spi(75) },
150 static struct platform_device scif3_device = {
154 .platform_data = &scif3_platform_data,
158 static struct plat_sci_port scif4_platform_data = {
159 .mapbase = 0xe6c80000,
160 .flags = UPF_BOOT_AUTOCONF,
161 .scscr = SCSCR_RE | SCSCR_TE,
162 .scbrr_algo_id = SCBRR_ALGO_4,
164 .irqs = { gic_spi(78), gic_spi(78),
165 gic_spi(78), gic_spi(78) },
168 static struct platform_device scif4_device = {
172 .platform_data = &scif4_platform_data,
176 static struct plat_sci_port scif5_platform_data = {
177 .mapbase = 0xe6cb0000,
178 .flags = UPF_BOOT_AUTOCONF,
179 .scscr = SCSCR_RE | SCSCR_TE,
180 .scbrr_algo_id = SCBRR_ALGO_4,
182 .irqs = { gic_spi(79), gic_spi(79),
183 gic_spi(79), gic_spi(79) },
186 static struct platform_device scif5_device = {
190 .platform_data = &scif5_platform_data,
194 static struct plat_sci_port scif6_platform_data = {
195 .mapbase = 0xe6cc0000,
196 .flags = UPF_BOOT_AUTOCONF,
197 .scscr = SCSCR_RE | SCSCR_TE,
198 .scbrr_algo_id = SCBRR_ALGO_4,
200 .irqs = { gic_spi(156), gic_spi(156),
201 gic_spi(156), gic_spi(156) },
204 static struct platform_device scif6_device = {
208 .platform_data = &scif6_platform_data,
212 static struct plat_sci_port scif7_platform_data = {
213 .mapbase = 0xe6cd0000,
214 .flags = UPF_BOOT_AUTOCONF,
215 .scscr = SCSCR_RE | SCSCR_TE,
216 .scbrr_algo_id = SCBRR_ALGO_4,
218 .irqs = { gic_spi(143), gic_spi(143),
219 gic_spi(143), gic_spi(143) },
222 static struct platform_device scif7_device = {
226 .platform_data = &scif7_platform_data,
230 static struct plat_sci_port scif8_platform_data = {
231 .mapbase = 0xe6c30000,
232 .flags = UPF_BOOT_AUTOCONF,
233 .scscr = SCSCR_RE | SCSCR_TE,
234 .scbrr_algo_id = SCBRR_ALGO_4,
236 .irqs = { gic_spi(80), gic_spi(80),
237 gic_spi(80), gic_spi(80) },
240 static struct platform_device scif8_device = {
244 .platform_data = &scif8_platform_data,
248 static struct sh_timer_config cmt10_platform_data = {
250 .channel_offset = 0x10,
252 .clockevent_rating = 125,
253 .clocksource_rating = 125,
256 static struct resource cmt10_resources[] = {
261 .flags = IORESOURCE_MEM,
264 .start = gic_spi(65),
265 .flags = IORESOURCE_IRQ,
269 static struct platform_device cmt10_device = {
273 .platform_data = &cmt10_platform_data,
275 .resource = cmt10_resources,
276 .num_resources = ARRAY_SIZE(cmt10_resources),
280 static struct sh_timer_config tmu00_platform_data = {
282 .channel_offset = 0x4,
284 .clockevent_rating = 200,
287 static struct resource tmu00_resources[] = {
292 .flags = IORESOURCE_MEM,
295 .start = intcs_evt2irq(0x0e80), /* TMU0_TUNI00 */
296 .flags = IORESOURCE_IRQ,
300 static struct platform_device tmu00_device = {
304 .platform_data = &tmu00_platform_data,
306 .resource = tmu00_resources,
307 .num_resources = ARRAY_SIZE(tmu00_resources),
310 static struct sh_timer_config tmu01_platform_data = {
312 .channel_offset = 0x10,
314 .clocksource_rating = 200,
317 static struct resource tmu01_resources[] = {
322 .flags = IORESOURCE_MEM,
325 .start = intcs_evt2irq(0x0ea0), /* TMU0_TUNI01 */
326 .flags = IORESOURCE_IRQ,
330 static struct platform_device tmu01_device = {
334 .platform_data = &tmu01_platform_data,
336 .resource = tmu01_resources,
337 .num_resources = ARRAY_SIZE(tmu01_resources),
340 static struct resource i2c0_resources[] = {
344 .end = 0xe6820425 - 1,
345 .flags = IORESOURCE_MEM,
348 .start = gic_spi(167),
350 .flags = IORESOURCE_IRQ,
354 static struct resource i2c1_resources[] = {
358 .end = 0xe6822425 - 1,
359 .flags = IORESOURCE_MEM,
362 .start = gic_spi(51),
364 .flags = IORESOURCE_IRQ,
368 static struct resource i2c2_resources[] = {
372 .end = 0xe6824425 - 1,
373 .flags = IORESOURCE_MEM,
376 .start = gic_spi(171),
378 .flags = IORESOURCE_IRQ,
382 static struct resource i2c3_resources[] = {
386 .end = 0xe6826425 - 1,
387 .flags = IORESOURCE_MEM,
390 .start = gic_spi(183),
392 .flags = IORESOURCE_IRQ,
396 static struct resource i2c4_resources[] = {
400 .end = 0xe6828425 - 1,
401 .flags = IORESOURCE_MEM,
404 .start = gic_spi(187),
406 .flags = IORESOURCE_IRQ,
410 static struct platform_device i2c0_device = {
411 .name = "i2c-sh_mobile",
413 .resource = i2c0_resources,
414 .num_resources = ARRAY_SIZE(i2c0_resources),
417 static struct platform_device i2c1_device = {
418 .name = "i2c-sh_mobile",
420 .resource = i2c1_resources,
421 .num_resources = ARRAY_SIZE(i2c1_resources),
424 static struct platform_device i2c2_device = {
425 .name = "i2c-sh_mobile",
427 .resource = i2c2_resources,
428 .num_resources = ARRAY_SIZE(i2c2_resources),
431 static struct platform_device i2c3_device = {
432 .name = "i2c-sh_mobile",
434 .resource = i2c3_resources,
435 .num_resources = ARRAY_SIZE(i2c3_resources),
438 static struct platform_device i2c4_device = {
439 .name = "i2c-sh_mobile",
441 .resource = i2c4_resources,
442 .num_resources = ARRAY_SIZE(i2c4_resources),
445 static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = {
447 .slave_id = SHDMA_SLAVE_SCIF0_TX,
449 .chcr = CHCR_TX(XMIT_SZ_8BIT),
452 .slave_id = SHDMA_SLAVE_SCIF0_RX,
454 .chcr = CHCR_RX(XMIT_SZ_8BIT),
457 .slave_id = SHDMA_SLAVE_SCIF1_TX,
459 .chcr = CHCR_TX(XMIT_SZ_8BIT),
462 .slave_id = SHDMA_SLAVE_SCIF1_RX,
464 .chcr = CHCR_RX(XMIT_SZ_8BIT),
467 .slave_id = SHDMA_SLAVE_SCIF2_TX,
469 .chcr = CHCR_TX(XMIT_SZ_8BIT),
472 .slave_id = SHDMA_SLAVE_SCIF2_RX,
474 .chcr = CHCR_RX(XMIT_SZ_8BIT),
477 .slave_id = SHDMA_SLAVE_SCIF3_TX,
479 .chcr = CHCR_TX(XMIT_SZ_8BIT),
482 .slave_id = SHDMA_SLAVE_SCIF3_RX,
484 .chcr = CHCR_RX(XMIT_SZ_8BIT),
487 .slave_id = SHDMA_SLAVE_SCIF4_TX,
489 .chcr = CHCR_TX(XMIT_SZ_8BIT),
492 .slave_id = SHDMA_SLAVE_SCIF4_RX,
494 .chcr = CHCR_RX(XMIT_SZ_8BIT),
497 .slave_id = SHDMA_SLAVE_SCIF5_TX,
499 .chcr = CHCR_TX(XMIT_SZ_8BIT),
502 .slave_id = SHDMA_SLAVE_SCIF5_RX,
504 .chcr = CHCR_RX(XMIT_SZ_8BIT),
507 .slave_id = SHDMA_SLAVE_SCIF6_TX,
509 .chcr = CHCR_TX(XMIT_SZ_8BIT),
512 .slave_id = SHDMA_SLAVE_SCIF6_RX,
514 .chcr = CHCR_RX(XMIT_SZ_8BIT),
517 .slave_id = SHDMA_SLAVE_SCIF7_TX,
519 .chcr = CHCR_TX(XMIT_SZ_8BIT),
522 .slave_id = SHDMA_SLAVE_SCIF7_RX,
524 .chcr = CHCR_RX(XMIT_SZ_8BIT),
527 .slave_id = SHDMA_SLAVE_SCIF8_TX,
529 .chcr = CHCR_TX(XMIT_SZ_8BIT),
532 .slave_id = SHDMA_SLAVE_SCIF8_RX,
534 .chcr = CHCR_RX(XMIT_SZ_8BIT),
537 .slave_id = SHDMA_SLAVE_SDHI0_TX,
539 .chcr = CHCR_TX(XMIT_SZ_16BIT),
542 .slave_id = SHDMA_SLAVE_SDHI0_RX,
544 .chcr = CHCR_RX(XMIT_SZ_16BIT),
547 .slave_id = SHDMA_SLAVE_SDHI1_TX,
549 .chcr = CHCR_TX(XMIT_SZ_16BIT),
552 .slave_id = SHDMA_SLAVE_SDHI1_RX,
554 .chcr = CHCR_RX(XMIT_SZ_16BIT),
557 .slave_id = SHDMA_SLAVE_SDHI2_TX,
559 .chcr = CHCR_TX(XMIT_SZ_16BIT),
562 .slave_id = SHDMA_SLAVE_SDHI2_RX,
564 .chcr = CHCR_RX(XMIT_SZ_16BIT),
567 .slave_id = SHDMA_SLAVE_MMCIF_TX,
569 .chcr = CHCR_TX(XMIT_SZ_32BIT),
572 .slave_id = SHDMA_SLAVE_MMCIF_RX,
574 .chcr = CHCR_RX(XMIT_SZ_32BIT),
579 #define DMAE_CHANNEL(_offset) \
581 .offset = _offset - 0x20, \
582 .dmars = _offset - 0x20 + 0x40, \
585 static const struct sh_dmae_channel sh73a0_dmae_channels[] = {
586 DMAE_CHANNEL(0x8000),
587 DMAE_CHANNEL(0x8080),
588 DMAE_CHANNEL(0x8100),
589 DMAE_CHANNEL(0x8180),
590 DMAE_CHANNEL(0x8200),
591 DMAE_CHANNEL(0x8280),
592 DMAE_CHANNEL(0x8300),
593 DMAE_CHANNEL(0x8380),
594 DMAE_CHANNEL(0x8400),
595 DMAE_CHANNEL(0x8480),
596 DMAE_CHANNEL(0x8500),
597 DMAE_CHANNEL(0x8580),
598 DMAE_CHANNEL(0x8600),
599 DMAE_CHANNEL(0x8680),
600 DMAE_CHANNEL(0x8700),
601 DMAE_CHANNEL(0x8780),
602 DMAE_CHANNEL(0x8800),
603 DMAE_CHANNEL(0x8880),
604 DMAE_CHANNEL(0x8900),
605 DMAE_CHANNEL(0x8980),
608 static struct sh_dmae_pdata sh73a0_dmae_platform_data = {
609 .slave = sh73a0_dmae_slaves,
610 .slave_num = ARRAY_SIZE(sh73a0_dmae_slaves),
611 .channel = sh73a0_dmae_channels,
612 .channel_num = ARRAY_SIZE(sh73a0_dmae_channels),
613 .ts_low_shift = TS_LOW_SHIFT,
614 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
615 .ts_high_shift = TS_HI_SHIFT,
616 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
617 .ts_shift = dma_ts_shift,
618 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
619 .dmaor_init = DMAOR_DME,
622 static struct resource sh73a0_dmae_resources[] = {
624 /* Registers including DMAOR and channels including DMARSx */
626 .end = 0xfe008a00 - 1,
627 .flags = IORESOURCE_MEM,
631 .start = gic_spi(129),
633 .flags = IORESOURCE_IRQ,
636 /* IRQ for channels 0-19 */
637 .start = gic_spi(109),
639 .flags = IORESOURCE_IRQ,
643 static struct platform_device dma0_device = {
644 .name = "sh-dma-engine",
646 .resource = sh73a0_dmae_resources,
647 .num_resources = ARRAY_SIZE(sh73a0_dmae_resources),
649 .platform_data = &sh73a0_dmae_platform_data,
654 static const struct sh_dmae_slave_config sh73a0_mpdma_slaves[] = {
656 .slave_id = SHDMA_SLAVE_FSI2A_RX,
658 .chcr = CHCR_RX(XMIT_SZ_32BIT),
659 .mid_rid = 0xd6, /* CHECK ME */
661 .slave_id = SHDMA_SLAVE_FSI2A_TX,
663 .chcr = CHCR_TX(XMIT_SZ_32BIT),
664 .mid_rid = 0xd5, /* CHECK ME */
666 .slave_id = SHDMA_SLAVE_FSI2C_RX,
668 .chcr = CHCR_RX(XMIT_SZ_32BIT),
669 .mid_rid = 0xda, /* CHECK ME */
671 .slave_id = SHDMA_SLAVE_FSI2C_TX,
673 .chcr = CHCR_TX(XMIT_SZ_32BIT),
674 .mid_rid = 0xd9, /* CHECK ME */
676 .slave_id = SHDMA_SLAVE_FSI2B_RX,
678 .chcr = CHCR_RX(XMIT_SZ_32BIT),
679 .mid_rid = 0x8e, /* CHECK ME */
681 .slave_id = SHDMA_SLAVE_FSI2B_TX,
683 .chcr = CHCR_RX(XMIT_SZ_32BIT),
684 .mid_rid = 0x8d, /* CHECK ME */
686 .slave_id = SHDMA_SLAVE_FSI2D_RX,
688 .chcr = CHCR_RX(XMIT_SZ_32BIT),
689 .mid_rid = 0x9a, /* CHECK ME */
693 #define MPDMA_CHANNEL(a, b, c) \
698 .chclr_offset = (0x220 - 0x20) + a \
701 static const struct sh_dmae_channel sh73a0_mpdma_channels[] = {
702 MPDMA_CHANNEL(0x00, 0, 0),
703 MPDMA_CHANNEL(0x10, 0, 8),
704 MPDMA_CHANNEL(0x20, 4, 0),
705 MPDMA_CHANNEL(0x30, 4, 8),
706 MPDMA_CHANNEL(0x50, 8, 0),
707 MPDMA_CHANNEL(0x70, 8, 8),
710 static struct sh_dmae_pdata sh73a0_mpdma_platform_data = {
711 .slave = sh73a0_mpdma_slaves,
712 .slave_num = ARRAY_SIZE(sh73a0_mpdma_slaves),
713 .channel = sh73a0_mpdma_channels,
714 .channel_num = ARRAY_SIZE(sh73a0_mpdma_channels),
715 .ts_low_shift = TS_LOW_SHIFT,
716 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
717 .ts_high_shift = TS_HI_SHIFT,
718 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
719 .ts_shift = dma_ts_shift,
720 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
721 .dmaor_init = DMAOR_DME,
725 /* Resource order important! */
726 static struct resource sh73a0_mpdma_resources[] = {
728 /* Channel registers and DMAOR */
731 .flags = IORESOURCE_MEM,
737 .flags = IORESOURCE_MEM,
741 .start = gic_spi(181),
743 .flags = IORESOURCE_IRQ,
746 /* IRQ for channels 0-5 */
747 .start = gic_spi(175),
749 .flags = IORESOURCE_IRQ,
753 static struct platform_device mpdma0_device = {
754 .name = "sh-dma-engine",
756 .resource = sh73a0_mpdma_resources,
757 .num_resources = ARRAY_SIZE(sh73a0_mpdma_resources),
759 .platform_data = &sh73a0_mpdma_platform_data,
763 static struct resource pmu_resources[] = {
765 .start = gic_spi(55),
767 .flags = IORESOURCE_IRQ,
770 .start = gic_spi(56),
772 .flags = IORESOURCE_IRQ,
776 static struct platform_device pmu_device = {
779 .num_resources = ARRAY_SIZE(pmu_resources),
780 .resource = pmu_resources,
783 static struct platform_device *sh73a0_early_devices_dt[] __initdata = {
796 static struct platform_device *sh73a0_early_devices[] __initdata = {
801 static struct platform_device *sh73a0_late_devices[] __initdata = {
812 #define SRCR2 IOMEM(0xe61580b0)
814 void __init sh73a0_add_standard_devices(void)
816 /* Clear software reset bit on SY-DMAC module */
817 __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2);
819 platform_add_devices(sh73a0_early_devices_dt,
820 ARRAY_SIZE(sh73a0_early_devices_dt));
821 platform_add_devices(sh73a0_early_devices,
822 ARRAY_SIZE(sh73a0_early_devices));
823 platform_add_devices(sh73a0_late_devices,
824 ARRAY_SIZE(sh73a0_late_devices));
827 /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
828 void __init __weak sh73a0_register_twd(void) { }
830 void __init sh73a0_earlytimer_init(void)
833 shmobile_earlytimer_init();
834 sh73a0_register_twd();
837 void __init sh73a0_add_early_devices(void)
839 early_platform_add_devices(sh73a0_early_devices_dt,
840 ARRAY_SIZE(sh73a0_early_devices_dt));
841 early_platform_add_devices(sh73a0_early_devices,
842 ARRAY_SIZE(sh73a0_early_devices));
844 /* setup early console here as well */
845 shmobile_setup_console();
850 /* Please note that the clock initialisation shcheme used in
851 * sh73a0_add_early_devices_dt() and sh73a0_add_standard_devices_dt()
852 * does not work with SMP as there is a yet to be resolved lock-up in
853 * workqueue initialisation.
855 * CONFIG_SMP should be disabled when using this code.
858 void __init sh73a0_add_early_devices_dt(void)
860 shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */
862 early_platform_add_devices(sh73a0_early_devices_dt,
863 ARRAY_SIZE(sh73a0_early_devices_dt));
865 /* setup early console here as well */
866 shmobile_setup_console();
869 static const struct of_dev_auxdata sh73a0_auxdata_lookup[] __initconst = {
873 void __init sh73a0_add_standard_devices_dt(void)
875 /* clocks are setup late during boot in the case of DT */
878 platform_add_devices(sh73a0_early_devices_dt,
879 ARRAY_SIZE(sh73a0_early_devices_dt));
880 of_platform_populate(NULL, of_default_bus_match_table,
881 sh73a0_auxdata_lookup, NULL);
884 static const char *sh73a0_boards_compat_dt[] __initdata = {
889 DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)")
890 .map_io = sh73a0_map_io,
891 .init_early = sh73a0_add_early_devices_dt,
892 .nr_irqs = NR_IRQS_LEGACY,
893 .init_irq = sh73a0_init_irq_dt,
894 .init_machine = sh73a0_add_standard_devices_dt,
895 .init_time = shmobile_timer_init,
896 .dt_compat = sh73a0_boards_compat_dt,
898 #endif /* CONFIG_USE_OF */