arch/arm/mach-shmobile/setup-sh7377.c

   1 /*
   2  * sh7377 processor support
   3  *
   4  * Copyright (C) 2010  Magnus Damm
   5  * Copyright (C) 2008  Yoshihiro Shimoda
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/irq.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/uio_driver.h>
  26 #include <linux/delay.h>
  27 #include <linux/input.h>
  28 #include <linux/io.h>
  29 #include <linux/serial_sci.h>
  30 #include <linux/sh_intc.h>
  31 #include <linux/sh_timer.h>
  32 #include <mach/hardware.h>
  33 #include <mach/common.h>
  34 #include <asm/mach/map.h>
  35 #include <asm/mach-types.h>
  36 #include <asm/mach/arch.h>
  37 #include <asm/mach/time.h>
  38
  39 static struct map_desc sh7377_io_desc[] __initdata = {
  40         /* create a 1:1 entity map for 0xe6xxxxxx
  41          * used by CPGA, INTC and PFC.
  42          */
  43         {
  44                 .virtual        = 0xe6000000,
  45                 .pfn            = __phys_to_pfn(0xe6000000),
  46                 .length         = 256 << 20,
  47                 .type           = MT_DEVICE_NONSHARED
  48         },
  49 };
  50
  51 void __init sh7377_map_io(void)
  52 {
  53         iotable_init(sh7377_io_desc, ARRAY_SIZE(sh7377_io_desc));
  54 }
  55
  56 /* SCIFA0 */
  57 static struct plat_sci_port scif0_platform_data = {
  58         .mapbase        = 0xe6c40000,
  59         .flags          = UPF_BOOT_AUTOCONF,
  60         .scscr          = SCSCR_RE | SCSCR_TE,
  61         .scbrr_algo_id  = SCBRR_ALGO_4,
  62         .type           = PORT_SCIFA,
  63         .irqs           = { evt2irq(0xc00), evt2irq(0xc00),
  64                             evt2irq(0xc00), evt2irq(0xc00) },
  65 };
  66
  67 static struct platform_device scif0_device = {
  68         .name           = "sh-sci",
  69         .id             = 0,
  70         .dev            = {
  71                 .platform_data  = &scif0_platform_data,
  72         },
  73 };
  74
  75 /* SCIFA1 */
  76 static struct plat_sci_port scif1_platform_data = {
  77         .mapbase        = 0xe6c50000,
  78         .flags          = UPF_BOOT_AUTOCONF,
  79         .scscr          = SCSCR_RE | SCSCR_TE,
  80         .scbrr_algo_id  = SCBRR_ALGO_4,
  81         .type           = PORT_SCIFA,
  82         .irqs           = { evt2irq(0xc20), evt2irq(0xc20),
  83                             evt2irq(0xc20), evt2irq(0xc20) },
  84 };
  85
  86 static struct platform_device scif1_device = {
  87         .name           = "sh-sci",
  88         .id             = 1,
  89         .dev            = {
  90                 .platform_data  = &scif1_platform_data,
  91         },
  92 };
  93
  94 /* SCIFA2 */
  95 static struct plat_sci_port scif2_platform_data = {
  96         .mapbase        = 0xe6c60000,
  97         .flags          = UPF_BOOT_AUTOCONF,
  98         .scscr          = SCSCR_RE | SCSCR_TE,
  99         .scbrr_algo_id  = SCBRR_ALGO_4,
 100         .type           = PORT_SCIFA,
 101         .irqs           = { evt2irq(0xc40), evt2irq(0xc40),
 102                             evt2irq(0xc40), evt2irq(0xc40) },
 103 };
 104
 105 static struct platform_device scif2_device = {
 106         .name           = "sh-sci",
 107         .id             = 2,
 108         .dev            = {
 109                 .platform_data  = &scif2_platform_data,
 110         },
 111 };
 112
 113 /* SCIFA3 */
 114 static struct plat_sci_port scif3_platform_data = {
 115         .mapbase        = 0xe6c70000,
 116         .flags          = UPF_BOOT_AUTOCONF,
 117         .scscr          = SCSCR_RE | SCSCR_TE,
 118         .scbrr_algo_id  = SCBRR_ALGO_4,
 119         .type           = PORT_SCIFA,
 120         .irqs           = { evt2irq(0xc60), evt2irq(0xc60),
 121                             evt2irq(0xc60), evt2irq(0xc60) },
 122 };
 123
 124 static struct platform_device scif3_device = {
 125         .name           = "sh-sci",
 126         .id             = 3,
 127         .dev            = {
 128                 .platform_data  = &scif3_platform_data,
 129         },
 130 };
 131
 132 /* SCIFA4 */
 133 static struct plat_sci_port scif4_platform_data = {
 134         .mapbase        = 0xe6c80000,
 135         .flags          = UPF_BOOT_AUTOCONF,
 136         .scscr          = SCSCR_RE | SCSCR_TE,
 137         .scbrr_algo_id  = SCBRR_ALGO_4,
 138         .type           = PORT_SCIFA,
 139         .irqs           = { evt2irq(0xd20), evt2irq(0xd20),
 140                             evt2irq(0xd20), evt2irq(0xd20) },
 141 };
 142
 143 static struct platform_device scif4_device = {
 144         .name           = "sh-sci",
 145         .id             = 4,
 146         .dev            = {
 147                 .platform_data  = &scif4_platform_data,
 148         },
 149 };
 150
 151 /* SCIFA5 */
 152 static struct plat_sci_port scif5_platform_data = {
 153         .mapbase        = 0xe6cb0000,
 154         .flags          = UPF_BOOT_AUTOCONF,
 155         .scscr          = SCSCR_RE | SCSCR_TE,
 156         .scbrr_algo_id  = SCBRR_ALGO_4,
 157         .type           = PORT_SCIFA,
 158         .irqs           = { evt2irq(0xd40), evt2irq(0xd40),
 159                             evt2irq(0xd40), evt2irq(0xd40) },
 160 };
 161
 162 static struct platform_device scif5_device = {
 163         .name           = "sh-sci",
 164         .id             = 5,
 165         .dev            = {
 166                 .platform_data  = &scif5_platform_data,
 167         },
 168 };
 169
 170 /* SCIFA6 */
 171 static struct plat_sci_port scif6_platform_data = {
 172         .mapbase        = 0xe6cc0000,
 173         .flags          = UPF_BOOT_AUTOCONF,
 174         .scscr          = SCSCR_RE | SCSCR_TE,
 175         .scbrr_algo_id  = SCBRR_ALGO_4,
 176         .type           = PORT_SCIFA,
 177         .irqs           = { intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80),
 178                             intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80) },
 179 };
 180
 181 static struct platform_device scif6_device = {
 182         .name           = "sh-sci",
 183         .id             = 6,
 184         .dev            = {
 185                 .platform_data  = &scif6_platform_data,
 186         },
 187 };
 188
 189 /* SCIFB */
 190 static struct plat_sci_port scif7_platform_data = {
 191         .mapbase        = 0xe6c30000,
 192         .flags          = UPF_BOOT_AUTOCONF,
 193         .scscr          = SCSCR_RE | SCSCR_TE,
 194         .scbrr_algo_id  = SCBRR_ALGO_4,
 195         .type           = PORT_SCIFB,
 196         .irqs           = { evt2irq(0xd60), evt2irq(0xd60),
 197                             evt2irq(0xd60), evt2irq(0xd60) },
 198 };
 199
 200 static struct platform_device scif7_device = {
 201         .name           = "sh-sci",
 202         .id             = 7,
 203         .dev            = {
 204                 .platform_data  = &scif7_platform_data,
 205         },
 206 };
 207
 208 static struct sh_timer_config cmt10_platform_data = {
 209         .name = "CMT10",
 210         .channel_offset = 0x10,
 211         .timer_bit = 0,
 212         .clockevent_rating = 125,
 213         .clocksource_rating = 125,
 214 };
 215
 216 static struct resource cmt10_resources[] = {
 217         [0] = {
 218                 .name   = "CMT10",
 219                 .start  = 0xe6138010,
 220                 .end    = 0xe613801b,
 221                 .flags  = IORESOURCE_MEM,
 222         },
 223         [1] = {
 224                 .start  = evt2irq(0xb00), /* CMT1_CMT10 */
 225                 .flags  = IORESOURCE_IRQ,
 226         },
 227 };
 228
 229 static struct platform_device cmt10_device = {
 230         .name           = "sh_cmt",
 231         .id             = 10,
 232         .dev = {
 233                 .platform_data  = &cmt10_platform_data,
 234         },
 235         .resource       = cmt10_resources,
 236         .num_resources  = ARRAY_SIZE(cmt10_resources),
 237 };
 238
 239 /* VPU */
 240 static struct uio_info vpu_platform_data = {
 241         .name = "VPU5HG",
 242         .version = "0",
 243         .irq = intcs_evt2irq(0x980),
 244 };
 245
 246 static struct resource vpu_resources[] = {
 247         [0] = {
 248                 .name   = "VPU",
 249                 .start  = 0xfe900000,
 250                 .end    = 0xfe900157,
 251                 .flags  = IORESOURCE_MEM,
 252         },
 253 };
 254
 255 static struct platform_device vpu_device = {
 256         .name           = "uio_pdrv_genirq",
 257         .id             = 0,
 258         .dev = {
 259                 .platform_data  = &vpu_platform_data,
 260         },
 261         .resource       = vpu_resources,
 262         .num_resources  = ARRAY_SIZE(vpu_resources),
 263 };
 264
 265 /* VEU0 */
 266 static struct uio_info veu0_platform_data = {
 267         .name = "VEU0",
 268         .version = "0",
 269         .irq = intcs_evt2irq(0x700),
 270 };
 271
 272 static struct resource veu0_resources[] = {
 273         [0] = {
 274                 .name   = "VEU0",
 275                 .start  = 0xfe920000,
 276                 .end    = 0xfe9200cb,
 277                 .flags  = IORESOURCE_MEM,
 278         },
 279 };
 280
 281 static struct platform_device veu0_device = {
 282         .name           = "uio_pdrv_genirq",
 283         .id             = 1,
 284         .dev = {
 285                 .platform_data  = &veu0_platform_data,
 286         },
 287         .resource       = veu0_resources,
 288         .num_resources  = ARRAY_SIZE(veu0_resources),
 289 };
 290
 291 /* VEU1 */
 292 static struct uio_info veu1_platform_data = {
 293         .name = "VEU1",
 294         .version = "0",
 295         .irq = intcs_evt2irq(0x720),
 296 };
 297
 298 static struct resource veu1_resources[] = {
 299         [0] = {
 300                 .name   = "VEU1",
 301                 .start  = 0xfe924000,
 302                 .end    = 0xfe9240cb,
 303                 .flags  = IORESOURCE_MEM,
 304         },
 305 };
 306
 307 static struct platform_device veu1_device = {
 308         .name           = "uio_pdrv_genirq",
 309         .id             = 2,
 310         .dev = {
 311                 .platform_data  = &veu1_platform_data,
 312         },
 313         .resource       = veu1_resources,
 314         .num_resources  = ARRAY_SIZE(veu1_resources),
 315 };
 316
 317 /* VEU2 */
 318 static struct uio_info veu2_platform_data = {
 319         .name = "VEU2",
 320         .version = "0",
 321         .irq = intcs_evt2irq(0x740),
 322 };
 323
 324 static struct resource veu2_resources[] = {
 325         [0] = {
 326                 .name   = "VEU2",
 327                 .start  = 0xfe928000,
 328                 .end    = 0xfe928307,
 329                 .flags  = IORESOURCE_MEM,
 330         },
 331 };
 332
 333 static struct platform_device veu2_device = {
 334         .name           = "uio_pdrv_genirq",
 335         .id             = 3,
 336         .dev = {
 337                 .platform_data  = &veu2_platform_data,
 338         },
 339         .resource       = veu2_resources,
 340         .num_resources  = ARRAY_SIZE(veu2_resources),
 341 };
 342
 343 /* VEU3 */
 344 static struct uio_info veu3_platform_data = {
 345         .name = "VEU3",
 346         .version = "0",
 347         .irq = intcs_evt2irq(0x760),
 348 };
 349
 350 static struct resource veu3_resources[] = {
 351         [0] = {
 352                 .name   = "VEU3",
 353                 .start  = 0xfe92c000,
 354                 .end    = 0xfe92c307,
 355                 .flags  = IORESOURCE_MEM,
 356         },
 357 };
 358
 359 static struct platform_device veu3_device = {
 360         .name           = "uio_pdrv_genirq",
 361         .id             = 4,
 362         .dev = {
 363                 .platform_data  = &veu3_platform_data,
 364         },
 365         .resource       = veu3_resources,
 366         .num_resources  = ARRAY_SIZE(veu3_resources),
 367 };
 368
 369 /* JPU */
 370 static struct uio_info jpu_platform_data = {
 371         .name = "JPU",
 372         .version = "0",
 373         .irq = intcs_evt2irq(0x560),
 374 };
 375
 376 static struct resource jpu_resources[] = {
 377         [0] = {
 378                 .name   = "JPU",
 379                 .start  = 0xfe980000,
 380                 .end    = 0xfe9902d3,
 381                 .flags  = IORESOURCE_MEM,
 382         },
 383 };
 384
 385 static struct platform_device jpu_device = {
 386         .name           = "uio_pdrv_genirq",
 387         .id             = 5,
 388         .dev = {
 389                 .platform_data  = &jpu_platform_data,
 390         },
 391         .resource       = jpu_resources,
 392         .num_resources  = ARRAY_SIZE(jpu_resources),
 393 };
 394
 395 /* SPU2DSP0 */
 396 static struct uio_info spu0_platform_data = {
 397         .name = "SPU2DSP0",
 398         .version = "0",
 399         .irq = evt2irq(0x1800),
 400 };
 401
 402 static struct resource spu0_resources[] = {
 403         [0] = {
 404                 .name   = "SPU2DSP0",
 405                 .start  = 0xfe200000,
 406                 .end    = 0xfe2fffff,
 407                 .flags  = IORESOURCE_MEM,
 408         },
 409 };
 410
 411 static struct platform_device spu0_device = {
 412         .name           = "uio_pdrv_genirq",
 413         .id             = 6,
 414         .dev = {
 415                 .platform_data  = &spu0_platform_data,
 416         },
 417         .resource       = spu0_resources,
 418         .num_resources  = ARRAY_SIZE(spu0_resources),
 419 };
 420
 421 /* SPU2DSP1 */
 422 static struct uio_info spu1_platform_data = {
 423         .name = "SPU2DSP1",
 424         .version = "0",
 425         .irq = evt2irq(0x1820),
 426 };
 427
 428 static struct resource spu1_resources[] = {
 429         [0] = {
 430                 .name   = "SPU2DSP1",
 431                 .start  = 0xfe300000,
 432                 .end    = 0xfe3fffff,
 433                 .flags  = IORESOURCE_MEM,
 434         },
 435 };
 436
 437 static struct platform_device spu1_device = {
 438         .name           = "uio_pdrv_genirq",
 439         .id             = 7,
 440         .dev = {
 441                 .platform_data  = &spu1_platform_data,
 442         },
 443         .resource       = spu1_resources,
 444         .num_resources  = ARRAY_SIZE(spu1_resources),
 445 };
 446
 447 static struct platform_device *sh7377_early_devices[] __initdata = {
 448         &scif0_device,
 449         &scif1_device,
 450         &scif2_device,
 451         &scif3_device,
 452         &scif4_device,
 453         &scif5_device,
 454         &scif6_device,
 455         &scif7_device,
 456         &cmt10_device,
 457 };
 458
 459 static struct platform_device *sh7377_devices[] __initdata = {
 460         &vpu_device,
 461         &veu0_device,
 462         &veu1_device,
 463         &veu2_device,
 464         &veu3_device,
 465         &jpu_device,
 466         &spu0_device,
 467         &spu1_device,
 468 };
 469
 470 void __init sh7377_add_standard_devices(void)
 471 {
 472         platform_add_devices(sh7377_early_devices,
 473                             ARRAY_SIZE(sh7377_early_devices));
 474
 475         platform_add_devices(sh7377_devices,
 476                             ARRAY_SIZE(sh7377_devices));
 477 }
 478
 479 static void __init sh7377_earlytimer_init(void)
 480 {
 481         sh7377_clock_init();
 482         shmobile_earlytimer_init();
 483 }
 484
 485 #define SMSTPCR3 0xe615013c
 486 #define SMSTPCR3_CMT1 (1 << 29)
 487
 488 void __init sh7377_add_early_devices(void)
 489 {
 490         /* enable clock to CMT1 */
 491         __raw_writel(__raw_readl(SMSTPCR3) & ~SMSTPCR3_CMT1, SMSTPCR3);
 492
 493         early_platform_add_devices(sh7377_early_devices,
 494                                    ARRAY_SIZE(sh7377_early_devices));
 495
 496         /* setup early console here as well */
 497         shmobile_setup_console();
 498
 499         /* override timer setup with soc-specific code */
 500         shmobile_timer.init = sh7377_earlytimer_init;
 501 }