2 * sh7372 processor support
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2008 Yoshihiro Shimoda
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
24 #include <linux/platform_device.h>
25 #include <linux/delay.h>
26 #include <linux/input.h>
28 #include <linux/serial_sci.h>
29 #include <linux/sh_dma.h>
30 #include <linux/sh_intc.h>
31 #include <linux/sh_timer.h>
32 #include <mach/hardware.h>
33 #include <mach/sh7372.h>
34 #include <asm/mach-types.h>
35 #include <asm/mach/arch.h>
38 static struct plat_sci_port scif0_platform_data = {
39 .mapbase = 0xe6c40000,
40 .flags = UPF_BOOT_AUTOCONF,
42 .irqs = { evt2irq(0x0c00), evt2irq(0x0c00),
43 evt2irq(0x0c00), evt2irq(0x0c00) },
46 static struct platform_device scif0_device = {
50 .platform_data = &scif0_platform_data,
55 static struct plat_sci_port scif1_platform_data = {
56 .mapbase = 0xe6c50000,
57 .flags = UPF_BOOT_AUTOCONF,
59 .irqs = { evt2irq(0x0c20), evt2irq(0x0c20),
60 evt2irq(0x0c20), evt2irq(0x0c20) },
63 static struct platform_device scif1_device = {
67 .platform_data = &scif1_platform_data,
72 static struct plat_sci_port scif2_platform_data = {
73 .mapbase = 0xe6c60000,
74 .flags = UPF_BOOT_AUTOCONF,
76 .irqs = { evt2irq(0x0c40), evt2irq(0x0c40),
77 evt2irq(0x0c40), evt2irq(0x0c40) },
80 static struct platform_device scif2_device = {
84 .platform_data = &scif2_platform_data,
89 static struct plat_sci_port scif3_platform_data = {
90 .mapbase = 0xe6c70000,
91 .flags = UPF_BOOT_AUTOCONF,
93 .irqs = { evt2irq(0x0c60), evt2irq(0x0c60),
94 evt2irq(0x0c60), evt2irq(0x0c60) },
97 static struct platform_device scif3_device = {
101 .platform_data = &scif3_platform_data,
106 static struct plat_sci_port scif4_platform_data = {
107 .mapbase = 0xe6c80000,
108 .flags = UPF_BOOT_AUTOCONF,
110 .irqs = { evt2irq(0x0d20), evt2irq(0x0d20),
111 evt2irq(0x0d20), evt2irq(0x0d20) },
114 static struct platform_device scif4_device = {
118 .platform_data = &scif4_platform_data,
123 static struct plat_sci_port scif5_platform_data = {
124 .mapbase = 0xe6cb0000,
125 .flags = UPF_BOOT_AUTOCONF,
127 .irqs = { evt2irq(0x0d40), evt2irq(0x0d40),
128 evt2irq(0x0d40), evt2irq(0x0d40) },
131 static struct platform_device scif5_device = {
135 .platform_data = &scif5_platform_data,
140 static struct plat_sci_port scif6_platform_data = {
141 .mapbase = 0xe6c30000,
142 .flags = UPF_BOOT_AUTOCONF,
144 .irqs = { evt2irq(0x0d60), evt2irq(0x0d60),
145 evt2irq(0x0d60), evt2irq(0x0d60) },
148 static struct platform_device scif6_device = {
152 .platform_data = &scif6_platform_data,
157 static struct sh_timer_config cmt10_platform_data = {
159 .channel_offset = 0x10,
162 .clockevent_rating = 125,
163 .clocksource_rating = 125,
166 static struct resource cmt10_resources[] = {
171 .flags = IORESOURCE_MEM,
174 .start = evt2irq(0x0b00), /* CMT1_CMT10 */
175 .flags = IORESOURCE_IRQ,
179 static struct platform_device cmt10_device = {
183 .platform_data = &cmt10_platform_data,
185 .resource = cmt10_resources,
186 .num_resources = ARRAY_SIZE(cmt10_resources),
190 static struct resource iic0_resources[] = {
194 .end = 0xFFF20425 - 1,
195 .flags = IORESOURCE_MEM,
198 .start = intcs_evt2irq(0xe00), /* IIC0_ALI0 */
199 .end = intcs_evt2irq(0xe60), /* IIC0_DTEI0 */
200 .flags = IORESOURCE_IRQ,
204 static struct platform_device iic0_device = {
205 .name = "i2c-sh_mobile",
206 .id = 0, /* "i2c0" clock */
207 .num_resources = ARRAY_SIZE(iic0_resources),
208 .resource = iic0_resources,
211 static struct resource iic1_resources[] = {
215 .end = 0xE6C20425 - 1,
216 .flags = IORESOURCE_MEM,
219 .start = evt2irq(0x780), /* IIC1_ALI1 */
220 .end = evt2irq(0x7e0), /* IIC1_DTEI1 */
221 .flags = IORESOURCE_IRQ,
225 static struct platform_device iic1_device = {
226 .name = "i2c-sh_mobile",
227 .id = 1, /* "i2c1" clock */
228 .num_resources = ARRAY_SIZE(iic1_resources),
229 .resource = iic1_resources,
233 /* Transmit sizes and respective CHCR register values */
244 /* log2(size / 8) - used to calculate number of transfers */
246 [XMIT_SZ_8BIT] = 0, \
247 [XMIT_SZ_16BIT] = 1, \
248 [XMIT_SZ_32BIT] = 2, \
249 [XMIT_SZ_64BIT] = 3, \
250 [XMIT_SZ_128BIT] = 4, \
251 [XMIT_SZ_256BIT] = 5, \
252 [XMIT_SZ_512BIT] = 6, \
255 #define TS_INDEX2VAL(i) ((((i) & 3) << 3) | \
256 (((i) & 0xc) << (20 - 2)))
258 static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
260 .slave_id = SHDMA_SLAVE_SCIF0_TX,
262 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
265 .slave_id = SHDMA_SLAVE_SCIF0_RX,
267 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
270 .slave_id = SHDMA_SLAVE_SCIF1_TX,
272 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
275 .slave_id = SHDMA_SLAVE_SCIF1_RX,
277 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
280 .slave_id = SHDMA_SLAVE_SCIF2_TX,
282 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
285 .slave_id = SHDMA_SLAVE_SCIF2_RX,
287 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
290 .slave_id = SHDMA_SLAVE_SCIF3_TX,
292 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
295 .slave_id = SHDMA_SLAVE_SCIF3_RX,
297 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
300 .slave_id = SHDMA_SLAVE_SCIF4_TX,
302 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
305 .slave_id = SHDMA_SLAVE_SCIF4_RX,
307 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
310 .slave_id = SHDMA_SLAVE_SCIF5_TX,
312 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
315 .slave_id = SHDMA_SLAVE_SCIF5_RX,
317 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
320 .slave_id = SHDMA_SLAVE_SCIF6_TX,
322 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
325 .slave_id = SHDMA_SLAVE_SCIF6_RX,
327 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
330 .slave_id = SHDMA_SLAVE_SDHI0_TX,
332 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
335 .slave_id = SHDMA_SLAVE_SDHI0_RX,
337 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
340 .slave_id = SHDMA_SLAVE_SDHI1_TX,
342 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
345 .slave_id = SHDMA_SLAVE_SDHI1_RX,
347 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
350 .slave_id = SHDMA_SLAVE_SDHI2_TX,
352 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
355 .slave_id = SHDMA_SLAVE_SDHI2_RX,
357 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
362 static const struct sh_dmae_channel sh7372_dmae_channels[] = {
390 static const unsigned int ts_shift[] = TS_SHIFT;
392 static struct sh_dmae_pdata dma_platform_data = {
393 .slave = sh7372_dmae_slaves,
394 .slave_num = ARRAY_SIZE(sh7372_dmae_slaves),
395 .channel = sh7372_dmae_channels,
396 .channel_num = ARRAY_SIZE(sh7372_dmae_channels),
399 .ts_high_shift = (20 - 2), /* 2 bits for shifted low TS */
400 .ts_high_mask = 0x00300000,
401 .ts_shift = ts_shift,
402 .ts_shift_num = ARRAY_SIZE(ts_shift),
403 .dmaor_init = DMAOR_DME,
406 /* Resource order important! */
407 static struct resource sh7372_dmae0_resources[] = {
409 /* Channel registers and DMAOR */
412 .flags = IORESOURCE_MEM,
418 .flags = IORESOURCE_MEM,
424 .flags = IORESOURCE_IRQ,
427 /* IRQ for channels 0-5 */
430 .flags = IORESOURCE_IRQ,
434 /* Resource order important! */
435 static struct resource sh7372_dmae1_resources[] = {
437 /* Channel registers and DMAOR */
440 .flags = IORESOURCE_MEM,
446 .flags = IORESOURCE_MEM,
452 .flags = IORESOURCE_IRQ,
455 /* IRQ for channels 0-5 */
458 .flags = IORESOURCE_IRQ,
462 /* Resource order important! */
463 static struct resource sh7372_dmae2_resources[] = {
465 /* Channel registers and DMAOR */
468 .flags = IORESOURCE_MEM,
474 .flags = IORESOURCE_MEM,
480 .flags = IORESOURCE_IRQ,
483 /* IRQ for channels 0-5 */
486 .flags = IORESOURCE_IRQ,
490 static struct platform_device dma0_device = {
491 .name = "sh-dma-engine",
493 .resource = sh7372_dmae0_resources,
494 .num_resources = ARRAY_SIZE(sh7372_dmae0_resources),
496 .platform_data = &dma_platform_data,
500 static struct platform_device dma1_device = {
501 .name = "sh-dma-engine",
503 .resource = sh7372_dmae1_resources,
504 .num_resources = ARRAY_SIZE(sh7372_dmae1_resources),
506 .platform_data = &dma_platform_data,
510 static struct platform_device dma2_device = {
511 .name = "sh-dma-engine",
513 .resource = sh7372_dmae2_resources,
514 .num_resources = ARRAY_SIZE(sh7372_dmae2_resources),
516 .platform_data = &dma_platform_data,
520 static struct platform_device *sh7372_early_devices[] __initdata = {
536 void __init sh7372_add_standard_devices(void)
538 platform_add_devices(sh7372_early_devices,
539 ARRAY_SIZE(sh7372_early_devices));
542 void __init sh7372_add_early_devices(void)
544 early_platform_add_devices(sh7372_early_devices,
545 ARRAY_SIZE(sh7372_early_devices));