2 * sh7372 processor support
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2008 Yoshihiro Shimoda
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
24 #include <linux/platform_device.h>
25 #include <linux/uio_driver.h>
26 #include <linux/delay.h>
27 #include <linux/input.h>
29 #include <linux/serial_sci.h>
30 #include <linux/sh_dma.h>
31 #include <linux/sh_intc.h>
32 #include <linux/sh_timer.h>
33 #include <mach/hardware.h>
34 #include <mach/sh7372.h>
35 #include <asm/mach-types.h>
36 #include <asm/mach/arch.h>
39 static struct plat_sci_port scif0_platform_data = {
40 .mapbase = 0xe6c40000,
41 .flags = UPF_BOOT_AUTOCONF,
42 .scscr = SCSCR_RE | SCSCR_TE,
43 .scbrr_algo_id = SCBRR_ALGO_4,
45 .irqs = { evt2irq(0x0c00), evt2irq(0x0c00),
46 evt2irq(0x0c00), evt2irq(0x0c00) },
49 static struct platform_device scif0_device = {
53 .platform_data = &scif0_platform_data,
58 static struct plat_sci_port scif1_platform_data = {
59 .mapbase = 0xe6c50000,
60 .flags = UPF_BOOT_AUTOCONF,
61 .scscr = SCSCR_RE | SCSCR_TE,
62 .scbrr_algo_id = SCBRR_ALGO_4,
64 .irqs = { evt2irq(0x0c20), evt2irq(0x0c20),
65 evt2irq(0x0c20), evt2irq(0x0c20) },
68 static struct platform_device scif1_device = {
72 .platform_data = &scif1_platform_data,
77 static struct plat_sci_port scif2_platform_data = {
78 .mapbase = 0xe6c60000,
79 .flags = UPF_BOOT_AUTOCONF,
80 .scscr = SCSCR_RE | SCSCR_TE,
81 .scbrr_algo_id = SCBRR_ALGO_4,
83 .irqs = { evt2irq(0x0c40), evt2irq(0x0c40),
84 evt2irq(0x0c40), evt2irq(0x0c40) },
87 static struct platform_device scif2_device = {
91 .platform_data = &scif2_platform_data,
96 static struct plat_sci_port scif3_platform_data = {
97 .mapbase = 0xe6c70000,
98 .flags = UPF_BOOT_AUTOCONF,
99 .scscr = SCSCR_RE | SCSCR_TE,
100 .scbrr_algo_id = SCBRR_ALGO_4,
102 .irqs = { evt2irq(0x0c60), evt2irq(0x0c60),
103 evt2irq(0x0c60), evt2irq(0x0c60) },
106 static struct platform_device scif3_device = {
110 .platform_data = &scif3_platform_data,
115 static struct plat_sci_port scif4_platform_data = {
116 .mapbase = 0xe6c80000,
117 .flags = UPF_BOOT_AUTOCONF,
118 .scscr = SCSCR_RE | SCSCR_TE,
119 .scbrr_algo_id = SCBRR_ALGO_4,
121 .irqs = { evt2irq(0x0d20), evt2irq(0x0d20),
122 evt2irq(0x0d20), evt2irq(0x0d20) },
125 static struct platform_device scif4_device = {
129 .platform_data = &scif4_platform_data,
134 static struct plat_sci_port scif5_platform_data = {
135 .mapbase = 0xe6cb0000,
136 .flags = UPF_BOOT_AUTOCONF,
137 .scscr = SCSCR_RE | SCSCR_TE,
138 .scbrr_algo_id = SCBRR_ALGO_4,
140 .irqs = { evt2irq(0x0d40), evt2irq(0x0d40),
141 evt2irq(0x0d40), evt2irq(0x0d40) },
144 static struct platform_device scif5_device = {
148 .platform_data = &scif5_platform_data,
153 static struct plat_sci_port scif6_platform_data = {
154 .mapbase = 0xe6c30000,
155 .flags = UPF_BOOT_AUTOCONF,
156 .scscr = SCSCR_RE | SCSCR_TE,
157 .scbrr_algo_id = SCBRR_ALGO_4,
159 .irqs = { evt2irq(0x0d60), evt2irq(0x0d60),
160 evt2irq(0x0d60), evt2irq(0x0d60) },
163 static struct platform_device scif6_device = {
167 .platform_data = &scif6_platform_data,
172 static struct sh_timer_config cmt10_platform_data = {
174 .channel_offset = 0x10,
176 .clockevent_rating = 125,
177 .clocksource_rating = 125,
180 static struct resource cmt10_resources[] = {
185 .flags = IORESOURCE_MEM,
188 .start = evt2irq(0x0b00), /* CMT1_CMT10 */
189 .flags = IORESOURCE_IRQ,
193 static struct platform_device cmt10_device = {
197 .platform_data = &cmt10_platform_data,
199 .resource = cmt10_resources,
200 .num_resources = ARRAY_SIZE(cmt10_resources),
204 static struct sh_timer_config tmu00_platform_data = {
206 .channel_offset = 0x4,
208 .clockevent_rating = 200,
211 static struct resource tmu00_resources[] = {
216 .flags = IORESOURCE_MEM,
219 .start = intcs_evt2irq(0xe80), /* TMU_TUNI0 */
220 .flags = IORESOURCE_IRQ,
224 static struct platform_device tmu00_device = {
228 .platform_data = &tmu00_platform_data,
230 .resource = tmu00_resources,
231 .num_resources = ARRAY_SIZE(tmu00_resources),
234 static struct sh_timer_config tmu01_platform_data = {
236 .channel_offset = 0x10,
238 .clocksource_rating = 200,
241 static struct resource tmu01_resources[] = {
246 .flags = IORESOURCE_MEM,
249 .start = intcs_evt2irq(0xea0), /* TMU_TUNI1 */
250 .flags = IORESOURCE_IRQ,
254 static struct platform_device tmu01_device = {
258 .platform_data = &tmu01_platform_data,
260 .resource = tmu01_resources,
261 .num_resources = ARRAY_SIZE(tmu01_resources),
265 static struct resource iic0_resources[] = {
269 .end = 0xFFF20425 - 1,
270 .flags = IORESOURCE_MEM,
273 .start = intcs_evt2irq(0xe00), /* IIC0_ALI0 */
274 .end = intcs_evt2irq(0xe60), /* IIC0_DTEI0 */
275 .flags = IORESOURCE_IRQ,
279 static struct platform_device iic0_device = {
280 .name = "i2c-sh_mobile",
281 .id = 0, /* "i2c0" clock */
282 .num_resources = ARRAY_SIZE(iic0_resources),
283 .resource = iic0_resources,
286 static struct resource iic1_resources[] = {
290 .end = 0xE6C20425 - 1,
291 .flags = IORESOURCE_MEM,
294 .start = evt2irq(0x780), /* IIC1_ALI1 */
295 .end = evt2irq(0x7e0), /* IIC1_DTEI1 */
296 .flags = IORESOURCE_IRQ,
300 static struct platform_device iic1_device = {
301 .name = "i2c-sh_mobile",
302 .id = 1, /* "i2c1" clock */
303 .num_resources = ARRAY_SIZE(iic1_resources),
304 .resource = iic1_resources,
308 /* Transmit sizes and respective CHCR register values */
319 /* log2(size / 8) - used to calculate number of transfers */
321 [XMIT_SZ_8BIT] = 0, \
322 [XMIT_SZ_16BIT] = 1, \
323 [XMIT_SZ_32BIT] = 2, \
324 [XMIT_SZ_64BIT] = 3, \
325 [XMIT_SZ_128BIT] = 4, \
326 [XMIT_SZ_256BIT] = 5, \
327 [XMIT_SZ_512BIT] = 6, \
330 #define TS_INDEX2VAL(i) ((((i) & 3) << 3) | \
331 (((i) & 0xc) << (20 - 2)))
333 static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
335 .slave_id = SHDMA_SLAVE_SCIF0_TX,
337 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
340 .slave_id = SHDMA_SLAVE_SCIF0_RX,
342 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
345 .slave_id = SHDMA_SLAVE_SCIF1_TX,
347 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
350 .slave_id = SHDMA_SLAVE_SCIF1_RX,
352 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
355 .slave_id = SHDMA_SLAVE_SCIF2_TX,
357 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
360 .slave_id = SHDMA_SLAVE_SCIF2_RX,
362 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
365 .slave_id = SHDMA_SLAVE_SCIF3_TX,
367 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
370 .slave_id = SHDMA_SLAVE_SCIF3_RX,
372 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
375 .slave_id = SHDMA_SLAVE_SCIF4_TX,
377 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
380 .slave_id = SHDMA_SLAVE_SCIF4_RX,
382 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
385 .slave_id = SHDMA_SLAVE_SCIF5_TX,
387 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
390 .slave_id = SHDMA_SLAVE_SCIF5_RX,
392 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
395 .slave_id = SHDMA_SLAVE_SCIF6_TX,
397 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
400 .slave_id = SHDMA_SLAVE_SCIF6_RX,
402 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
405 .slave_id = SHDMA_SLAVE_SDHI0_TX,
407 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
410 .slave_id = SHDMA_SLAVE_SDHI0_RX,
412 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
415 .slave_id = SHDMA_SLAVE_SDHI1_TX,
417 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
420 .slave_id = SHDMA_SLAVE_SDHI1_RX,
422 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
425 .slave_id = SHDMA_SLAVE_SDHI2_TX,
427 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
430 .slave_id = SHDMA_SLAVE_SDHI2_RX,
432 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
435 .slave_id = SHDMA_SLAVE_MMCIF_TX,
437 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
440 .slave_id = SHDMA_SLAVE_MMCIF_RX,
442 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
447 static const struct sh_dmae_channel sh7372_dmae_channels[] = {
475 static const unsigned int ts_shift[] = TS_SHIFT;
477 static struct sh_dmae_pdata dma_platform_data = {
478 .slave = sh7372_dmae_slaves,
479 .slave_num = ARRAY_SIZE(sh7372_dmae_slaves),
480 .channel = sh7372_dmae_channels,
481 .channel_num = ARRAY_SIZE(sh7372_dmae_channels),
484 .ts_high_shift = (20 - 2), /* 2 bits for shifted low TS */
485 .ts_high_mask = 0x00300000,
486 .ts_shift = ts_shift,
487 .ts_shift_num = ARRAY_SIZE(ts_shift),
488 .dmaor_init = DMAOR_DME,
491 /* Resource order important! */
492 static struct resource sh7372_dmae0_resources[] = {
494 /* Channel registers and DMAOR */
497 .flags = IORESOURCE_MEM,
503 .flags = IORESOURCE_MEM,
507 .start = evt2irq(0x20c0),
508 .end = evt2irq(0x20c0),
509 .flags = IORESOURCE_IRQ,
512 /* IRQ for channels 0-5 */
513 .start = evt2irq(0x2000),
514 .end = evt2irq(0x20a0),
515 .flags = IORESOURCE_IRQ,
519 /* Resource order important! */
520 static struct resource sh7372_dmae1_resources[] = {
522 /* Channel registers and DMAOR */
525 .flags = IORESOURCE_MEM,
531 .flags = IORESOURCE_MEM,
535 .start = evt2irq(0x21c0),
536 .end = evt2irq(0x21c0),
537 .flags = IORESOURCE_IRQ,
540 /* IRQ for channels 0-5 */
541 .start = evt2irq(0x2100),
542 .end = evt2irq(0x21a0),
543 .flags = IORESOURCE_IRQ,
547 /* Resource order important! */
548 static struct resource sh7372_dmae2_resources[] = {
550 /* Channel registers and DMAOR */
553 .flags = IORESOURCE_MEM,
559 .flags = IORESOURCE_MEM,
563 .start = evt2irq(0x22c0),
564 .end = evt2irq(0x22c0),
565 .flags = IORESOURCE_IRQ,
568 /* IRQ for channels 0-5 */
569 .start = evt2irq(0x2200),
570 .end = evt2irq(0x22a0),
571 .flags = IORESOURCE_IRQ,
575 static struct platform_device dma0_device = {
576 .name = "sh-dma-engine",
578 .resource = sh7372_dmae0_resources,
579 .num_resources = ARRAY_SIZE(sh7372_dmae0_resources),
581 .platform_data = &dma_platform_data,
585 static struct platform_device dma1_device = {
586 .name = "sh-dma-engine",
588 .resource = sh7372_dmae1_resources,
589 .num_resources = ARRAY_SIZE(sh7372_dmae1_resources),
591 .platform_data = &dma_platform_data,
595 static struct platform_device dma2_device = {
596 .name = "sh-dma-engine",
598 .resource = sh7372_dmae2_resources,
599 .num_resources = ARRAY_SIZE(sh7372_dmae2_resources),
601 .platform_data = &dma_platform_data,
606 static struct uio_info vpu_platform_data = {
609 .irq = intcs_evt2irq(0x980),
612 static struct resource vpu_resources[] = {
617 .flags = IORESOURCE_MEM,
621 static struct platform_device vpu_device = {
622 .name = "uio_pdrv_genirq",
625 .platform_data = &vpu_platform_data,
627 .resource = vpu_resources,
628 .num_resources = ARRAY_SIZE(vpu_resources),
632 static struct uio_info veu0_platform_data = {
635 .irq = intcs_evt2irq(0x700),
638 static struct resource veu0_resources[] = {
643 .flags = IORESOURCE_MEM,
647 static struct platform_device veu0_device = {
648 .name = "uio_pdrv_genirq",
651 .platform_data = &veu0_platform_data,
653 .resource = veu0_resources,
654 .num_resources = ARRAY_SIZE(veu0_resources),
658 static struct uio_info veu1_platform_data = {
661 .irq = intcs_evt2irq(0x720),
664 static struct resource veu1_resources[] = {
669 .flags = IORESOURCE_MEM,
673 static struct platform_device veu1_device = {
674 .name = "uio_pdrv_genirq",
677 .platform_data = &veu1_platform_data,
679 .resource = veu1_resources,
680 .num_resources = ARRAY_SIZE(veu1_resources),
684 static struct uio_info veu2_platform_data = {
687 .irq = intcs_evt2irq(0x740),
690 static struct resource veu2_resources[] = {
695 .flags = IORESOURCE_MEM,
699 static struct platform_device veu2_device = {
700 .name = "uio_pdrv_genirq",
703 .platform_data = &veu2_platform_data,
705 .resource = veu2_resources,
706 .num_resources = ARRAY_SIZE(veu2_resources),
710 static struct uio_info veu3_platform_data = {
713 .irq = intcs_evt2irq(0x760),
716 static struct resource veu3_resources[] = {
721 .flags = IORESOURCE_MEM,
725 static struct platform_device veu3_device = {
726 .name = "uio_pdrv_genirq",
729 .platform_data = &veu3_platform_data,
731 .resource = veu3_resources,
732 .num_resources = ARRAY_SIZE(veu3_resources),
736 static struct uio_info jpu_platform_data = {
739 .irq = intcs_evt2irq(0x560),
742 static struct resource jpu_resources[] = {
747 .flags = IORESOURCE_MEM,
751 static struct platform_device jpu_device = {
752 .name = "uio_pdrv_genirq",
755 .platform_data = &jpu_platform_data,
757 .resource = jpu_resources,
758 .num_resources = ARRAY_SIZE(jpu_resources),
762 static struct uio_info spu0_platform_data = {
765 .irq = evt2irq(0x1800),
768 static struct resource spu0_resources[] = {
773 .flags = IORESOURCE_MEM,
777 static struct platform_device spu0_device = {
778 .name = "uio_pdrv_genirq",
781 .platform_data = &spu0_platform_data,
783 .resource = spu0_resources,
784 .num_resources = ARRAY_SIZE(spu0_resources),
788 static struct uio_info spu1_platform_data = {
791 .irq = evt2irq(0x1820),
794 static struct resource spu1_resources[] = {
799 .flags = IORESOURCE_MEM,
803 static struct platform_device spu1_device = {
804 .name = "uio_pdrv_genirq",
807 .platform_data = &spu1_platform_data,
809 .resource = spu1_resources,
810 .num_resources = ARRAY_SIZE(spu1_resources),
813 static struct platform_device *sh7372_early_devices[] __initdata = {
826 static struct platform_device *sh7372_late_devices[] __initdata = {
842 void __init sh7372_add_standard_devices(void)
844 sh7372_init_pm_domain(&sh7372_a4lc);
845 sh7372_init_pm_domain(&sh7372_a4mp);
846 sh7372_init_pm_domain(&sh7372_d4);
847 sh7372_init_pm_domain(&sh7372_a3rv);
848 sh7372_init_pm_domain(&sh7372_a3ri);
849 sh7372_init_pm_domain(&sh7372_a3sg);
851 platform_add_devices(sh7372_early_devices,
852 ARRAY_SIZE(sh7372_early_devices));
854 platform_add_devices(sh7372_late_devices,
855 ARRAY_SIZE(sh7372_late_devices));
857 sh7372_add_device_to_domain(&sh7372_a3rv, &vpu_device);
858 sh7372_add_device_to_domain(&sh7372_a4mp, &spu0_device);
859 sh7372_add_device_to_domain(&sh7372_a4mp, &spu1_device);
862 void __init sh7372_add_early_devices(void)
864 early_platform_add_devices(sh7372_early_devices,
865 ARRAY_SIZE(sh7372_early_devices));