2 * sh7372 processor support
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2008 Yoshihiro Shimoda
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
24 #include <linux/platform_device.h>
25 #include <linux/of_platform.h>
26 #include <linux/uio_driver.h>
27 #include <linux/delay.h>
28 #include <linux/input.h>
30 #include <linux/serial_sci.h>
31 #include <linux/sh_dma.h>
32 #include <linux/sh_intc.h>
33 #include <linux/sh_timer.h>
34 #include <linux/pm_domain.h>
35 #include <linux/dma-mapping.h>
36 #include <mach/hardware.h>
37 #include <mach/irqs.h>
38 #include <mach/sh7372.h>
39 #include <mach/common.h>
40 #include <asm/mach/map.h>
41 #include <asm/mach-types.h>
42 #include <asm/mach/arch.h>
43 #include <asm/mach/time.h>
45 static struct map_desc sh7372_io_desc[] __initdata = {
46 /* create a 1:1 entity map for 0xe6xxxxxx
47 * used by CPGA, INTC and PFC.
50 .virtual = 0xe6000000,
51 .pfn = __phys_to_pfn(0xe6000000),
53 .type = MT_DEVICE_NONSHARED
57 void __init sh7372_map_io(void)
59 iotable_init(sh7372_io_desc, ARRAY_SIZE(sh7372_io_desc));
62 * DMA memory at 0xff200000 - 0xffdfffff. The default 2MB size isn't
63 * enough to allocate the frame buffer memory.
65 init_consistent_dma_size(12 << 20);
69 static struct plat_sci_port scif0_platform_data = {
70 .mapbase = 0xe6c40000,
71 .flags = UPF_BOOT_AUTOCONF,
72 .scscr = SCSCR_RE | SCSCR_TE,
73 .scbrr_algo_id = SCBRR_ALGO_4,
75 .irqs = { evt2irq(0x0c00), evt2irq(0x0c00),
76 evt2irq(0x0c00), evt2irq(0x0c00) },
79 static struct platform_device scif0_device = {
83 .platform_data = &scif0_platform_data,
88 static struct plat_sci_port scif1_platform_data = {
89 .mapbase = 0xe6c50000,
90 .flags = UPF_BOOT_AUTOCONF,
91 .scscr = SCSCR_RE | SCSCR_TE,
92 .scbrr_algo_id = SCBRR_ALGO_4,
94 .irqs = { evt2irq(0x0c20), evt2irq(0x0c20),
95 evt2irq(0x0c20), evt2irq(0x0c20) },
98 static struct platform_device scif1_device = {
102 .platform_data = &scif1_platform_data,
107 static struct plat_sci_port scif2_platform_data = {
108 .mapbase = 0xe6c60000,
109 .flags = UPF_BOOT_AUTOCONF,
110 .scscr = SCSCR_RE | SCSCR_TE,
111 .scbrr_algo_id = SCBRR_ALGO_4,
113 .irqs = { evt2irq(0x0c40), evt2irq(0x0c40),
114 evt2irq(0x0c40), evt2irq(0x0c40) },
117 static struct platform_device scif2_device = {
121 .platform_data = &scif2_platform_data,
126 static struct plat_sci_port scif3_platform_data = {
127 .mapbase = 0xe6c70000,
128 .flags = UPF_BOOT_AUTOCONF,
129 .scscr = SCSCR_RE | SCSCR_TE,
130 .scbrr_algo_id = SCBRR_ALGO_4,
132 .irqs = { evt2irq(0x0c60), evt2irq(0x0c60),
133 evt2irq(0x0c60), evt2irq(0x0c60) },
136 static struct platform_device scif3_device = {
140 .platform_data = &scif3_platform_data,
145 static struct plat_sci_port scif4_platform_data = {
146 .mapbase = 0xe6c80000,
147 .flags = UPF_BOOT_AUTOCONF,
148 .scscr = SCSCR_RE | SCSCR_TE,
149 .scbrr_algo_id = SCBRR_ALGO_4,
151 .irqs = { evt2irq(0x0d20), evt2irq(0x0d20),
152 evt2irq(0x0d20), evt2irq(0x0d20) },
155 static struct platform_device scif4_device = {
159 .platform_data = &scif4_platform_data,
164 static struct plat_sci_port scif5_platform_data = {
165 .mapbase = 0xe6cb0000,
166 .flags = UPF_BOOT_AUTOCONF,
167 .scscr = SCSCR_RE | SCSCR_TE,
168 .scbrr_algo_id = SCBRR_ALGO_4,
170 .irqs = { evt2irq(0x0d40), evt2irq(0x0d40),
171 evt2irq(0x0d40), evt2irq(0x0d40) },
174 static struct platform_device scif5_device = {
178 .platform_data = &scif5_platform_data,
183 static struct plat_sci_port scif6_platform_data = {
184 .mapbase = 0xe6c30000,
185 .flags = UPF_BOOT_AUTOCONF,
186 .scscr = SCSCR_RE | SCSCR_TE,
187 .scbrr_algo_id = SCBRR_ALGO_4,
189 .irqs = { evt2irq(0x0d60), evt2irq(0x0d60),
190 evt2irq(0x0d60), evt2irq(0x0d60) },
193 static struct platform_device scif6_device = {
197 .platform_data = &scif6_platform_data,
202 static struct sh_timer_config cmt2_platform_data = {
204 .channel_offset = 0x40,
206 .clockevent_rating = 125,
207 .clocksource_rating = 125,
210 static struct resource cmt2_resources[] = {
215 .flags = IORESOURCE_MEM,
218 .start = evt2irq(0x0b80), /* CMT2 */
219 .flags = IORESOURCE_IRQ,
223 static struct platform_device cmt2_device = {
227 .platform_data = &cmt2_platform_data,
229 .resource = cmt2_resources,
230 .num_resources = ARRAY_SIZE(cmt2_resources),
234 static struct sh_timer_config tmu00_platform_data = {
236 .channel_offset = 0x4,
238 .clockevent_rating = 200,
241 static struct resource tmu00_resources[] = {
246 .flags = IORESOURCE_MEM,
249 .start = intcs_evt2irq(0xe80), /* TMU_TUNI0 */
250 .flags = IORESOURCE_IRQ,
254 static struct platform_device tmu00_device = {
258 .platform_data = &tmu00_platform_data,
260 .resource = tmu00_resources,
261 .num_resources = ARRAY_SIZE(tmu00_resources),
264 static struct sh_timer_config tmu01_platform_data = {
266 .channel_offset = 0x10,
268 .clocksource_rating = 200,
271 static struct resource tmu01_resources[] = {
276 .flags = IORESOURCE_MEM,
279 .start = intcs_evt2irq(0xea0), /* TMU_TUNI1 */
280 .flags = IORESOURCE_IRQ,
284 static struct platform_device tmu01_device = {
288 .platform_data = &tmu01_platform_data,
290 .resource = tmu01_resources,
291 .num_resources = ARRAY_SIZE(tmu01_resources),
295 static struct resource iic0_resources[] = {
299 .end = 0xFFF20425 - 1,
300 .flags = IORESOURCE_MEM,
303 .start = intcs_evt2irq(0xe00), /* IIC0_ALI0 */
304 .end = intcs_evt2irq(0xe60), /* IIC0_DTEI0 */
305 .flags = IORESOURCE_IRQ,
309 static struct platform_device iic0_device = {
310 .name = "i2c-sh_mobile",
311 .id = 0, /* "i2c0" clock */
312 .num_resources = ARRAY_SIZE(iic0_resources),
313 .resource = iic0_resources,
316 static struct resource iic1_resources[] = {
320 .end = 0xE6C20425 - 1,
321 .flags = IORESOURCE_MEM,
324 .start = evt2irq(0x780), /* IIC1_ALI1 */
325 .end = evt2irq(0x7e0), /* IIC1_DTEI1 */
326 .flags = IORESOURCE_IRQ,
330 static struct platform_device iic1_device = {
331 .name = "i2c-sh_mobile",
332 .id = 1, /* "i2c1" clock */
333 .num_resources = ARRAY_SIZE(iic1_resources),
334 .resource = iic1_resources,
338 /* Transmit sizes and respective CHCR register values */
349 /* log2(size / 8) - used to calculate number of transfers */
351 [XMIT_SZ_8BIT] = 0, \
352 [XMIT_SZ_16BIT] = 1, \
353 [XMIT_SZ_32BIT] = 2, \
354 [XMIT_SZ_64BIT] = 3, \
355 [XMIT_SZ_128BIT] = 4, \
356 [XMIT_SZ_256BIT] = 5, \
357 [XMIT_SZ_512BIT] = 6, \
360 #define TS_INDEX2VAL(i) ((((i) & 3) << 3) | \
361 (((i) & 0xc) << (20 - 2)))
363 static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
365 .slave_id = SHDMA_SLAVE_SCIF0_TX,
367 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
370 .slave_id = SHDMA_SLAVE_SCIF0_RX,
372 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
375 .slave_id = SHDMA_SLAVE_SCIF1_TX,
377 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
380 .slave_id = SHDMA_SLAVE_SCIF1_RX,
382 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
385 .slave_id = SHDMA_SLAVE_SCIF2_TX,
387 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
390 .slave_id = SHDMA_SLAVE_SCIF2_RX,
392 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
395 .slave_id = SHDMA_SLAVE_SCIF3_TX,
397 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
400 .slave_id = SHDMA_SLAVE_SCIF3_RX,
402 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
405 .slave_id = SHDMA_SLAVE_SCIF4_TX,
407 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
410 .slave_id = SHDMA_SLAVE_SCIF4_RX,
412 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
415 .slave_id = SHDMA_SLAVE_SCIF5_TX,
417 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
420 .slave_id = SHDMA_SLAVE_SCIF5_RX,
422 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
425 .slave_id = SHDMA_SLAVE_SCIF6_TX,
427 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
430 .slave_id = SHDMA_SLAVE_SCIF6_RX,
432 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
435 .slave_id = SHDMA_SLAVE_SDHI0_TX,
437 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
440 .slave_id = SHDMA_SLAVE_SDHI0_RX,
442 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
445 .slave_id = SHDMA_SLAVE_SDHI1_TX,
447 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
450 .slave_id = SHDMA_SLAVE_SDHI1_RX,
452 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
455 .slave_id = SHDMA_SLAVE_SDHI2_TX,
457 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
460 .slave_id = SHDMA_SLAVE_SDHI2_RX,
462 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
465 .slave_id = SHDMA_SLAVE_FSIA_TX,
467 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
470 .slave_id = SHDMA_SLAVE_FSIA_RX,
472 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
475 .slave_id = SHDMA_SLAVE_MMCIF_TX,
477 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
480 .slave_id = SHDMA_SLAVE_MMCIF_RX,
482 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
487 #define SH7372_CHCLR (0x220 - 0x20)
489 static const struct sh_dmae_channel sh7372_dmae_channels[] = {
494 .chclr_offset = SH7372_CHCLR + 0,
499 .chclr_offset = SH7372_CHCLR + 0x10,
504 .chclr_offset = SH7372_CHCLR + 0x20,
509 .chclr_offset = SH7372_CHCLR + 0x30,
514 .chclr_offset = SH7372_CHCLR + 0x50,
519 .chclr_offset = SH7372_CHCLR + 0x60,
523 static const unsigned int ts_shift[] = TS_SHIFT;
525 static struct sh_dmae_pdata dma_platform_data = {
526 .slave = sh7372_dmae_slaves,
527 .slave_num = ARRAY_SIZE(sh7372_dmae_slaves),
528 .channel = sh7372_dmae_channels,
529 .channel_num = ARRAY_SIZE(sh7372_dmae_channels),
532 .ts_high_shift = (20 - 2), /* 2 bits for shifted low TS */
533 .ts_high_mask = 0x00300000,
534 .ts_shift = ts_shift,
535 .ts_shift_num = ARRAY_SIZE(ts_shift),
536 .dmaor_init = DMAOR_DME,
540 /* Resource order important! */
541 static struct resource sh7372_dmae0_resources[] = {
543 /* Channel registers and DMAOR */
546 .flags = IORESOURCE_MEM,
552 .flags = IORESOURCE_MEM,
556 .start = evt2irq(0x20c0),
557 .end = evt2irq(0x20c0),
558 .flags = IORESOURCE_IRQ,
561 /* IRQ for channels 0-5 */
562 .start = evt2irq(0x2000),
563 .end = evt2irq(0x20a0),
564 .flags = IORESOURCE_IRQ,
568 /* Resource order important! */
569 static struct resource sh7372_dmae1_resources[] = {
571 /* Channel registers and DMAOR */
574 .flags = IORESOURCE_MEM,
580 .flags = IORESOURCE_MEM,
584 .start = evt2irq(0x21c0),
585 .end = evt2irq(0x21c0),
586 .flags = IORESOURCE_IRQ,
589 /* IRQ for channels 0-5 */
590 .start = evt2irq(0x2100),
591 .end = evt2irq(0x21a0),
592 .flags = IORESOURCE_IRQ,
596 /* Resource order important! */
597 static struct resource sh7372_dmae2_resources[] = {
599 /* Channel registers and DMAOR */
602 .flags = IORESOURCE_MEM,
608 .flags = IORESOURCE_MEM,
612 .start = evt2irq(0x22c0),
613 .end = evt2irq(0x22c0),
614 .flags = IORESOURCE_IRQ,
617 /* IRQ for channels 0-5 */
618 .start = evt2irq(0x2200),
619 .end = evt2irq(0x22a0),
620 .flags = IORESOURCE_IRQ,
624 static struct platform_device dma0_device = {
625 .name = "sh-dma-engine",
627 .resource = sh7372_dmae0_resources,
628 .num_resources = ARRAY_SIZE(sh7372_dmae0_resources),
630 .platform_data = &dma_platform_data,
634 static struct platform_device dma1_device = {
635 .name = "sh-dma-engine",
637 .resource = sh7372_dmae1_resources,
638 .num_resources = ARRAY_SIZE(sh7372_dmae1_resources),
640 .platform_data = &dma_platform_data,
644 static struct platform_device dma2_device = {
645 .name = "sh-dma-engine",
647 .resource = sh7372_dmae2_resources,
648 .num_resources = ARRAY_SIZE(sh7372_dmae2_resources),
650 .platform_data = &dma_platform_data,
658 unsigned int usbts_shift[] = {3, 4, 5};
666 #define USBTS_INDEX2VAL(i) (((i) & 3) << 6)
668 static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = {
677 static const struct sh_dmae_slave_config sh7372_usb_dmae0_slaves[] = {
679 .slave_id = SHDMA_SLAVE_USB0_TX,
680 .chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
682 .slave_id = SHDMA_SLAVE_USB0_RX,
683 .chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
687 static struct sh_dmae_pdata usb_dma0_platform_data = {
688 .slave = sh7372_usb_dmae0_slaves,
689 .slave_num = ARRAY_SIZE(sh7372_usb_dmae0_slaves),
690 .channel = sh7372_usb_dmae_channels,
691 .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
696 .ts_shift = usbts_shift,
697 .ts_shift_num = ARRAY_SIZE(usbts_shift),
698 .dmaor_init = DMAOR_DME,
700 .chcr_ie_bit = 1 << 5,
707 static struct resource sh7372_usb_dmae0_resources[] = {
709 /* Channel registers and DMAOR */
711 .end = 0xe68a0064 - 1,
712 .flags = IORESOURCE_MEM,
717 .end = 0xe68a0014 - 1,
718 .flags = IORESOURCE_MEM,
721 /* IRQ for channels */
722 .start = evt2irq(0x0a00),
723 .end = evt2irq(0x0a00),
724 .flags = IORESOURCE_IRQ,
728 static struct platform_device usb_dma0_device = {
729 .name = "sh-dma-engine",
731 .resource = sh7372_usb_dmae0_resources,
732 .num_resources = ARRAY_SIZE(sh7372_usb_dmae0_resources),
734 .platform_data = &usb_dma0_platform_data,
739 static const struct sh_dmae_slave_config sh7372_usb_dmae1_slaves[] = {
741 .slave_id = SHDMA_SLAVE_USB1_TX,
742 .chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
744 .slave_id = SHDMA_SLAVE_USB1_RX,
745 .chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
749 static struct sh_dmae_pdata usb_dma1_platform_data = {
750 .slave = sh7372_usb_dmae1_slaves,
751 .slave_num = ARRAY_SIZE(sh7372_usb_dmae1_slaves),
752 .channel = sh7372_usb_dmae_channels,
753 .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
758 .ts_shift = usbts_shift,
759 .ts_shift_num = ARRAY_SIZE(usbts_shift),
760 .dmaor_init = DMAOR_DME,
762 .chcr_ie_bit = 1 << 5,
769 static struct resource sh7372_usb_dmae1_resources[] = {
771 /* Channel registers and DMAOR */
773 .end = 0xe68c0064 - 1,
774 .flags = IORESOURCE_MEM,
779 .end = 0xe68c0014 - 1,
780 .flags = IORESOURCE_MEM,
783 /* IRQ for channels */
784 .start = evt2irq(0x1d00),
785 .end = evt2irq(0x1d00),
786 .flags = IORESOURCE_IRQ,
790 static struct platform_device usb_dma1_device = {
791 .name = "sh-dma-engine",
793 .resource = sh7372_usb_dmae1_resources,
794 .num_resources = ARRAY_SIZE(sh7372_usb_dmae1_resources),
796 .platform_data = &usb_dma1_platform_data,
801 static struct uio_info vpu_platform_data = {
804 .irq = intcs_evt2irq(0x980),
807 static struct resource vpu_resources[] = {
812 .flags = IORESOURCE_MEM,
816 static struct platform_device vpu_device = {
817 .name = "uio_pdrv_genirq",
820 .platform_data = &vpu_platform_data,
822 .resource = vpu_resources,
823 .num_resources = ARRAY_SIZE(vpu_resources),
827 static struct uio_info veu0_platform_data = {
830 .irq = intcs_evt2irq(0x700),
833 static struct resource veu0_resources[] = {
838 .flags = IORESOURCE_MEM,
842 static struct platform_device veu0_device = {
843 .name = "uio_pdrv_genirq",
846 .platform_data = &veu0_platform_data,
848 .resource = veu0_resources,
849 .num_resources = ARRAY_SIZE(veu0_resources),
853 static struct uio_info veu1_platform_data = {
856 .irq = intcs_evt2irq(0x720),
859 static struct resource veu1_resources[] = {
864 .flags = IORESOURCE_MEM,
868 static struct platform_device veu1_device = {
869 .name = "uio_pdrv_genirq",
872 .platform_data = &veu1_platform_data,
874 .resource = veu1_resources,
875 .num_resources = ARRAY_SIZE(veu1_resources),
879 static struct uio_info veu2_platform_data = {
882 .irq = intcs_evt2irq(0x740),
885 static struct resource veu2_resources[] = {
890 .flags = IORESOURCE_MEM,
894 static struct platform_device veu2_device = {
895 .name = "uio_pdrv_genirq",
898 .platform_data = &veu2_platform_data,
900 .resource = veu2_resources,
901 .num_resources = ARRAY_SIZE(veu2_resources),
905 static struct uio_info veu3_platform_data = {
908 .irq = intcs_evt2irq(0x760),
911 static struct resource veu3_resources[] = {
916 .flags = IORESOURCE_MEM,
920 static struct platform_device veu3_device = {
921 .name = "uio_pdrv_genirq",
924 .platform_data = &veu3_platform_data,
926 .resource = veu3_resources,
927 .num_resources = ARRAY_SIZE(veu3_resources),
931 static struct uio_info jpu_platform_data = {
934 .irq = intcs_evt2irq(0x560),
937 static struct resource jpu_resources[] = {
942 .flags = IORESOURCE_MEM,
946 static struct platform_device jpu_device = {
947 .name = "uio_pdrv_genirq",
950 .platform_data = &jpu_platform_data,
952 .resource = jpu_resources,
953 .num_resources = ARRAY_SIZE(jpu_resources),
957 static struct uio_info spu0_platform_data = {
960 .irq = evt2irq(0x1800),
963 static struct resource spu0_resources[] = {
968 .flags = IORESOURCE_MEM,
972 static struct platform_device spu0_device = {
973 .name = "uio_pdrv_genirq",
976 .platform_data = &spu0_platform_data,
978 .resource = spu0_resources,
979 .num_resources = ARRAY_SIZE(spu0_resources),
983 static struct uio_info spu1_platform_data = {
986 .irq = evt2irq(0x1820),
989 static struct resource spu1_resources[] = {
994 .flags = IORESOURCE_MEM,
998 static struct platform_device spu1_device = {
999 .name = "uio_pdrv_genirq",
1002 .platform_data = &spu1_platform_data,
1004 .resource = spu1_resources,
1005 .num_resources = ARRAY_SIZE(spu1_resources),
1008 static struct platform_device *sh7372_early_devices[] __initdata = {
1021 static struct platform_device *sh7372_late_devices[] __initdata = {
1039 void __init sh7372_add_standard_devices(void)
1041 sh7372_init_pm_domain(&sh7372_a4lc);
1042 sh7372_init_pm_domain(&sh7372_a4mp);
1043 sh7372_init_pm_domain(&sh7372_d4);
1044 sh7372_init_pm_domain(&sh7372_a4r);
1045 sh7372_init_pm_domain(&sh7372_a3rv);
1046 sh7372_init_pm_domain(&sh7372_a3ri);
1047 sh7372_init_pm_domain(&sh7372_a4s);
1048 sh7372_init_pm_domain(&sh7372_a3sp);
1049 sh7372_init_pm_domain(&sh7372_a3sg);
1051 sh7372_pm_add_subdomain(&sh7372_a4lc, &sh7372_a3rv);
1052 sh7372_pm_add_subdomain(&sh7372_a4r, &sh7372_a4lc);
1054 sh7372_pm_add_subdomain(&sh7372_a4s, &sh7372_a3sg);
1055 sh7372_pm_add_subdomain(&sh7372_a4s, &sh7372_a3sp);
1057 platform_add_devices(sh7372_early_devices,
1058 ARRAY_SIZE(sh7372_early_devices));
1060 platform_add_devices(sh7372_late_devices,
1061 ARRAY_SIZE(sh7372_late_devices));
1063 sh7372_add_device_to_domain(&sh7372_a3rv, &vpu_device);
1064 sh7372_add_device_to_domain(&sh7372_a4mp, &spu0_device);
1065 sh7372_add_device_to_domain(&sh7372_a4mp, &spu1_device);
1066 sh7372_add_device_to_domain(&sh7372_a3sp, &scif0_device);
1067 sh7372_add_device_to_domain(&sh7372_a3sp, &scif1_device);
1068 sh7372_add_device_to_domain(&sh7372_a3sp, &scif2_device);
1069 sh7372_add_device_to_domain(&sh7372_a3sp, &scif3_device);
1070 sh7372_add_device_to_domain(&sh7372_a3sp, &scif4_device);
1071 sh7372_add_device_to_domain(&sh7372_a3sp, &scif5_device);
1072 sh7372_add_device_to_domain(&sh7372_a3sp, &scif6_device);
1073 sh7372_add_device_to_domain(&sh7372_a3sp, &iic1_device);
1074 sh7372_add_device_to_domain(&sh7372_a3sp, &dma0_device);
1075 sh7372_add_device_to_domain(&sh7372_a3sp, &dma1_device);
1076 sh7372_add_device_to_domain(&sh7372_a3sp, &dma2_device);
1077 sh7372_add_device_to_domain(&sh7372_a3sp, &usb_dma0_device);
1078 sh7372_add_device_to_domain(&sh7372_a3sp, &usb_dma1_device);
1079 sh7372_add_device_to_domain(&sh7372_a4r, &iic0_device);
1080 sh7372_add_device_to_domain(&sh7372_a4r, &veu0_device);
1081 sh7372_add_device_to_domain(&sh7372_a4r, &veu1_device);
1082 sh7372_add_device_to_domain(&sh7372_a4r, &veu2_device);
1083 sh7372_add_device_to_domain(&sh7372_a4r, &veu3_device);
1084 sh7372_add_device_to_domain(&sh7372_a4r, &jpu_device);
1085 sh7372_add_device_to_domain(&sh7372_a4r, &tmu00_device);
1086 sh7372_add_device_to_domain(&sh7372_a4r, &tmu01_device);
1089 static void __init sh7372_earlytimer_init(void)
1091 sh7372_clock_init();
1092 shmobile_earlytimer_init();
1095 void __init sh7372_add_early_devices(void)
1097 early_platform_add_devices(sh7372_early_devices,
1098 ARRAY_SIZE(sh7372_early_devices));
1100 /* setup early console here as well */
1101 shmobile_setup_console();
1103 /* override timer setup with soc-specific code */
1104 shmobile_timer.init = sh7372_earlytimer_init;
1107 #ifdef CONFIG_USE_OF
1109 void __init sh7372_add_early_devices_dt(void)
1111 shmobile_setup_delay(800, 1, 3); /* Cortex-A8 @ 800MHz */
1113 early_platform_add_devices(sh7372_early_devices,
1114 ARRAY_SIZE(sh7372_early_devices));
1116 /* setup early console here as well */
1117 shmobile_setup_console();
1120 static const struct of_dev_auxdata sh7372_auxdata_lookup[] __initconst = {
1124 void __init sh7372_add_standard_devices_dt(void)
1126 /* clocks are setup late during boot in the case of DT */
1127 sh7372_clock_init();
1129 platform_add_devices(sh7372_early_devices,
1130 ARRAY_SIZE(sh7372_early_devices));
1132 of_platform_populate(NULL, of_default_bus_match_table,
1133 sh7372_auxdata_lookup, NULL);
1136 static const char *sh7372_boards_compat_dt[] __initdata = {
1141 DT_MACHINE_START(SH7372_DT, "Generic SH7372 (Flattened Device Tree)")
1142 .map_io = sh7372_map_io,
1143 .init_early = sh7372_add_early_devices_dt,
1144 .nr_irqs = NR_IRQS_LEGACY,
1145 .init_irq = sh7372_init_irq,
1146 .handle_irq = shmobile_handle_irq_intc,
1147 .init_machine = sh7372_add_standard_devices_dt,
1148 .timer = &shmobile_timer,
1149 .dt_compat = sh7372_boards_compat_dt,
1152 #endif /* CONFIG_USE_OF */