2 * sh7372 processor support
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2008 Yoshihiro Shimoda
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
24 #include <linux/platform_device.h>
25 #include <linux/uio_driver.h>
26 #include <linux/delay.h>
27 #include <linux/input.h>
29 #include <linux/serial_sci.h>
30 #include <linux/sh_dma.h>
31 #include <linux/sh_intc.h>
32 #include <linux/sh_timer.h>
33 #include <linux/pm_domain.h>
34 #include <mach/hardware.h>
35 #include <mach/sh7372.h>
36 #include <mach/common.h>
37 #include <asm/mach/map.h>
38 #include <asm/mach-types.h>
39 #include <asm/mach/arch.h>
40 #include <asm/mach/time.h>
42 static struct map_desc sh7372_io_desc[] __initdata = {
43 /* create a 1:1 entity map for 0xe6xxxxxx
44 * used by CPGA, INTC and PFC.
47 .virtual = 0xe6000000,
48 .pfn = __phys_to_pfn(0xe6000000),
50 .type = MT_DEVICE_NONSHARED
54 void __init sh7372_map_io(void)
56 iotable_init(sh7372_io_desc, ARRAY_SIZE(sh7372_io_desc));
60 static struct plat_sci_port scif0_platform_data = {
61 .mapbase = 0xe6c40000,
62 .flags = UPF_BOOT_AUTOCONF,
63 .scscr = SCSCR_RE | SCSCR_TE,
64 .scbrr_algo_id = SCBRR_ALGO_4,
66 .irqs = { evt2irq(0x0c00), evt2irq(0x0c00),
67 evt2irq(0x0c00), evt2irq(0x0c00) },
70 static struct platform_device scif0_device = {
74 .platform_data = &scif0_platform_data,
79 static struct plat_sci_port scif1_platform_data = {
80 .mapbase = 0xe6c50000,
81 .flags = UPF_BOOT_AUTOCONF,
82 .scscr = SCSCR_RE | SCSCR_TE,
83 .scbrr_algo_id = SCBRR_ALGO_4,
85 .irqs = { evt2irq(0x0c20), evt2irq(0x0c20),
86 evt2irq(0x0c20), evt2irq(0x0c20) },
89 static struct platform_device scif1_device = {
93 .platform_data = &scif1_platform_data,
98 static struct plat_sci_port scif2_platform_data = {
99 .mapbase = 0xe6c60000,
100 .flags = UPF_BOOT_AUTOCONF,
101 .scscr = SCSCR_RE | SCSCR_TE,
102 .scbrr_algo_id = SCBRR_ALGO_4,
104 .irqs = { evt2irq(0x0c40), evt2irq(0x0c40),
105 evt2irq(0x0c40), evt2irq(0x0c40) },
108 static struct platform_device scif2_device = {
112 .platform_data = &scif2_platform_data,
117 static struct plat_sci_port scif3_platform_data = {
118 .mapbase = 0xe6c70000,
119 .flags = UPF_BOOT_AUTOCONF,
120 .scscr = SCSCR_RE | SCSCR_TE,
121 .scbrr_algo_id = SCBRR_ALGO_4,
123 .irqs = { evt2irq(0x0c60), evt2irq(0x0c60),
124 evt2irq(0x0c60), evt2irq(0x0c60) },
127 static struct platform_device scif3_device = {
131 .platform_data = &scif3_platform_data,
136 static struct plat_sci_port scif4_platform_data = {
137 .mapbase = 0xe6c80000,
138 .flags = UPF_BOOT_AUTOCONF,
139 .scscr = SCSCR_RE | SCSCR_TE,
140 .scbrr_algo_id = SCBRR_ALGO_4,
142 .irqs = { evt2irq(0x0d20), evt2irq(0x0d20),
143 evt2irq(0x0d20), evt2irq(0x0d20) },
146 static struct platform_device scif4_device = {
150 .platform_data = &scif4_platform_data,
155 static struct plat_sci_port scif5_platform_data = {
156 .mapbase = 0xe6cb0000,
157 .flags = UPF_BOOT_AUTOCONF,
158 .scscr = SCSCR_RE | SCSCR_TE,
159 .scbrr_algo_id = SCBRR_ALGO_4,
161 .irqs = { evt2irq(0x0d40), evt2irq(0x0d40),
162 evt2irq(0x0d40), evt2irq(0x0d40) },
165 static struct platform_device scif5_device = {
169 .platform_data = &scif5_platform_data,
174 static struct plat_sci_port scif6_platform_data = {
175 .mapbase = 0xe6c30000,
176 .flags = UPF_BOOT_AUTOCONF,
177 .scscr = SCSCR_RE | SCSCR_TE,
178 .scbrr_algo_id = SCBRR_ALGO_4,
180 .irqs = { evt2irq(0x0d60), evt2irq(0x0d60),
181 evt2irq(0x0d60), evt2irq(0x0d60) },
184 static struct platform_device scif6_device = {
188 .platform_data = &scif6_platform_data,
193 static struct sh_timer_config cmt2_platform_data = {
195 .channel_offset = 0x40,
197 .clockevent_rating = 125,
198 .clocksource_rating = 125,
201 static struct resource cmt2_resources[] = {
206 .flags = IORESOURCE_MEM,
209 .start = evt2irq(0x0b80), /* CMT2 */
210 .flags = IORESOURCE_IRQ,
214 static struct platform_device cmt2_device = {
218 .platform_data = &cmt2_platform_data,
220 .resource = cmt2_resources,
221 .num_resources = ARRAY_SIZE(cmt2_resources),
225 static struct sh_timer_config tmu00_platform_data = {
227 .channel_offset = 0x4,
229 .clockevent_rating = 200,
232 static struct resource tmu00_resources[] = {
237 .flags = IORESOURCE_MEM,
240 .start = intcs_evt2irq(0xe80), /* TMU_TUNI0 */
241 .flags = IORESOURCE_IRQ,
245 static struct platform_device tmu00_device = {
249 .platform_data = &tmu00_platform_data,
251 .resource = tmu00_resources,
252 .num_resources = ARRAY_SIZE(tmu00_resources),
255 static struct sh_timer_config tmu01_platform_data = {
257 .channel_offset = 0x10,
259 .clocksource_rating = 200,
262 static struct resource tmu01_resources[] = {
267 .flags = IORESOURCE_MEM,
270 .start = intcs_evt2irq(0xea0), /* TMU_TUNI1 */
271 .flags = IORESOURCE_IRQ,
275 static struct platform_device tmu01_device = {
279 .platform_data = &tmu01_platform_data,
281 .resource = tmu01_resources,
282 .num_resources = ARRAY_SIZE(tmu01_resources),
286 static struct resource iic0_resources[] = {
290 .end = 0xFFF20425 - 1,
291 .flags = IORESOURCE_MEM,
294 .start = intcs_evt2irq(0xe00), /* IIC0_ALI0 */
295 .end = intcs_evt2irq(0xe60), /* IIC0_DTEI0 */
296 .flags = IORESOURCE_IRQ,
300 static struct platform_device iic0_device = {
301 .name = "i2c-sh_mobile",
302 .id = 0, /* "i2c0" clock */
303 .num_resources = ARRAY_SIZE(iic0_resources),
304 .resource = iic0_resources,
307 static struct resource iic1_resources[] = {
311 .end = 0xE6C20425 - 1,
312 .flags = IORESOURCE_MEM,
315 .start = evt2irq(0x780), /* IIC1_ALI1 */
316 .end = evt2irq(0x7e0), /* IIC1_DTEI1 */
317 .flags = IORESOURCE_IRQ,
321 static struct platform_device iic1_device = {
322 .name = "i2c-sh_mobile",
323 .id = 1, /* "i2c1" clock */
324 .num_resources = ARRAY_SIZE(iic1_resources),
325 .resource = iic1_resources,
329 /* Transmit sizes and respective CHCR register values */
340 /* log2(size / 8) - used to calculate number of transfers */
342 [XMIT_SZ_8BIT] = 0, \
343 [XMIT_SZ_16BIT] = 1, \
344 [XMIT_SZ_32BIT] = 2, \
345 [XMIT_SZ_64BIT] = 3, \
346 [XMIT_SZ_128BIT] = 4, \
347 [XMIT_SZ_256BIT] = 5, \
348 [XMIT_SZ_512BIT] = 6, \
351 #define TS_INDEX2VAL(i) ((((i) & 3) << 3) | \
352 (((i) & 0xc) << (20 - 2)))
354 static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
356 .slave_id = SHDMA_SLAVE_SCIF0_TX,
358 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
361 .slave_id = SHDMA_SLAVE_SCIF0_RX,
363 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
366 .slave_id = SHDMA_SLAVE_SCIF1_TX,
368 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
371 .slave_id = SHDMA_SLAVE_SCIF1_RX,
373 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
376 .slave_id = SHDMA_SLAVE_SCIF2_TX,
378 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
381 .slave_id = SHDMA_SLAVE_SCIF2_RX,
383 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
386 .slave_id = SHDMA_SLAVE_SCIF3_TX,
388 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
391 .slave_id = SHDMA_SLAVE_SCIF3_RX,
393 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
396 .slave_id = SHDMA_SLAVE_SCIF4_TX,
398 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
401 .slave_id = SHDMA_SLAVE_SCIF4_RX,
403 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
406 .slave_id = SHDMA_SLAVE_SCIF5_TX,
408 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
411 .slave_id = SHDMA_SLAVE_SCIF5_RX,
413 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
416 .slave_id = SHDMA_SLAVE_SCIF6_TX,
418 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
421 .slave_id = SHDMA_SLAVE_SCIF6_RX,
423 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
426 .slave_id = SHDMA_SLAVE_SDHI0_TX,
428 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
431 .slave_id = SHDMA_SLAVE_SDHI0_RX,
433 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
436 .slave_id = SHDMA_SLAVE_SDHI1_TX,
438 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
441 .slave_id = SHDMA_SLAVE_SDHI1_RX,
443 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
446 .slave_id = SHDMA_SLAVE_SDHI2_TX,
448 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
451 .slave_id = SHDMA_SLAVE_SDHI2_RX,
453 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
456 .slave_id = SHDMA_SLAVE_MMCIF_TX,
458 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
461 .slave_id = SHDMA_SLAVE_MMCIF_RX,
463 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
468 #define SH7372_CHCLR 0x220
470 static const struct sh_dmae_channel sh7372_dmae_channels[] = {
475 .chclr_offset = SH7372_CHCLR + 0,
480 .chclr_offset = SH7372_CHCLR + 0x10,
485 .chclr_offset = SH7372_CHCLR + 0x20,
490 .chclr_offset = SH7372_CHCLR + 0x30,
495 .chclr_offset = SH7372_CHCLR + 0x50,
500 .chclr_offset = SH7372_CHCLR + 0x60,
504 static const unsigned int ts_shift[] = TS_SHIFT;
506 static struct sh_dmae_pdata dma_platform_data = {
507 .slave = sh7372_dmae_slaves,
508 .slave_num = ARRAY_SIZE(sh7372_dmae_slaves),
509 .channel = sh7372_dmae_channels,
510 .channel_num = ARRAY_SIZE(sh7372_dmae_channels),
513 .ts_high_shift = (20 - 2), /* 2 bits for shifted low TS */
514 .ts_high_mask = 0x00300000,
515 .ts_shift = ts_shift,
516 .ts_shift_num = ARRAY_SIZE(ts_shift),
517 .dmaor_init = DMAOR_DME,
521 /* Resource order important! */
522 static struct resource sh7372_dmae0_resources[] = {
524 /* Channel registers and DMAOR */
527 .flags = IORESOURCE_MEM,
533 .flags = IORESOURCE_MEM,
537 .start = evt2irq(0x20c0),
538 .end = evt2irq(0x20c0),
539 .flags = IORESOURCE_IRQ,
542 /* IRQ for channels 0-5 */
543 .start = evt2irq(0x2000),
544 .end = evt2irq(0x20a0),
545 .flags = IORESOURCE_IRQ,
549 /* Resource order important! */
550 static struct resource sh7372_dmae1_resources[] = {
552 /* Channel registers and DMAOR */
555 .flags = IORESOURCE_MEM,
561 .flags = IORESOURCE_MEM,
565 .start = evt2irq(0x21c0),
566 .end = evt2irq(0x21c0),
567 .flags = IORESOURCE_IRQ,
570 /* IRQ for channels 0-5 */
571 .start = evt2irq(0x2100),
572 .end = evt2irq(0x21a0),
573 .flags = IORESOURCE_IRQ,
577 /* Resource order important! */
578 static struct resource sh7372_dmae2_resources[] = {
580 /* Channel registers and DMAOR */
583 .flags = IORESOURCE_MEM,
589 .flags = IORESOURCE_MEM,
593 .start = evt2irq(0x22c0),
594 .end = evt2irq(0x22c0),
595 .flags = IORESOURCE_IRQ,
598 /* IRQ for channels 0-5 */
599 .start = evt2irq(0x2200),
600 .end = evt2irq(0x22a0),
601 .flags = IORESOURCE_IRQ,
605 static struct platform_device dma0_device = {
606 .name = "sh-dma-engine",
608 .resource = sh7372_dmae0_resources,
609 .num_resources = ARRAY_SIZE(sh7372_dmae0_resources),
611 .platform_data = &dma_platform_data,
615 static struct platform_device dma1_device = {
616 .name = "sh-dma-engine",
618 .resource = sh7372_dmae1_resources,
619 .num_resources = ARRAY_SIZE(sh7372_dmae1_resources),
621 .platform_data = &dma_platform_data,
625 static struct platform_device dma2_device = {
626 .name = "sh-dma-engine",
628 .resource = sh7372_dmae2_resources,
629 .num_resources = ARRAY_SIZE(sh7372_dmae2_resources),
631 .platform_data = &dma_platform_data,
639 unsigned int usbts_shift[] = {3, 4, 5};
647 #define USBTS_INDEX2VAL(i) (((i) & 3) << 6)
649 static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = {
658 static const struct sh_dmae_slave_config sh7372_usb_dmae0_slaves[] = {
660 .slave_id = SHDMA_SLAVE_USB0_TX,
661 .chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
663 .slave_id = SHDMA_SLAVE_USB0_RX,
664 .chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
668 static struct sh_dmae_pdata usb_dma0_platform_data = {
669 .slave = sh7372_usb_dmae0_slaves,
670 .slave_num = ARRAY_SIZE(sh7372_usb_dmae0_slaves),
671 .channel = sh7372_usb_dmae_channels,
672 .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
677 .ts_shift = usbts_shift,
678 .ts_shift_num = ARRAY_SIZE(usbts_shift),
679 .dmaor_init = DMAOR_DME,
681 .chcr_ie_bit = 1 << 5,
688 static struct resource sh7372_usb_dmae0_resources[] = {
690 /* Channel registers and DMAOR */
692 .end = 0xe68a0064 - 1,
693 .flags = IORESOURCE_MEM,
698 .end = 0xe68a0014 - 1,
699 .flags = IORESOURCE_MEM,
702 /* IRQ for channels */
703 .start = evt2irq(0x0a00),
704 .end = evt2irq(0x0a00),
705 .flags = IORESOURCE_IRQ,
709 static struct platform_device usb_dma0_device = {
710 .name = "sh-dma-engine",
712 .resource = sh7372_usb_dmae0_resources,
713 .num_resources = ARRAY_SIZE(sh7372_usb_dmae0_resources),
715 .platform_data = &usb_dma0_platform_data,
720 static const struct sh_dmae_slave_config sh7372_usb_dmae1_slaves[] = {
722 .slave_id = SHDMA_SLAVE_USB1_TX,
723 .chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
725 .slave_id = SHDMA_SLAVE_USB1_RX,
726 .chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
730 static struct sh_dmae_pdata usb_dma1_platform_data = {
731 .slave = sh7372_usb_dmae1_slaves,
732 .slave_num = ARRAY_SIZE(sh7372_usb_dmae1_slaves),
733 .channel = sh7372_usb_dmae_channels,
734 .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
739 .ts_shift = usbts_shift,
740 .ts_shift_num = ARRAY_SIZE(usbts_shift),
741 .dmaor_init = DMAOR_DME,
743 .chcr_ie_bit = 1 << 5,
750 static struct resource sh7372_usb_dmae1_resources[] = {
752 /* Channel registers and DMAOR */
754 .end = 0xe68c0064 - 1,
755 .flags = IORESOURCE_MEM,
760 .end = 0xe68c0014 - 1,
761 .flags = IORESOURCE_MEM,
764 /* IRQ for channels */
765 .start = evt2irq(0x1d00),
766 .end = evt2irq(0x1d00),
767 .flags = IORESOURCE_IRQ,
771 static struct platform_device usb_dma1_device = {
772 .name = "sh-dma-engine",
774 .resource = sh7372_usb_dmae1_resources,
775 .num_resources = ARRAY_SIZE(sh7372_usb_dmae1_resources),
777 .platform_data = &usb_dma1_platform_data,
782 static struct uio_info vpu_platform_data = {
785 .irq = intcs_evt2irq(0x980),
788 static struct resource vpu_resources[] = {
793 .flags = IORESOURCE_MEM,
797 static struct platform_device vpu_device = {
798 .name = "uio_pdrv_genirq",
801 .platform_data = &vpu_platform_data,
803 .resource = vpu_resources,
804 .num_resources = ARRAY_SIZE(vpu_resources),
808 static struct uio_info veu0_platform_data = {
811 .irq = intcs_evt2irq(0x700),
814 static struct resource veu0_resources[] = {
819 .flags = IORESOURCE_MEM,
823 static struct platform_device veu0_device = {
824 .name = "uio_pdrv_genirq",
827 .platform_data = &veu0_platform_data,
829 .resource = veu0_resources,
830 .num_resources = ARRAY_SIZE(veu0_resources),
834 static struct uio_info veu1_platform_data = {
837 .irq = intcs_evt2irq(0x720),
840 static struct resource veu1_resources[] = {
845 .flags = IORESOURCE_MEM,
849 static struct platform_device veu1_device = {
850 .name = "uio_pdrv_genirq",
853 .platform_data = &veu1_platform_data,
855 .resource = veu1_resources,
856 .num_resources = ARRAY_SIZE(veu1_resources),
860 static struct uio_info veu2_platform_data = {
863 .irq = intcs_evt2irq(0x740),
866 static struct resource veu2_resources[] = {
871 .flags = IORESOURCE_MEM,
875 static struct platform_device veu2_device = {
876 .name = "uio_pdrv_genirq",
879 .platform_data = &veu2_platform_data,
881 .resource = veu2_resources,
882 .num_resources = ARRAY_SIZE(veu2_resources),
886 static struct uio_info veu3_platform_data = {
889 .irq = intcs_evt2irq(0x760),
892 static struct resource veu3_resources[] = {
897 .flags = IORESOURCE_MEM,
901 static struct platform_device veu3_device = {
902 .name = "uio_pdrv_genirq",
905 .platform_data = &veu3_platform_data,
907 .resource = veu3_resources,
908 .num_resources = ARRAY_SIZE(veu3_resources),
912 static struct uio_info jpu_platform_data = {
915 .irq = intcs_evt2irq(0x560),
918 static struct resource jpu_resources[] = {
923 .flags = IORESOURCE_MEM,
927 static struct platform_device jpu_device = {
928 .name = "uio_pdrv_genirq",
931 .platform_data = &jpu_platform_data,
933 .resource = jpu_resources,
934 .num_resources = ARRAY_SIZE(jpu_resources),
938 static struct uio_info spu0_platform_data = {
941 .irq = evt2irq(0x1800),
944 static struct resource spu0_resources[] = {
949 .flags = IORESOURCE_MEM,
953 static struct platform_device spu0_device = {
954 .name = "uio_pdrv_genirq",
957 .platform_data = &spu0_platform_data,
959 .resource = spu0_resources,
960 .num_resources = ARRAY_SIZE(spu0_resources),
964 static struct uio_info spu1_platform_data = {
967 .irq = evt2irq(0x1820),
970 static struct resource spu1_resources[] = {
975 .flags = IORESOURCE_MEM,
979 static struct platform_device spu1_device = {
980 .name = "uio_pdrv_genirq",
983 .platform_data = &spu1_platform_data,
985 .resource = spu1_resources,
986 .num_resources = ARRAY_SIZE(spu1_resources),
989 static struct platform_device *sh7372_early_devices[] __initdata = {
1002 static struct platform_device *sh7372_late_devices[] __initdata = {
1020 void __init sh7372_add_standard_devices(void)
1022 sh7372_init_pm_domain(&sh7372_a4lc);
1023 sh7372_init_pm_domain(&sh7372_a4mp);
1024 sh7372_init_pm_domain(&sh7372_d4);
1025 sh7372_init_pm_domain(&sh7372_a4r);
1026 sh7372_init_pm_domain(&sh7372_a3rv);
1027 sh7372_init_pm_domain(&sh7372_a3ri);
1028 sh7372_init_pm_domain(&sh7372_a4s);
1029 sh7372_init_pm_domain(&sh7372_a3sp);
1030 sh7372_init_pm_domain(&sh7372_a3sg);
1032 sh7372_pm_add_subdomain(&sh7372_a4lc, &sh7372_a3rv);
1033 sh7372_pm_add_subdomain(&sh7372_a4r, &sh7372_a4lc);
1035 sh7372_pm_add_subdomain(&sh7372_a4s, &sh7372_a3sg);
1036 sh7372_pm_add_subdomain(&sh7372_a4s, &sh7372_a3sp);
1038 platform_add_devices(sh7372_early_devices,
1039 ARRAY_SIZE(sh7372_early_devices));
1041 platform_add_devices(sh7372_late_devices,
1042 ARRAY_SIZE(sh7372_late_devices));
1044 sh7372_add_device_to_domain(&sh7372_a3rv, &vpu_device);
1045 sh7372_add_device_to_domain(&sh7372_a4mp, &spu0_device);
1046 sh7372_add_device_to_domain(&sh7372_a4mp, &spu1_device);
1047 sh7372_add_device_to_domain(&sh7372_a3sp, &scif0_device);
1048 sh7372_add_device_to_domain(&sh7372_a3sp, &scif1_device);
1049 sh7372_add_device_to_domain(&sh7372_a3sp, &scif2_device);
1050 sh7372_add_device_to_domain(&sh7372_a3sp, &scif3_device);
1051 sh7372_add_device_to_domain(&sh7372_a3sp, &scif4_device);
1052 sh7372_add_device_to_domain(&sh7372_a3sp, &scif5_device);
1053 sh7372_add_device_to_domain(&sh7372_a3sp, &scif6_device);
1054 sh7372_add_device_to_domain(&sh7372_a3sp, &iic1_device);
1055 sh7372_add_device_to_domain(&sh7372_a3sp, &dma0_device);
1056 sh7372_add_device_to_domain(&sh7372_a3sp, &dma1_device);
1057 sh7372_add_device_to_domain(&sh7372_a3sp, &dma2_device);
1058 sh7372_add_device_to_domain(&sh7372_a3sp, &usb_dma0_device);
1059 sh7372_add_device_to_domain(&sh7372_a3sp, &usb_dma1_device);
1060 sh7372_add_device_to_domain(&sh7372_a4r, &iic0_device);
1061 sh7372_add_device_to_domain(&sh7372_a4r, &veu0_device);
1062 sh7372_add_device_to_domain(&sh7372_a4r, &veu1_device);
1063 sh7372_add_device_to_domain(&sh7372_a4r, &veu2_device);
1064 sh7372_add_device_to_domain(&sh7372_a4r, &veu3_device);
1065 sh7372_add_device_to_domain(&sh7372_a4r, &jpu_device);
1068 static void __init sh7372_earlytimer_init(void)
1070 sh7372_clock_init();
1071 shmobile_earlytimer_init();
1074 void __init sh7372_add_early_devices(void)
1076 early_platform_add_devices(sh7372_early_devices,
1077 ARRAY_SIZE(sh7372_early_devices));
1079 /* setup early console here as well */
1080 shmobile_setup_console();
1082 /* override timer setup with soc-specific code */
1083 shmobile_timer.init = sh7372_earlytimer_init;