arch/arm/mach-shmobile/pm-sh7372.c

   1 /*
   2  * sh7372 Power management support
   3  *
   4  *  Copyright (C) 2011 Magnus Damm
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10
  11 #include <linux/pm.h>
  12 #include <linux/suspend.h>
  13 #include <linux/cpuidle.h>
  14 #include <linux/module.h>
  15 #include <linux/list.h>
  16 #include <linux/err.h>
  17 #include <linux/slab.h>
  18 #include <linux/pm_runtime.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/delay.h>
  21 #include <asm/system.h>
  22 #include <asm/io.h>
  23 #include <asm/tlbflush.h>
  24 #include <mach/common.h>
  25 #include <mach/sh7372.h>
  26
  27 #define SMFRAM 0xe6a70000
  28 #define SYSTBCR 0xe6150024
  29 #define SBAR 0xe6180020
  30 #define APARMBAREA 0xe6f10020
  31
  32 #define SPDCR 0xe6180008
  33 #define SWUCR 0xe6180014
  34 #define PSTR 0xe6180080
  35
  36 #define PSTR_RETRIES 100
  37 #define PSTR_DELAY_US 10
  38
  39 #ifdef CONFIG_PM
  40
  41 static int pd_power_down(struct generic_pm_domain *genpd)
  42 {
  43         struct sh7372_pm_domain *sh7372_pd = to_sh7372_pd(genpd);
  44         unsigned int mask = 1 << sh7372_pd->bit_shift;
  45
  46         if (__raw_readl(PSTR) & mask) {
  47                 unsigned int retry_count;
  48
  49                 __raw_writel(mask, SPDCR);
  50
  51                 for (retry_count = PSTR_RETRIES; retry_count; retry_count--) {
  52                         if (!(__raw_readl(SPDCR) & mask))
  53                                 break;
  54                         cpu_relax();
  55                 }
  56         }
  57
  58         pr_debug("sh7372 power domain down 0x%08x -> PSTR = 0x%08x\n",
  59                  mask, __raw_readl(PSTR));
  60
  61         return 0;
  62 }
  63
  64 static int pd_power_up(struct generic_pm_domain *genpd)
  65 {
  66         struct sh7372_pm_domain *sh7372_pd = to_sh7372_pd(genpd);
  67         unsigned int mask = 1 << sh7372_pd->bit_shift;
  68         unsigned int retry_count;
  69         int ret = 0;
  70
  71         if (__raw_readl(PSTR) & mask)
  72                 goto out;
  73
  74         __raw_writel(mask, SWUCR);
  75
  76         for (retry_count = 2 * PSTR_RETRIES; retry_count; retry_count--) {
  77                 if (!(__raw_readl(SWUCR) & mask))
  78                         goto out;
  79                 if (retry_count > PSTR_RETRIES)
  80                         udelay(PSTR_DELAY_US);
  81                 else
  82                         cpu_relax();
  83         }
  84         if (__raw_readl(SWUCR) & mask)
  85                 ret = -EIO;
  86
  87  out:
  88         pr_debug("sh7372 power domain up 0x%08x -> PSTR = 0x%08x\n",
  89                  mask, __raw_readl(PSTR));
  90
  91         return ret;
  92 }
  93
  94 static int pd_power_up_a3rv(struct generic_pm_domain *genpd)
  95 {
  96         int ret = pd_power_up(genpd);
  97
  98         /* force A4LC on after A3RV has been requested on */
  99         pm_genpd_poweron(&sh7372_a4lc.genpd);
 100
 101         return ret;
 102 }
 103
 104 static int pd_power_down_a3rv(struct generic_pm_domain *genpd)
 105 {
 106         int ret = pd_power_down(genpd);
 107
 108         /* try to power down A4LC after A3RV is requested off */
 109         pm_genpd_poweron(&sh7372_a4lc.genpd);
 110         queue_work(pm_wq, &sh7372_a4lc.genpd.power_off_work);
 111
 112         return ret;
 113 }
 114
 115 static int pd_power_down_a4lc(struct generic_pm_domain *genpd)
 116 {
 117         /* only power down A4LC if A3RV is off */
 118         if (!(__raw_readl(PSTR) & (1 << sh7372_a3rv.bit_shift)))
 119                 return pd_power_down(genpd);
 120
 121         return 0;
 122 }
 123
 124 static bool pd_active_wakeup(struct device *dev)
 125 {
 126         return true;
 127 }
 128
 129 void sh7372_init_pm_domain(struct sh7372_pm_domain *sh7372_pd)
 130 {
 131         struct generic_pm_domain *genpd = &sh7372_pd->genpd;
 132
 133         pm_genpd_init(genpd, NULL, false);
 134         genpd->stop_device = pm_clk_suspend;
 135         genpd->start_device = pm_clk_resume;
 136         genpd->active_wakeup = pd_active_wakeup;
 137
 138         if (sh7372_pd == &sh7372_a4lc) {
 139                 genpd->power_off = pd_power_down_a4lc;
 140                 genpd->power_on = pd_power_up;
 141         } else if (sh7372_pd == &sh7372_a3rv) {
 142                 genpd->power_off = pd_power_down_a3rv;
 143                 genpd->power_on = pd_power_up_a3rv;
 144         } else {
 145                 genpd->power_off = pd_power_down;
 146                 genpd->power_on = pd_power_up;
 147         }
 148         genpd->power_on(&sh7372_pd->genpd);
 149 }
 150
 151 void sh7372_add_device_to_domain(struct sh7372_pm_domain *sh7372_pd,
 152                                  struct platform_device *pdev)
 153 {
 154         struct device *dev = &pdev->dev;
 155
 156         if (!dev->power.subsys_data) {
 157                 pm_clk_init(dev);
 158                 pm_clk_add(dev, NULL);
 159         }
 160         pm_genpd_add_device(&sh7372_pd->genpd, dev);
 161 }
 162
 163 struct sh7372_pm_domain sh7372_a4lc = {
 164         .bit_shift = 1,
 165 };
 166
 167 struct sh7372_pm_domain sh7372_a4mp = {
 168         .bit_shift = 2,
 169 };
 170
 171 struct sh7372_pm_domain sh7372_d4 = {
 172         .bit_shift = 3,
 173 };
 174
 175 struct sh7372_pm_domain sh7372_a3rv = {
 176         .bit_shift = 6,
 177 };
 178
 179 struct sh7372_pm_domain sh7372_a3ri = {
 180         .bit_shift = 8,
 181 };
 182
 183 struct sh7372_pm_domain sh7372_a3sg = {
 184         .bit_shift = 13,
 185 };
 186
 187 #endif /* CONFIG_PM */
 188
 189 static void sh7372_enter_core_standby(void)
 190 {
 191         void __iomem *smfram = (void __iomem *)SMFRAM;
 192
 193         __raw_writel(0, APARMBAREA); /* translate 4k */
 194         __raw_writel(__pa(sh7372_cpu_resume), SBAR); /* set reset vector */
 195         __raw_writel(0x10, SYSTBCR); /* enable core standby */
 196
 197         __raw_writel(0, smfram + 0x3c); /* clear page table address */
 198
 199         sh7372_cpu_suspend();
 200         cpu_init();
 201
 202         /* if page table address is non-NULL then we have been powered down */
 203         if (__raw_readl(smfram + 0x3c)) {
 204                 __raw_writel(__raw_readl(smfram + 0x40),
 205                              __va(__raw_readl(smfram + 0x3c)));
 206
 207                 flush_tlb_all();
 208                 set_cr(__raw_readl(smfram + 0x38));
 209         }
 210
 211         __raw_writel(0, SYSTBCR); /* disable core standby */
 212         __raw_writel(0, SBAR); /* disable reset vector translation */
 213 }
 214
 215 #ifdef CONFIG_CPU_IDLE
 216 static void sh7372_cpuidle_setup(struct cpuidle_device *dev)
 217 {
 218         struct cpuidle_state *state;
 219         int i = dev->state_count;
 220
 221         state = &dev->states[i];
 222         snprintf(state->name, CPUIDLE_NAME_LEN, "C2");
 223         strncpy(state->desc, "Core Standby Mode", CPUIDLE_DESC_LEN);
 224         state->exit_latency = 10;
 225         state->target_residency = 20 + 10;
 226         state->power_usage = 1; /* perhaps not */
 227         state->flags = 0;
 228         state->flags |= CPUIDLE_FLAG_TIME_VALID;
 229         shmobile_cpuidle_modes[i] = sh7372_enter_core_standby;
 230
 231         dev->state_count = i + 1;
 232 }
 233
 234 static void sh7372_cpuidle_init(void)
 235 {
 236         shmobile_cpuidle_setup = sh7372_cpuidle_setup;
 237 }
 238 #else
 239 static void sh7372_cpuidle_init(void) {}
 240 #endif
 241
 242 #ifdef CONFIG_SUSPEND
 243 static int sh7372_enter_suspend(suspend_state_t suspend_state)
 244 {
 245         sh7372_enter_core_standby();
 246         return 0;
 247 }
 248
 249 static void sh7372_suspend_init(void)
 250 {
 251         shmobile_suspend_ops.enter = sh7372_enter_suspend;
 252 }
 253 #else
 254 static void sh7372_suspend_init(void) {}
 255 #endif
 256
 257 #define DBGREG1 0xe6100020
 258 #define DBGREG9 0xe6100040
 259
 260 void __init sh7372_pm_init(void)
 261 {
 262         /* enable DBG hardware block to kick SYSC */
 263         __raw_writel(0x0000a500, DBGREG9);
 264         __raw_writel(0x0000a501, DBGREG9);
 265         __raw_writel(0x00000000, DBGREG1);
 266
 267         sh7372_suspend_init();
 268         sh7372_cpuidle_init();
 269 }