4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 #include <linux/kernel.h>
23 #include <linux/i2c.h>
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
26 #include <linux/irq.h>
27 #include <linux/platform_device.h>
28 #include <linux/gpio.h>
29 #include <linux/smsc911x.h>
30 #include <mach/common.h>
31 #include <asm/mach-types.h>
32 #include <asm/mach/arch.h>
33 #include <asm/mach/map.h>
34 #include <asm/mach/time.h>
35 #include <asm/hardware/cache-l2x0.h>
36 #include <mach/r8a7740.h>
37 #include <video/sh_mobile_lcdc.h>
40 * CS Address device note
41 *----------------------------------------------------------------
42 * 0 0x0000_0000 NOR Flash (64MB) SW12 : bit3 = OFF
43 * 2 0x0800_0000 ExtNOR (64MB) SW12 : bit3 = OFF
46 * 5B 0x1600_0000 SRAM (8MB)
47 * 6 0x1800_0000 FPGA (64K)
48 * 0x1801_0000 Ether (4KB)
49 * 0x1801_1000 USB (4KB)
56 *----------------------------------------------------------------------------
57 * ON NOR WriteProtect NAND WriteProtect CS0 ExtNOR / CS2 NOR
58 * OFF NOR Not WriteProtect NAND Not WriteProtect CS0 NOR / CS2 ExtNOR
83 #define BUSSWMR1 0x0070
84 #define BUSSWMR2 0x0072
85 #define BUSSWMR3 0x0074
86 #define BUSSWMR4 0x0076
89 #define DEVRSTCR1 0x10D0
90 #define DEVRSTCR2 0x10D2
95 #define FPGA_IRQ_BASE (512)
96 #define FPGA_IRQ0 (FPGA_IRQ_BASE)
97 #define FPGA_IRQ1 (FPGA_IRQ_BASE + 16)
98 #define FPGA_ETH_IRQ (FPGA_IRQ0 + 15)
99 static u16 bonito_fpga_read(u32 offset)
101 return __raw_readw(0xf0003000 + offset);
104 static void bonito_fpga_write(u32 offset, u16 val)
106 __raw_writew(val, 0xf0003000 + offset);
109 static void bonito_fpga_irq_disable(struct irq_data *data)
111 unsigned int irq = data->irq;
112 u32 addr = (irq < 1016) ? IRQMR0 : IRQMR1;
113 int shift = irq % 16;
115 bonito_fpga_write(addr, bonito_fpga_read(addr) | (1 << shift));
118 static void bonito_fpga_irq_enable(struct irq_data *data)
120 unsigned int irq = data->irq;
121 u32 addr = (irq < 1016) ? IRQMR0 : IRQMR1;
122 int shift = irq % 16;
124 bonito_fpga_write(addr, bonito_fpga_read(addr) & ~(1 << shift));
127 static struct irq_chip bonito_fpga_irq_chip __read_mostly = {
128 .name = "bonito FPGA",
129 .irq_mask = bonito_fpga_irq_disable,
130 .irq_unmask = bonito_fpga_irq_enable,
133 static void bonito_fpga_irq_demux(unsigned int irq, struct irq_desc *desc)
135 u32 val = bonito_fpga_read(IRQSR1) << 16 |
136 bonito_fpga_read(IRQSR0);
137 u32 mask = bonito_fpga_read(IRQMR1) << 16 |
138 bonito_fpga_read(IRQMR0);
144 for (i = 0; i < 32; i++) {
145 if (!(val & (1 << i)))
148 generic_handle_irq(FPGA_IRQ_BASE + i);
152 static void bonito_fpga_init(void)
156 bonito_fpga_write(IRQMR0, 0xffff); /* mask all */
157 bonito_fpga_write(IRQMR1, 0xffff); /* mask all */
160 bonito_fpga_write(DEVRSTCR1,
163 /* FPGA irq require special handling */
164 for (i = FPGA_IRQ_BASE; i < FPGA_IRQ_BASE + 32; i++) {
165 irq_set_chip_and_handler_name(i, &bonito_fpga_irq_chip,
166 handle_level_irq, "level");
167 set_irq_flags(i, IRQF_VALID); /* yuck */
170 irq_set_chained_handler(evt2irq(0x0340), bonito_fpga_irq_demux);
171 irq_set_irq_type(evt2irq(0x0340), IRQ_TYPE_LEVEL_LOW);
179 * bonito board needs some settings by pmic which use i2c access.
180 * pmic settings use device_initcall() here for use it.
182 static __u8 *pmic_settings = NULL;
183 static __u8 pmic_do_2A[] = {
189 static int __init pmic_init(void)
191 struct i2c_adapter *a = i2c_get_adapter(0);
206 for (i = 0; ; i += 2) {
207 buf[0] = pmic_settings[i + 0];
208 buf[1] = pmic_settings[i + 1];
210 if ((0xff == buf[0]) && (0xff == buf[1]))
213 ret = i2c_transfer(a, &msg, 1);
215 pr_err("i2c transfer fail\n");
222 device_initcall(pmic_init);
227 static const struct fb_videomode lcdc0_mode = {
228 .name = "WVGA Panel",
240 static struct sh_mobile_lcdc_info lcdc0_info = {
241 .clock_source = LCDC_CLK_BUS,
243 .chan = LCDC_CHAN_MAINLCD,
245 .interface_type = RGB24,
248 .lcd_cfg = &lcdc0_mode,
257 static struct resource lcdc0_resources[] = {
262 .flags = IORESOURCE_MEM,
265 .start = intcs_evt2irq(0x0580),
266 .flags = IORESOURCE_IRQ,
270 static struct platform_device lcdc0_device = {
271 .name = "sh_mobile_lcdc_fb",
273 .resource = lcdc0_resources,
274 .num_resources = ARRAY_SIZE(lcdc0_resources),
276 .platform_data = &lcdc0_info,
277 .coherent_dma_mask = ~0,
284 static struct resource smsc_resources[] = {
287 .end = 0x18011000 - 1,
288 .flags = IORESOURCE_MEM,
291 .start = FPGA_ETH_IRQ,
292 .flags = IORESOURCE_IRQ,
296 static struct smsc911x_platform_config smsc_platdata = {
297 .flags = SMSC911X_USE_16BIT,
298 .phy_interface = PHY_INTERFACE_MODE_MII,
299 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
300 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
303 static struct platform_device smsc_device = {
306 .platform_data = &smsc_platdata,
308 .resource = smsc_resources,
309 .num_resources = ARRAY_SIZE(smsc_resources),
315 static struct platform_device *bonito_core_devices[] __initdata = {
321 static struct platform_device *bonito_base_devices[] __initdata = {
329 static struct map_desc bonito_io_desc[] __initdata = {
331 * for FPGA (0x1800000-0x19ffffff)
332 * 0x18000000-0x18002000 -> 0xf0003000-0xf0005000
335 .virtual = 0xf0003000,
336 .pfn = __phys_to_pfn(0x18000000),
337 .length = PAGE_SIZE * 2,
338 .type = MT_DEVICE_NONSHARED
342 static void __init bonito_map_io(void)
345 iotable_init(bonito_io_desc, ARRAY_SIZE(bonito_io_desc));
351 #define BIT_ON(sw, bit) (sw & (1 << bit))
352 #define BIT_OFF(sw, bit) (!(sw & (1 << bit)))
354 #define VCCQ1CR 0xE6058140
355 #define VCCQ1LCDCR 0xE6058186
357 static void __init bonito_init(void)
361 r8a7740_pinmux_init();
364 pmic_settings = pmic_do_2A;
367 * core board settings
370 #ifdef CONFIG_CACHE_L2X0
371 /* Early BRESP enable, Shared attribute override enable, 32K*8way */
372 l2x0_init(__io(0xf0002000), 0x40440000, 0x82000fff);
375 r8a7740_add_standard_devices();
377 platform_add_devices(bonito_core_devices,
378 ARRAY_SIZE(bonito_core_devices));
381 * base board settings
383 gpio_request(GPIO_PORT176, NULL);
384 gpio_direction_input(GPIO_PORT176);
385 if (!gpio_get_value(GPIO_PORT176)) {
393 gpio_request(GPIO_FN_CS5B, NULL);
394 gpio_request(GPIO_FN_CS6A, NULL);
395 gpio_request(GPIO_FN_CS5A_PORT105, NULL);
396 gpio_request(GPIO_FN_IRQ10, NULL);
398 val = bonito_fpga_read(BVERR);
399 pr_info("bonito version: cpu %02x, base %02x\n",
401 ((val >> 0) & 0xFF));
403 bsw2 = bonito_fpga_read(BUSSWMR2);
404 bsw3 = bonito_fpga_read(BUSSWMR3);
405 bsw4 = bonito_fpga_read(BUSSWMR4);
410 if (BIT_OFF(bsw2, 1) && /* S38.3 = ON */
411 BIT_OFF(bsw3, 9) && /* S39.6 = ON */
412 BIT_OFF(bsw4, 4)) { /* S43.1 = ON */
413 gpio_request(GPIO_FN_SCIFA5_TXD_PORT91, NULL);
414 gpio_request(GPIO_FN_SCIFA5_RXD_PORT92, NULL);
420 if (BIT_ON(bsw2, 3) && /* S38.1 = OFF */
421 BIT_ON(bsw2, 2)) { /* S38.2 = OFF */
422 gpio_request(GPIO_FN_LCDC0_SELECT, NULL);
423 gpio_request(GPIO_FN_LCD0_D0, NULL);
424 gpio_request(GPIO_FN_LCD0_D1, NULL);
425 gpio_request(GPIO_FN_LCD0_D2, NULL);
426 gpio_request(GPIO_FN_LCD0_D3, NULL);
427 gpio_request(GPIO_FN_LCD0_D4, NULL);
428 gpio_request(GPIO_FN_LCD0_D5, NULL);
429 gpio_request(GPIO_FN_LCD0_D6, NULL);
430 gpio_request(GPIO_FN_LCD0_D7, NULL);
431 gpio_request(GPIO_FN_LCD0_D8, NULL);
432 gpio_request(GPIO_FN_LCD0_D9, NULL);
433 gpio_request(GPIO_FN_LCD0_D10, NULL);
434 gpio_request(GPIO_FN_LCD0_D11, NULL);
435 gpio_request(GPIO_FN_LCD0_D12, NULL);
436 gpio_request(GPIO_FN_LCD0_D13, NULL);
437 gpio_request(GPIO_FN_LCD0_D14, NULL);
438 gpio_request(GPIO_FN_LCD0_D15, NULL);
439 gpio_request(GPIO_FN_LCD0_D16, NULL);
440 gpio_request(GPIO_FN_LCD0_D17, NULL);
441 gpio_request(GPIO_FN_LCD0_D18_PORT163, NULL);
442 gpio_request(GPIO_FN_LCD0_D19_PORT162, NULL);
443 gpio_request(GPIO_FN_LCD0_D20_PORT161, NULL);
444 gpio_request(GPIO_FN_LCD0_D21_PORT158, NULL);
445 gpio_request(GPIO_FN_LCD0_D22_PORT160, NULL);
446 gpio_request(GPIO_FN_LCD0_D23_PORT159, NULL);
447 gpio_request(GPIO_FN_LCD0_DCK, NULL);
448 gpio_request(GPIO_FN_LCD0_VSYN, NULL);
449 gpio_request(GPIO_FN_LCD0_HSYN, NULL);
450 gpio_request(GPIO_FN_LCD0_DISP, NULL);
451 gpio_request(GPIO_FN_LCD0_LCLK_PORT165, NULL);
453 gpio_request(GPIO_PORT61, NULL); /* LCDDON */
454 gpio_direction_output(GPIO_PORT61, 1);
457 bonito_fpga_write(LCDCR, 1);
459 /* drivability Max */
460 __raw_writew(0x00FF , VCCQ1LCDCR);
461 __raw_writew(0xFFFF , VCCQ1CR);
464 platform_add_devices(bonito_base_devices,
465 ARRAY_SIZE(bonito_base_devices));
469 static void __init bonito_timer_init(void)
474 /* read MD_CK value */
475 val = bonito_fpga_read(A1MDSR);
483 r8a7740_clock_init(md_ck);
484 shmobile_timer.init();
487 struct sys_timer bonito_timer = {
488 .init = bonito_timer_init,
491 MACHINE_START(BONITO, "bonito")
492 .map_io = bonito_map_io,
493 .init_early = r8a7740_add_early_devices,
494 .init_irq = r8a7740_init_irq,
495 .handle_irq = shmobile_handle_irq_intc,
496 .init_machine = bonito_init,
497 .timer = &bonito_timer,