1 /* linux/arch/arm/mach-s5pv310/irq-eint.c
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * S5PV310 - IRQ EINT support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/kernel.h>
14 #include <linux/interrupt.h>
15 #include <linux/irq.h>
17 #include <linux/sysdev.h>
18 #include <linux/gpio.h>
22 #include <plat/gpio-cfg.h>
24 #include <mach/regs-gpio.h>
26 static DEFINE_SPINLOCK(eint_lock);
28 static unsigned int eint0_15_data[16];
30 static unsigned int s5pv310_get_irq_nr(unsigned int number)
36 ret = (number + IRQ_EINT0);
39 ret = (number + (IRQ_EINT4 - 4));
42 ret = (number + (IRQ_EINT8 - 8));
45 printk(KERN_ERR "number available : %d\n", number);
51 static inline void s5pv310_irq_eint_mask(struct irq_data *data)
55 spin_lock(&eint_lock);
56 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
57 mask |= eint_irq_to_bit(data->irq);
58 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
59 spin_unlock(&eint_lock);
62 static void s5pv310_irq_eint_unmask(struct irq_data *data)
66 spin_lock(&eint_lock);
67 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
68 mask &= ~(eint_irq_to_bit(data->irq));
69 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
70 spin_unlock(&eint_lock);
73 static inline void s5pv310_irq_eint_ack(struct irq_data *data)
75 __raw_writel(eint_irq_to_bit(data->irq),
76 S5P_EINT_PEND(EINT_REG_NR(data->irq)));
79 static void s5pv310_irq_eint_maskack(struct irq_data *data)
81 s5pv310_irq_eint_mask(data);
82 s5pv310_irq_eint_ack(data);
85 static int s5pv310_irq_eint_set_type(struct irq_data *data, unsigned int type)
87 int offs = EINT_OFFSET(data->irq);
93 case IRQ_TYPE_EDGE_RISING:
94 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
97 case IRQ_TYPE_EDGE_FALLING:
98 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
101 case IRQ_TYPE_EDGE_BOTH:
102 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
105 case IRQ_TYPE_LEVEL_LOW:
106 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
109 case IRQ_TYPE_LEVEL_HIGH:
110 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
114 printk(KERN_ERR "No such irq type %d", type);
118 shift = (offs & 0x7) * 4;
121 spin_lock(&eint_lock);
122 ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
124 ctrl |= newvalue << shift;
125 __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
126 spin_unlock(&eint_lock);
130 s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
133 s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
136 s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
139 s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
142 printk(KERN_ERR "No such irq number %d", offs);
148 static struct irq_chip s5pv310_irq_eint = {
149 .name = "s5pv310-eint",
150 .irq_mask = s5pv310_irq_eint_mask,
151 .irq_unmask = s5pv310_irq_eint_unmask,
152 .irq_mask_ack = s5pv310_irq_eint_maskack,
153 .irq_ack = s5pv310_irq_eint_ack,
154 .irq_set_type = s5pv310_irq_eint_set_type,
156 .irq_set_wake = s3c_irqext_wake,
160 /* s5pv310_irq_demux_eint
162 * This function demuxes the IRQ from from EINTs 16 to 31.
163 * It is designed to be inlined into the specific handler
164 * s5p_irq_demux_eintX_Y.
166 * Each EINT pend/mask registers handle eight of them.
168 static inline void s5pv310_irq_demux_eint(unsigned int start)
172 u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
173 u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
179 irq = fls(status) - 1;
180 generic_handle_irq(irq + start);
181 status &= ~(1 << irq);
185 static void s5pv310_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
187 s5pv310_irq_demux_eint(IRQ_EINT(16));
188 s5pv310_irq_demux_eint(IRQ_EINT(24));
191 static void s5pv310_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
193 u32 *irq_data = get_irq_data(irq);
194 struct irq_chip *chip = get_irq_chip(irq);
196 chip->irq_mask(&desc->irq_data);
199 chip->irq_ack(&desc->irq_data);
201 generic_handle_irq(*irq_data);
203 chip->irq_unmask(&desc->irq_data);
206 int __init s5pv310_init_irq_eint(void)
210 for (irq = 0 ; irq <= 31 ; irq++) {
211 set_irq_chip(IRQ_EINT(irq), &s5pv310_irq_eint);
212 set_irq_handler(IRQ_EINT(irq), handle_level_irq);
213 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
216 set_irq_chained_handler(IRQ_EINT16_31, s5pv310_irq_demux_eint16_31);
218 for (irq = 0 ; irq <= 15 ; irq++) {
219 eint0_15_data[irq] = IRQ_EINT(irq);
221 set_irq_data(s5pv310_get_irq_nr(irq), &eint0_15_data[irq]);
222 set_irq_chained_handler(s5pv310_get_irq_nr(irq),
223 s5pv310_irq_eint0_15);
229 arch_initcall(s5pv310_init_irq_eint);