1 /* linux/arch/arm/mach-s5pv210/clock.c
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
6 * S5PV210 - Clock support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/list.h>
17 #include <linux/errno.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
20 #include <linux/sysdev.h>
25 #include <plat/cpu-freq.h>
26 #include <mach/regs-clock.h>
27 #include <plat/clock.h>
30 #include <plat/s5p-clock.h>
31 #include <plat/clock-clksrc.h>
32 #include <plat/s5pv210.h>
34 static struct clksrc_clk clk_mout_apll = {
39 .sources = &clk_src_apll,
40 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
43 static struct clksrc_clk clk_mout_epll = {
48 .sources = &clk_src_epll,
49 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
52 static struct clksrc_clk clk_mout_mpll = {
57 .sources = &clk_src_mpll,
58 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
61 static struct clk *clkset_armclk_list[] = {
62 [0] = &clk_mout_apll.clk,
63 [1] = &clk_mout_mpll.clk,
66 static struct clksrc_sources clkset_armclk = {
67 .sources = clkset_armclk_list,
68 .nr_sources = ARRAY_SIZE(clkset_armclk_list),
71 static struct clksrc_clk clk_armclk = {
76 .sources = &clkset_armclk,
77 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
78 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 },
81 static struct clksrc_clk clk_hclk_msys = {
85 .parent = &clk_armclk.clk,
87 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
90 static struct clksrc_clk clk_sclk_a2m = {
94 .parent = &clk_mout_apll.clk,
96 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
99 static struct clk *clkset_hclk_sys_list[] = {
100 [0] = &clk_mout_mpll.clk,
101 [1] = &clk_sclk_a2m.clk,
104 static struct clksrc_sources clkset_hclk_sys = {
105 .sources = clkset_hclk_sys_list,
106 .nr_sources = ARRAY_SIZE(clkset_hclk_sys_list),
109 static struct clksrc_clk clk_hclk_dsys = {
114 .sources = &clkset_hclk_sys,
115 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
116 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 },
119 static struct clksrc_clk clk_hclk_psys = {
124 .sources = &clkset_hclk_sys,
125 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
126 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 },
129 static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable)
131 return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
134 static int s5pv210_clk_ip1_ctrl(struct clk *clk, int enable)
136 return s5p_gatectrl(S5P_CLKGATE_IP1, clk, enable);
139 static int s5pv210_clk_ip2_ctrl(struct clk *clk, int enable)
141 return s5p_gatectrl(S5P_CLKGATE_IP2, clk, enable);
144 static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable)
146 return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
149 static struct clk clk_h100 = {
154 static struct clk clk_p100 = {
159 static struct clk clk_p83 = {
164 static struct clk clk_p66 = {
169 static struct clk *sys_clks[] = {
176 static struct clk init_clocks_disable[] = {
180 .parent = &clk_hclk_dsys.clk,
181 .enable = s5pv210_clk_ip0_ctrl,
186 .parent = &clk_hclk_psys.clk,
187 .enable = s5pv210_clk_ip1_ctrl,
192 .parent = &clk_hclk_psys.clk,
193 .enable = s5pv210_clk_ip1_ctrl,
198 .parent = &clk_hclk_dsys.clk,
199 .enable = s5pv210_clk_ip1_ctrl,
204 .parent = &clk_hclk_psys.clk,
205 .enable = s5pv210_clk_ip1_ctrl,
210 .parent = &clk_hclk_psys.clk,
211 .enable = s5pv210_clk_ip2_ctrl,
216 .parent = &clk_hclk_psys.clk,
217 .enable = s5pv210_clk_ip2_ctrl,
222 .parent = &clk_hclk_psys.clk,
223 .enable = s5pv210_clk_ip2_ctrl,
228 .parent = &clk_hclk_psys.clk,
229 .enable = s5pv210_clk_ip2_ctrl,
235 .enable = s5pv210_clk_ip3_ctrl,
241 .enable = s5pv210_clk_ip3_ctrl,
247 .enable = s5pv210_clk_ip3_ctrl,
253 .enable = s5pv210_clk_ip3_ctrl,
259 .enable = s5pv210_clk_ip3_ctrl,
265 .enable = s5pv210_clk_ip3_ctrl,
271 .enable = s5pv210_clk_ip3_ctrl,
277 .enable = s5pv210_clk_ip3_ctrl,
283 .enable = s5pv210_clk_ip3_ctrl,
289 .enable = s5pv210_clk_ip3_ctrl,
295 .enable = s5pv210_clk_ip3_ctrl,
301 .enable = s5pv210_clk_ip3_ctrl,
307 .enable = s5pv210_clk_ip3_ctrl,
313 .enable = s5pv210_clk_ip3_ctrl,
319 .enable = s5pv210_clk_ip3_ctrl,
324 static struct clk init_clocks[] = {
329 .enable = s5pv210_clk_ip3_ctrl,
335 .enable = s5pv210_clk_ip3_ctrl,
341 .enable = s5pv210_clk_ip3_ctrl,
347 .enable = s5pv210_clk_ip3_ctrl,
352 static struct clk *clkset_uart_list[] = {
353 [6] = &clk_mout_mpll.clk,
354 [7] = &clk_mout_epll.clk,
357 static struct clksrc_sources clkset_uart = {
358 .sources = clkset_uart_list,
359 .nr_sources = ARRAY_SIZE(clkset_uart_list),
362 static struct clksrc_clk clksrcs[] = {
368 .enable = s5pv210_clk_ip3_ctrl,
370 .sources = &clkset_uart,
371 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
372 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
376 /* Clock initialisation code */
377 static struct clksrc_clk *sysclks[] = {
388 #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
390 void __init_or_cpufreq s5pv210_setup_clocks(void)
392 struct clk *xtal_clk;
394 unsigned long armclk;
395 unsigned long hclk_msys;
396 unsigned long hclk_dsys;
397 unsigned long hclk_psys;
398 unsigned long pclk100;
399 unsigned long pclk83;
400 unsigned long pclk66;
405 u32 clkdiv0, clkdiv1;
407 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
409 clkdiv0 = __raw_readl(S5P_CLK_DIV0);
410 clkdiv1 = __raw_readl(S5P_CLK_DIV1);
412 printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n",
413 __func__, clkdiv0, clkdiv1);
415 xtal_clk = clk_get(NULL, "xtal");
416 BUG_ON(IS_ERR(xtal_clk));
418 xtal = clk_get_rate(xtal_clk);
421 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
423 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
424 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
425 epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500);
427 clk_fout_apll.rate = apll;
428 clk_fout_mpll.rate = mpll;
429 clk_fout_epll.rate = epll;
431 printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld",
434 armclk = clk_get_rate(&clk_armclk.clk);
435 hclk_msys = clk_get_rate(&clk_hclk_msys.clk);
436 hclk_dsys = clk_get_rate(&clk_hclk_dsys.clk);
437 hclk_psys = clk_get_rate(&clk_hclk_psys.clk);
439 pclk100 = hclk_msys / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK100);
440 pclk83 = hclk_dsys / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK83);
441 pclk66 = hclk_psys / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK66);
443 printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld\n"
444 "HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n",
445 armclk, hclk_msys, hclk_dsys, hclk_psys,
446 pclk100, pclk83, pclk66);
449 clk_h.rate = hclk_psys;
451 clk_p66.rate = pclk66;
452 clk_p83.rate = pclk83;
454 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
455 s3c_set_clksrc(&clksrcs[ptr], true);
458 static struct clk *clks[] __initdata = {
461 void __init s5pv210_register_clocks(void)
467 ret = s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
469 printk(KERN_ERR "Failed to register %u clocks\n", ret);
471 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
472 s3c_register_clksrc(sysclks[ptr], 1);
474 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
475 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
477 ret = s3c24xx_register_clocks(sys_clks, ARRAY_SIZE(sys_clks));
479 printk(KERN_ERR "Failed to register system clocks\n");
481 clkp = init_clocks_disable;
482 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
483 ret = s3c24xx_register_clock(clkp);
485 printk(KERN_ERR "Failed to register clock %s (%d)\n",
488 (clkp->enable)(clkp, 0);