1 /* linux/arch/arm/mach-s5p64x0/clock-s5p6440.c
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * S5P6440 - Clock support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/list.h>
17 #include <linux/errno.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
20 #include <linux/sysdev.h>
23 #include <mach/hardware.h>
25 #include <mach/regs-clock.h>
26 #include <mach/s5p64x0-clock.h>
28 #include <plat/cpu-freq.h>
29 #include <plat/clock.h>
32 #include <plat/s5p-clock.h>
33 #include <plat/clock-clksrc.h>
34 #include <plat/s5p6440.h>
36 static u32 epll_div[][5] = {
37 { 36000000, 0, 48, 1, 4 },
38 { 48000000, 0, 32, 1, 3 },
39 { 60000000, 0, 40, 1, 3 },
40 { 72000000, 0, 48, 1, 3 },
41 { 84000000, 0, 28, 1, 2 },
42 { 96000000, 0, 32, 1, 2 },
43 { 32768000, 45264, 43, 1, 4 },
44 { 45158000, 6903, 30, 1, 3 },
45 { 49152000, 50332, 32, 1, 3 },
46 { 67738000, 10398, 45, 1, 3 },
47 { 73728000, 9961, 49, 1, 3 }
50 static int s5p6440_epll_set_rate(struct clk *clk, unsigned long rate)
52 unsigned int epll_con, epll_con_k;
55 if (clk->rate == rate) /* Return if nothing changed */
58 epll_con = __raw_readl(S5P64X0_EPLL_CON);
59 epll_con_k = __raw_readl(S5P64X0_EPLL_CON_K);
61 epll_con_k &= ~(PLL90XX_KDIV_MASK);
62 epll_con &= ~(PLL90XX_MDIV_MASK | PLL90XX_PDIV_MASK | PLL90XX_SDIV_MASK);
64 for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
65 if (epll_div[i][0] == rate) {
66 epll_con_k |= (epll_div[i][1] << PLL90XX_KDIV_SHIFT);
67 epll_con |= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) |
68 (epll_div[i][3] << PLL90XX_PDIV_SHIFT) |
69 (epll_div[i][4] << PLL90XX_SDIV_SHIFT);
74 if (i == ARRAY_SIZE(epll_div)) {
75 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
79 __raw_writel(epll_con, S5P64X0_EPLL_CON);
80 __raw_writel(epll_con_k, S5P64X0_EPLL_CON_K);
82 printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
90 static struct clk_ops s5p6440_epll_ops = {
91 .get_rate = s5p_epll_get_rate,
92 .set_rate = s5p6440_epll_set_rate,
95 static struct clksrc_clk clk_hclk = {
98 .parent = &clk_armclk.clk,
100 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 },
103 static struct clksrc_clk clk_pclk = {
106 .parent = &clk_hclk.clk,
108 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
110 static struct clksrc_clk clk_hclk_low = {
112 .name = "clk_hclk_low",
114 .sources = &clkset_hclk_low,
115 .reg_src = { .reg = S5P64X0_SYS_OTHERS, .shift = 6, .size = 1 },
116 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 8, .size = 4 },
119 static struct clksrc_clk clk_pclk_low = {
121 .name = "clk_pclk_low",
122 .parent = &clk_hclk_low.clk,
124 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
128 * The following clocks will be disabled during clock initialization. It is
129 * recommended to keep the following clocks disabled until the driver requests
130 * for enabling the clock.
132 static struct clk init_clocks_off[] = {
135 .parent = &clk_hclk.clk,
136 .enable = s5p64x0_mem_ctrl,
140 .parent = &clk_hclk_low.clk,
141 .enable = s5p64x0_hclk0_ctrl,
145 .parent = &clk_hclk.clk,
146 .enable = s5p64x0_hclk0_ctrl,
150 .devname = "dma-pl330",
151 .parent = &clk_hclk_low.clk,
152 .enable = s5p64x0_hclk0_ctrl,
153 .ctrlbit = (1 << 12),
156 .devname = "s3c-sdhci.0",
157 .parent = &clk_hclk_low.clk,
158 .enable = s5p64x0_hclk0_ctrl,
159 .ctrlbit = (1 << 17),
162 .devname = "s3c-sdhci.1",
163 .parent = &clk_hclk_low.clk,
164 .enable = s5p64x0_hclk0_ctrl,
165 .ctrlbit = (1 << 18),
168 .devname = "s3c-sdhci.2",
169 .parent = &clk_hclk_low.clk,
170 .enable = s5p64x0_hclk0_ctrl,
171 .ctrlbit = (1 << 19),
174 .parent = &clk_hclk_low.clk,
175 .enable = s5p64x0_hclk0_ctrl,
179 .parent = &clk_hclk.clk,
180 .enable = s5p64x0_hclk0_ctrl,
181 .ctrlbit = (1 << 25),
184 .parent = &clk_hclk_low.clk,
185 .enable = s5p64x0_hclk1_ctrl,
188 .name = "hclk_fimgvg",
189 .parent = &clk_hclk.clk,
190 .enable = s5p64x0_hclk1_ctrl,
194 .parent = &clk_hclk_low.clk,
195 .enable = s5p64x0_hclk1_ctrl,
199 .parent = &clk_pclk_low.clk,
200 .enable = s5p64x0_pclk_ctrl,
204 .parent = &clk_pclk_low.clk,
205 .enable = s5p64x0_pclk_ctrl,
209 .parent = &clk_pclk_low.clk,
210 .enable = s5p64x0_pclk_ctrl,
214 .parent = &clk_pclk_low.clk,
215 .enable = s5p64x0_pclk_ctrl,
219 .parent = &clk_pclk_low.clk,
220 .enable = s5p64x0_pclk_ctrl,
221 .ctrlbit = (1 << 12),
224 .parent = &clk_pclk_low.clk,
225 .enable = s5p64x0_pclk_ctrl,
226 .ctrlbit = (1 << 17),
229 .devname = "s3c64xx-spi.0",
230 .parent = &clk_pclk_low.clk,
231 .enable = s5p64x0_pclk_ctrl,
232 .ctrlbit = (1 << 21),
235 .devname = "s3c64xx-spi.1",
236 .parent = &clk_pclk_low.clk,
237 .enable = s5p64x0_pclk_ctrl,
238 .ctrlbit = (1 << 22),
241 .parent = &clk_pclk_low.clk,
242 .enable = s5p64x0_pclk_ctrl,
243 .ctrlbit = (1 << 25),
246 .devname = "samsung-i2s.0",
247 .parent = &clk_pclk_low.clk,
248 .enable = s5p64x0_pclk_ctrl,
249 .ctrlbit = (1 << 26),
252 .parent = &clk_pclk_low.clk,
253 .enable = s5p64x0_pclk_ctrl,
254 .ctrlbit = (1 << 28),
257 .parent = &clk_pclk.clk,
258 .enable = s5p64x0_pclk_ctrl,
259 .ctrlbit = (1 << 29),
262 .parent = &clk_pclk.clk,
263 .enable = s5p64x0_pclk_ctrl,
264 .ctrlbit = (1 << 30),
266 .name = "pclk_fimgvg",
267 .parent = &clk_pclk.clk,
268 .enable = s5p64x0_pclk_ctrl,
269 .ctrlbit = (1 << 31),
271 .name = "sclk_spi_48",
272 .devname = "s3c64xx-spi.0",
274 .enable = s5p64x0_sclk_ctrl,
275 .ctrlbit = (1 << 22),
277 .name = "sclk_spi_48",
278 .devname = "s3c64xx-spi.1",
280 .enable = s5p64x0_sclk_ctrl,
281 .ctrlbit = (1 << 23),
284 .devname = "s3c-sdhci.0",
286 .enable = s5p64x0_sclk_ctrl,
287 .ctrlbit = (1 << 27),
290 .devname = "s3c-sdhci.1",
292 .enable = s5p64x0_sclk_ctrl,
293 .ctrlbit = (1 << 28),
296 .devname = "s3c-sdhci.2",
298 .enable = s5p64x0_sclk_ctrl,
299 .ctrlbit = (1 << 29),
304 * The following clocks will be enabled during clock initialization.
306 static struct clk init_clocks[] = {
309 .parent = &clk_hclk.clk,
310 .enable = s5p64x0_hclk0_ctrl,
314 .parent = &clk_hclk.clk,
315 .enable = s5p64x0_hclk0_ctrl,
316 .ctrlbit = (1 << 21),
319 .devname = "s3c6400-uart.0",
320 .parent = &clk_pclk_low.clk,
321 .enable = s5p64x0_pclk_ctrl,
325 .devname = "s3c6400-uart.1",
326 .parent = &clk_pclk_low.clk,
327 .enable = s5p64x0_pclk_ctrl,
331 .devname = "s3c6400-uart.2",
332 .parent = &clk_pclk_low.clk,
333 .enable = s5p64x0_pclk_ctrl,
337 .devname = "s3c6400-uart.3",
338 .parent = &clk_pclk_low.clk,
339 .enable = s5p64x0_pclk_ctrl,
343 .parent = &clk_pclk_low.clk,
344 .enable = s5p64x0_pclk_ctrl,
345 .ctrlbit = (1 << 18),
349 static struct clk clk_iis_cd_v40 = {
350 .name = "iis_cdclk_v40",
353 static struct clk clk_pcm_cd = {
357 static struct clk *clkset_group1_list[] = {
363 static struct clksrc_sources clkset_group1 = {
364 .sources = clkset_group1_list,
365 .nr_sources = ARRAY_SIZE(clkset_group1_list),
368 static struct clk *clkset_uart_list[] = {
373 static struct clksrc_sources clkset_uart = {
374 .sources = clkset_uart_list,
375 .nr_sources = ARRAY_SIZE(clkset_uart_list),
378 static struct clk *clkset_audio_list[] = {
386 static struct clksrc_sources clkset_audio = {
387 .sources = clkset_audio_list,
388 .nr_sources = ARRAY_SIZE(clkset_audio_list),
391 static struct clksrc_clk clksrcs[] = {
395 .devname = "s3c-sdhci.0",
396 .ctrlbit = (1 << 24),
397 .enable = s5p64x0_sclk_ctrl,
399 .sources = &clkset_group1,
400 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
401 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
405 .devname = "s3c-sdhci.1",
406 .ctrlbit = (1 << 25),
407 .enable = s5p64x0_sclk_ctrl,
409 .sources = &clkset_group1,
410 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
411 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
415 .devname = "s3c-sdhci.2",
416 .ctrlbit = (1 << 26),
417 .enable = s5p64x0_sclk_ctrl,
419 .sources = &clkset_group1,
420 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
421 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
426 .enable = s5p64x0_sclk_ctrl,
428 .sources = &clkset_uart,
429 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
430 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
434 .devname = "s3c64xx-spi.0",
435 .ctrlbit = (1 << 20),
436 .enable = s5p64x0_sclk_ctrl,
438 .sources = &clkset_group1,
439 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
440 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
444 .devname = "s3c64xx-spi.1",
445 .ctrlbit = (1 << 21),
446 .enable = s5p64x0_sclk_ctrl,
448 .sources = &clkset_group1,
449 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
450 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
454 .ctrlbit = (1 << 10),
455 .enable = s5p64x0_sclk_ctrl,
457 .sources = &clkset_group1,
458 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 26, .size = 2 },
459 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 12, .size = 4 },
462 .name = "sclk_dispcon",
464 .enable = s5p64x0_sclk1_ctrl,
466 .sources = &clkset_group1,
467 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 4, .size = 2 },
468 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 0, .size = 4 },
471 .name = "sclk_fimgvg",
473 .enable = s5p64x0_sclk1_ctrl,
475 .sources = &clkset_group1,
476 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 8, .size = 2 },
477 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 4, .size = 4 },
480 .name = "sclk_audio2",
481 .ctrlbit = (1 << 11),
482 .enable = s5p64x0_sclk_ctrl,
484 .sources = &clkset_audio,
485 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 0, .size = 3 },
486 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 24, .size = 4 },
490 /* Clock initialization code */
491 static struct clksrc_clk *sysclks[] = {
503 static struct clk dummy_apb_pclk = {
508 void __init_or_cpufreq s5p6440_setup_clocks(void)
510 struct clk *xtal_clk;
515 unsigned long hclk_low;
517 unsigned long pclk_low;
524 /* Set S5P6440 functions for clk_fout_epll */
526 clk_fout_epll.enable = s5p_epll_enable;
527 clk_fout_epll.ops = &s5p6440_epll_ops;
529 clk_48m.enable = s5p64x0_clk48m_ctrl;
531 xtal_clk = clk_get(NULL, "ext_xtal");
532 BUG_ON(IS_ERR(xtal_clk));
534 xtal = clk_get_rate(xtal_clk);
537 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_APLL_CON), pll_4502);
538 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_MPLL_CON), pll_4502);
539 epll = s5p_get_pll90xx(xtal, __raw_readl(S5P64X0_EPLL_CON),
540 __raw_readl(S5P64X0_EPLL_CON_K));
542 clk_fout_apll.rate = apll;
543 clk_fout_mpll.rate = mpll;
544 clk_fout_epll.rate = epll;
546 printk(KERN_INFO "S5P6440: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
548 print_mhz(apll), print_mhz(mpll), print_mhz(epll));
550 fclk = clk_get_rate(&clk_armclk.clk);
551 hclk = clk_get_rate(&clk_hclk.clk);
552 pclk = clk_get_rate(&clk_pclk.clk);
553 hclk_low = clk_get_rate(&clk_hclk_low.clk);
554 pclk_low = clk_get_rate(&clk_pclk_low.clk);
556 printk(KERN_INFO "S5P6440: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
557 " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
558 print_mhz(hclk), print_mhz(hclk_low),
559 print_mhz(pclk), print_mhz(pclk_low));
565 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
566 s3c_set_clksrc(&clksrcs[ptr], true);
569 static struct clk *clks[] __initdata = {
575 void __init s5p6440_register_clocks(void)
579 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
581 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
582 s3c_register_clksrc(sysclks[ptr], 1);
584 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
585 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
587 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
588 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
590 s3c24xx_register_clock(&dummy_apb_pclk);