1 /* linux/arch/arm/mach-s5p64x0/clock-s5p6440.c
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * S5P6440 - Clock support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/list.h>
17 #include <linux/errno.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
20 #include <linux/sysdev.h>
23 #include <mach/hardware.h>
25 #include <mach/regs-clock.h>
26 #include <mach/s5p64x0-clock.h>
28 #include <plat/cpu-freq.h>
29 #include <plat/clock.h>
32 #include <plat/s5p-clock.h>
33 #include <plat/clock-clksrc.h>
34 #include <plat/s5p6440.h>
36 static u32 epll_div[][5] = {
37 { 36000000, 0, 48, 1, 4 },
38 { 48000000, 0, 32, 1, 3 },
39 { 60000000, 0, 40, 1, 3 },
40 { 72000000, 0, 48, 1, 3 },
41 { 84000000, 0, 28, 1, 2 },
42 { 96000000, 0, 32, 1, 2 },
43 { 32768000, 45264, 43, 1, 4 },
44 { 45158000, 6903, 30, 1, 3 },
45 { 49152000, 50332, 32, 1, 3 },
46 { 67738000, 10398, 45, 1, 3 },
47 { 73728000, 9961, 49, 1, 3 }
50 static int s5p6440_epll_set_rate(struct clk *clk, unsigned long rate)
52 unsigned int epll_con, epll_con_k;
55 if (clk->rate == rate) /* Return if nothing changed */
58 epll_con = __raw_readl(S5P64X0_EPLL_CON);
59 epll_con_k = __raw_readl(S5P64X0_EPLL_CON_K);
61 epll_con_k &= ~(PLL90XX_KDIV_MASK);
62 epll_con &= ~(PLL90XX_MDIV_MASK | PLL90XX_PDIV_MASK | PLL90XX_SDIV_MASK);
64 for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
65 if (epll_div[i][0] == rate) {
66 epll_con_k |= (epll_div[i][1] << PLL90XX_KDIV_SHIFT);
67 epll_con |= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) |
68 (epll_div[i][3] << PLL90XX_PDIV_SHIFT) |
69 (epll_div[i][4] << PLL90XX_SDIV_SHIFT);
74 if (i == ARRAY_SIZE(epll_div)) {
75 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
79 __raw_writel(epll_con, S5P64X0_EPLL_CON);
80 __raw_writel(epll_con_k, S5P64X0_EPLL_CON_K);
82 printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
90 static struct clk_ops s5p6440_epll_ops = {
91 .get_rate = s5p_epll_get_rate,
92 .set_rate = s5p6440_epll_set_rate,
95 static struct clksrc_clk clk_hclk = {
98 .parent = &clk_armclk.clk,
100 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 },
103 static struct clksrc_clk clk_pclk = {
106 .parent = &clk_hclk.clk,
108 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
110 static struct clksrc_clk clk_hclk_low = {
112 .name = "clk_hclk_low",
114 .sources = &clkset_hclk_low,
115 .reg_src = { .reg = S5P64X0_SYS_OTHERS, .shift = 6, .size = 1 },
116 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 8, .size = 4 },
119 static struct clksrc_clk clk_pclk_low = {
121 .name = "clk_pclk_low",
122 .parent = &clk_hclk_low.clk,
124 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
128 * The following clocks will be disabled during clock initialization. It is
129 * recommended to keep the following clocks disabled until the driver requests
130 * for enabling the clock.
132 static struct clk init_clocks_off[] = {
135 .parent = &clk_hclk.clk,
136 .enable = s5p64x0_mem_ctrl,
140 .parent = &clk_hclk_low.clk,
141 .enable = s5p64x0_hclk0_ctrl,
145 .parent = &clk_hclk.clk,
146 .enable = s5p64x0_hclk0_ctrl,
150 .parent = &clk_hclk_low.clk,
151 .enable = s5p64x0_hclk0_ctrl,
152 .ctrlbit = (1 << 12),
155 .devname = "s3c-sdhci.0",
156 .parent = &clk_hclk_low.clk,
157 .enable = s5p64x0_hclk0_ctrl,
158 .ctrlbit = (1 << 17),
161 .devname = "s3c-sdhci.1",
162 .parent = &clk_hclk_low.clk,
163 .enable = s5p64x0_hclk0_ctrl,
164 .ctrlbit = (1 << 18),
167 .devname = "s3c-sdhci.2",
168 .parent = &clk_hclk_low.clk,
169 .enable = s5p64x0_hclk0_ctrl,
170 .ctrlbit = (1 << 19),
173 .parent = &clk_hclk_low.clk,
174 .enable = s5p64x0_hclk0_ctrl,
178 .parent = &clk_hclk.clk,
179 .enable = s5p64x0_hclk0_ctrl,
180 .ctrlbit = (1 << 25),
183 .parent = &clk_hclk_low.clk,
184 .enable = s5p64x0_hclk1_ctrl,
187 .name = "hclk_fimgvg",
188 .parent = &clk_hclk.clk,
189 .enable = s5p64x0_hclk1_ctrl,
193 .parent = &clk_hclk_low.clk,
194 .enable = s5p64x0_hclk1_ctrl,
198 .parent = &clk_pclk_low.clk,
199 .enable = s5p64x0_pclk_ctrl,
203 .parent = &clk_pclk_low.clk,
204 .enable = s5p64x0_pclk_ctrl,
208 .parent = &clk_pclk_low.clk,
209 .enable = s5p64x0_pclk_ctrl,
213 .parent = &clk_pclk_low.clk,
214 .enable = s5p64x0_pclk_ctrl,
218 .parent = &clk_pclk_low.clk,
219 .enable = s5p64x0_pclk_ctrl,
220 .ctrlbit = (1 << 12),
223 .parent = &clk_pclk_low.clk,
224 .enable = s5p64x0_pclk_ctrl,
225 .ctrlbit = (1 << 17),
228 .devname = "s3c64xx-spi.0",
229 .parent = &clk_pclk_low.clk,
230 .enable = s5p64x0_pclk_ctrl,
231 .ctrlbit = (1 << 21),
234 .devname = "s3c64xx-spi.1",
235 .parent = &clk_pclk_low.clk,
236 .enable = s5p64x0_pclk_ctrl,
237 .ctrlbit = (1 << 22),
240 .parent = &clk_pclk_low.clk,
241 .enable = s5p64x0_pclk_ctrl,
242 .ctrlbit = (1 << 25),
245 .devname = "samsung-i2s.0",
246 .parent = &clk_pclk_low.clk,
247 .enable = s5p64x0_pclk_ctrl,
248 .ctrlbit = (1 << 26),
251 .parent = &clk_pclk_low.clk,
252 .enable = s5p64x0_pclk_ctrl,
253 .ctrlbit = (1 << 28),
256 .parent = &clk_pclk.clk,
257 .enable = s5p64x0_pclk_ctrl,
258 .ctrlbit = (1 << 29),
261 .parent = &clk_pclk.clk,
262 .enable = s5p64x0_pclk_ctrl,
263 .ctrlbit = (1 << 30),
265 .name = "pclk_fimgvg",
266 .parent = &clk_pclk.clk,
267 .enable = s5p64x0_pclk_ctrl,
268 .ctrlbit = (1 << 31),
270 .name = "sclk_spi_48",
271 .devname = "s3c64xx-spi.0",
273 .enable = s5p64x0_sclk_ctrl,
274 .ctrlbit = (1 << 22),
276 .name = "sclk_spi_48",
277 .devname = "s3c64xx-spi.1",
279 .enable = s5p64x0_sclk_ctrl,
280 .ctrlbit = (1 << 23),
283 .devname = "s3c-sdhci.0",
285 .enable = s5p64x0_sclk_ctrl,
286 .ctrlbit = (1 << 27),
289 .devname = "s3c-sdhci.1",
291 .enable = s5p64x0_sclk_ctrl,
292 .ctrlbit = (1 << 28),
295 .devname = "s3c-sdhci.2",
297 .enable = s5p64x0_sclk_ctrl,
298 .ctrlbit = (1 << 29),
303 * The following clocks will be enabled during clock initialization.
305 static struct clk init_clocks[] = {
308 .parent = &clk_hclk.clk,
309 .enable = s5p64x0_hclk0_ctrl,
313 .parent = &clk_hclk.clk,
314 .enable = s5p64x0_hclk0_ctrl,
315 .ctrlbit = (1 << 21),
318 .devname = "s3c6400-uart.0",
319 .parent = &clk_pclk_low.clk,
320 .enable = s5p64x0_pclk_ctrl,
324 .devname = "s3c6400-uart.1",
325 .parent = &clk_pclk_low.clk,
326 .enable = s5p64x0_pclk_ctrl,
330 .devname = "s3c6400-uart.2",
331 .parent = &clk_pclk_low.clk,
332 .enable = s5p64x0_pclk_ctrl,
336 .devname = "s3c6400-uart.3",
337 .parent = &clk_pclk_low.clk,
338 .enable = s5p64x0_pclk_ctrl,
342 .parent = &clk_pclk_low.clk,
343 .enable = s5p64x0_pclk_ctrl,
344 .ctrlbit = (1 << 18),
348 static struct clk clk_iis_cd_v40 = {
349 .name = "iis_cdclk_v40",
352 static struct clk clk_pcm_cd = {
356 static struct clk *clkset_group1_list[] = {
362 static struct clksrc_sources clkset_group1 = {
363 .sources = clkset_group1_list,
364 .nr_sources = ARRAY_SIZE(clkset_group1_list),
367 static struct clk *clkset_uart_list[] = {
372 static struct clksrc_sources clkset_uart = {
373 .sources = clkset_uart_list,
374 .nr_sources = ARRAY_SIZE(clkset_uart_list),
377 static struct clk *clkset_audio_list[] = {
385 static struct clksrc_sources clkset_audio = {
386 .sources = clkset_audio_list,
387 .nr_sources = ARRAY_SIZE(clkset_audio_list),
390 static struct clksrc_clk clksrcs[] = {
394 .devname = "s3c-sdhci.0",
395 .ctrlbit = (1 << 24),
396 .enable = s5p64x0_sclk_ctrl,
398 .sources = &clkset_group1,
399 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
400 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
404 .devname = "s3c-sdhci.1",
405 .ctrlbit = (1 << 25),
406 .enable = s5p64x0_sclk_ctrl,
408 .sources = &clkset_group1,
409 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
410 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
414 .devname = "s3c-sdhci.2",
415 .ctrlbit = (1 << 26),
416 .enable = s5p64x0_sclk_ctrl,
418 .sources = &clkset_group1,
419 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
420 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
425 .enable = s5p64x0_sclk_ctrl,
427 .sources = &clkset_uart,
428 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
429 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
433 .devname = "s3c64xx-spi.0",
434 .ctrlbit = (1 << 20),
435 .enable = s5p64x0_sclk_ctrl,
437 .sources = &clkset_group1,
438 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
439 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
443 .devname = "s3c64xx-spi.1",
444 .ctrlbit = (1 << 21),
445 .enable = s5p64x0_sclk_ctrl,
447 .sources = &clkset_group1,
448 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
449 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
453 .ctrlbit = (1 << 10),
454 .enable = s5p64x0_sclk_ctrl,
456 .sources = &clkset_group1,
457 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 26, .size = 2 },
458 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 12, .size = 4 },
461 .name = "sclk_dispcon",
463 .enable = s5p64x0_sclk1_ctrl,
465 .sources = &clkset_group1,
466 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 4, .size = 2 },
467 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 0, .size = 4 },
470 .name = "sclk_fimgvg",
472 .enable = s5p64x0_sclk1_ctrl,
474 .sources = &clkset_group1,
475 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 8, .size = 2 },
476 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 4, .size = 4 },
479 .name = "sclk_audio2",
480 .ctrlbit = (1 << 11),
481 .enable = s5p64x0_sclk_ctrl,
483 .sources = &clkset_audio,
484 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 0, .size = 3 },
485 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 24, .size = 4 },
489 /* Clock initialization code */
490 static struct clksrc_clk *sysclks[] = {
502 void __init_or_cpufreq s5p6440_setup_clocks(void)
504 struct clk *xtal_clk;
509 unsigned long hclk_low;
511 unsigned long pclk_low;
518 /* Set S5P6440 functions for clk_fout_epll */
520 clk_fout_epll.enable = s5p_epll_enable;
521 clk_fout_epll.ops = &s5p6440_epll_ops;
523 clk_48m.enable = s5p64x0_clk48m_ctrl;
525 xtal_clk = clk_get(NULL, "ext_xtal");
526 BUG_ON(IS_ERR(xtal_clk));
528 xtal = clk_get_rate(xtal_clk);
531 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_APLL_CON), pll_4502);
532 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_MPLL_CON), pll_4502);
533 epll = s5p_get_pll90xx(xtal, __raw_readl(S5P64X0_EPLL_CON),
534 __raw_readl(S5P64X0_EPLL_CON_K));
536 clk_fout_apll.rate = apll;
537 clk_fout_mpll.rate = mpll;
538 clk_fout_epll.rate = epll;
540 printk(KERN_INFO "S5P6440: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
542 print_mhz(apll), print_mhz(mpll), print_mhz(epll));
544 fclk = clk_get_rate(&clk_armclk.clk);
545 hclk = clk_get_rate(&clk_hclk.clk);
546 pclk = clk_get_rate(&clk_pclk.clk);
547 hclk_low = clk_get_rate(&clk_hclk_low.clk);
548 pclk_low = clk_get_rate(&clk_pclk_low.clk);
550 printk(KERN_INFO "S5P6440: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
551 " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
552 print_mhz(hclk), print_mhz(hclk_low),
553 print_mhz(pclk), print_mhz(pclk_low));
559 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
560 s3c_set_clksrc(&clksrcs[ptr], true);
563 static struct clk *clks[] __initdata = {
569 void __init s5p6440_register_clocks(void)
573 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
575 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
576 s3c_register_clksrc(sysclks[ptr], 1);
578 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
579 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
581 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
582 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));