1 /* arch/arm/plat-s3c64xx/irq-eint.c
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
8 * S3C64XX - Interrupt handling for IRQ_EINT(x)
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/kernel.h>
16 #include <linux/interrupt.h>
17 #include <linux/sysdev.h>
18 #include <linux/gpio.h>
19 #include <linux/irq.h>
22 #include <asm/hardware/vic.h>
24 #include <plat/regs-irqtype.h>
25 #include <mach/regs-gpio.h>
26 #include <plat/gpio-cfg.h>
32 #define eint_offset(irq) ((irq) - IRQ_EINT(0))
33 #define eint_irq_to_bit(irq) ((u32)(1 << eint_offset(irq)))
35 static inline void s3c_irq_eint_mask(struct irq_data *data)
39 mask = __raw_readl(S3C64XX_EINT0MASK);
40 mask |= (u32)data->chip_data;
41 __raw_writel(mask, S3C64XX_EINT0MASK);
44 static void s3c_irq_eint_unmask(struct irq_data *data)
48 mask = __raw_readl(S3C64XX_EINT0MASK);
49 mask &= ~((u32)data->chip_data);
50 __raw_writel(mask, S3C64XX_EINT0MASK);
53 static inline void s3c_irq_eint_ack(struct irq_data *data)
55 __raw_writel((u32)data->chip_data, S3C64XX_EINT0PEND);
58 static void s3c_irq_eint_maskack(struct irq_data *data)
60 /* compiler should in-line these */
61 s3c_irq_eint_mask(data);
62 s3c_irq_eint_ack(data);
65 static int s3c_irq_eint_set_type(struct irq_data *data, unsigned int type)
67 int offs = eint_offset(data->irq);
78 reg = S3C64XX_EINT0CON0;
80 reg = S3C64XX_EINT0CON1;
84 printk(KERN_WARNING "No edge setting!\n");
87 case IRQ_TYPE_EDGE_RISING:
88 newvalue = S3C2410_EXTINT_RISEEDGE;
91 case IRQ_TYPE_EDGE_FALLING:
92 newvalue = S3C2410_EXTINT_FALLEDGE;
95 case IRQ_TYPE_EDGE_BOTH:
96 newvalue = S3C2410_EXTINT_BOTHEDGE;
99 case IRQ_TYPE_LEVEL_LOW:
100 newvalue = S3C2410_EXTINT_LOWLEV;
103 case IRQ_TYPE_LEVEL_HIGH:
104 newvalue = S3C2410_EXTINT_HILEV;
108 printk(KERN_ERR "No such irq type %d", type);
113 shift = (offs / 2) * 4;
115 shift = ((offs - 16) / 2) * 4;
118 ctrl = __raw_readl(reg);
120 ctrl |= newvalue << shift;
121 __raw_writel(ctrl, reg);
123 /* set the GPIO pin appropriately */
126 pin = S3C64XX_GPN(offs);
127 pin_val = S3C_GPIO_SFN(2);
128 } else if (offs < 23) {
129 pin = S3C64XX_GPL(offs + 8 - 16);
130 pin_val = S3C_GPIO_SFN(3);
132 pin = S3C64XX_GPM(offs - 23);
133 pin_val = S3C_GPIO_SFN(3);
136 s3c_gpio_cfgpin(pin, pin_val);
141 static struct irq_chip s3c_irq_eint = {
143 .irq_mask = s3c_irq_eint_mask,
144 .irq_unmask = s3c_irq_eint_unmask,
145 .irq_mask_ack = s3c_irq_eint_maskack,
146 .irq_ack = s3c_irq_eint_ack,
147 .irq_set_type = s3c_irq_eint_set_type,
148 .irq_set_wake = s3c_irqext_wake,
151 /* s3c_irq_demux_eint
153 * This function demuxes the IRQ from the group0 external interrupts,
154 * from IRQ_EINT(0) to IRQ_EINT(27). It is designed to be inlined into
155 * the specific handlers s3c_irq_demux_eintX_Y.
157 static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end)
159 u32 status = __raw_readl(S3C64XX_EINT0PEND);
160 u32 mask = __raw_readl(S3C64XX_EINT0MASK);
165 status &= (1 << (end - start + 1)) - 1;
167 for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
169 generic_handle_irq(irq);
175 static void s3c_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
177 s3c_irq_demux_eint(0, 3);
180 static void s3c_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
182 s3c_irq_demux_eint(4, 11);
185 static void s3c_irq_demux_eint12_19(unsigned int irq, struct irq_desc *desc)
187 s3c_irq_demux_eint(12, 19);
190 static void s3c_irq_demux_eint20_27(unsigned int irq, struct irq_desc *desc)
192 s3c_irq_demux_eint(20, 27);
195 static int __init s3c64xx_init_irq_eint(void)
199 for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) {
200 irq_set_chip(irq, &s3c_irq_eint);
201 irq_set_chip_data(irq, (void *)eint_irq_to_bit(irq));
202 irq_set_handler(irq, handle_level_irq);
203 set_irq_flags(irq, IRQF_VALID);
206 irq_set_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3);
207 irq_set_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11);
208 irq_set_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19);
209 irq_set_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27);
214 arch_initcall(s3c64xx_init_irq_eint);