1 /* arch/arm/plat-s3c64xx/gpiolib.c
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
8 * S3C64XX - GPIOlib support
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/kernel.h>
16 #include <linux/irq.h>
20 #include <mach/gpio.h>
22 #include <plat/gpio-core.h>
23 #include <plat/gpio-cfg.h>
24 #include <plat/gpio-cfg-helpers.h>
25 #include <mach/regs-gpio.h>
29 * Bank GPIOs Style SlpCon ExtInt Group
40 * K 16 4Bit[2] No None
41 * L 15 4Bit[2] No None
42 * M 6 4Bit No IRQ_EINT
43 * N 16 2Bit No IRQ_EINT
48 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
49 * [2] BANK has two control registers, GPxCON0 and GPxCON1
52 static struct s3c_gpio_cfg gpio_4bit_cfg_noint = {
53 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
54 .set_pull = s3c_gpio_setpull_updown,
55 .get_pull = s3c_gpio_getpull_updown,
58 static struct s3c_gpio_cfg gpio_4bit_cfg_eint0111 = {
60 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
61 .set_pull = s3c_gpio_setpull_updown,
62 .get_pull = s3c_gpio_getpull_updown,
65 static struct s3c_gpio_cfg gpio_4bit_cfg_eint0011 = {
67 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
68 .set_pull = s3c_gpio_setpull_updown,
69 .get_pull = s3c_gpio_getpull_updown,
72 int s3c64xx_gpio2int_gpm(struct gpio_chip *chip, unsigned pin)
74 return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO;
77 static struct s3c_gpio_chip gpio_4bit[] = {
79 .base = S3C64XX_GPA_BASE,
80 .config = &gpio_4bit_cfg_eint0111,
82 .base = S3C64XX_GPA(0),
83 .ngpio = S3C64XX_GPIO_A_NR,
87 .base = S3C64XX_GPB_BASE,
88 .config = &gpio_4bit_cfg_eint0111,
90 .base = S3C64XX_GPB(0),
91 .ngpio = S3C64XX_GPIO_B_NR,
95 .base = S3C64XX_GPC_BASE,
96 .config = &gpio_4bit_cfg_eint0111,
98 .base = S3C64XX_GPC(0),
99 .ngpio = S3C64XX_GPIO_C_NR,
103 .base = S3C64XX_GPD_BASE,
104 .config = &gpio_4bit_cfg_eint0111,
106 .base = S3C64XX_GPD(0),
107 .ngpio = S3C64XX_GPIO_D_NR,
111 .base = S3C64XX_GPE_BASE,
112 .config = &gpio_4bit_cfg_noint,
114 .base = S3C64XX_GPE(0),
115 .ngpio = S3C64XX_GPIO_E_NR,
119 .base = S3C64XX_GPG_BASE,
120 .config = &gpio_4bit_cfg_eint0111,
122 .base = S3C64XX_GPG(0),
123 .ngpio = S3C64XX_GPIO_G_NR,
127 .base = S3C64XX_GPM_BASE,
128 .config = &gpio_4bit_cfg_eint0011,
130 .base = S3C64XX_GPM(0),
131 .ngpio = S3C64XX_GPIO_M_NR,
133 .to_irq = s3c64xx_gpio2int_gpm,
138 int s3c64xx_gpio2int_gpl(struct gpio_chip *chip, unsigned pin)
140 return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO;
143 static struct s3c_gpio_chip gpio_4bit2[] = {
145 .base = S3C64XX_GPH_BASE + 0x4,
146 .config = &gpio_4bit_cfg_eint0111,
148 .base = S3C64XX_GPH(0),
149 .ngpio = S3C64XX_GPIO_H_NR,
153 .base = S3C64XX_GPK_BASE + 0x4,
154 .config = &gpio_4bit_cfg_noint,
156 .base = S3C64XX_GPK(0),
157 .ngpio = S3C64XX_GPIO_K_NR,
161 .base = S3C64XX_GPL_BASE + 0x4,
162 .config = &gpio_4bit_cfg_eint0011,
164 .base = S3C64XX_GPL(0),
165 .ngpio = S3C64XX_GPIO_L_NR,
167 .to_irq = s3c64xx_gpio2int_gpl,
172 static struct s3c_gpio_cfg gpio_2bit_cfg_noint = {
173 .set_config = s3c_gpio_setcfg_s3c24xx,
174 .set_pull = s3c_gpio_setpull_updown,
175 .get_pull = s3c_gpio_getpull_updown,
178 static struct s3c_gpio_cfg gpio_2bit_cfg_eint10 = {
180 .set_config = s3c_gpio_setcfg_s3c24xx,
181 .set_pull = s3c_gpio_setpull_updown,
182 .get_pull = s3c_gpio_getpull_updown,
185 static struct s3c_gpio_cfg gpio_2bit_cfg_eint11 = {
187 .set_config = s3c_gpio_setcfg_s3c24xx,
188 .set_pull = s3c_gpio_setpull_updown,
189 .get_pull = s3c_gpio_getpull_updown,
192 int s3c64xx_gpio2int_gpn(struct gpio_chip *chip, unsigned pin)
194 return IRQ_EINT(0) + pin;
197 static struct s3c_gpio_chip gpio_2bit[] = {
199 .base = S3C64XX_GPF_BASE,
200 .config = &gpio_2bit_cfg_eint11,
202 .base = S3C64XX_GPF(0),
203 .ngpio = S3C64XX_GPIO_F_NR,
207 .base = S3C64XX_GPI_BASE,
208 .config = &gpio_2bit_cfg_noint,
210 .base = S3C64XX_GPI(0),
211 .ngpio = S3C64XX_GPIO_I_NR,
215 .base = S3C64XX_GPJ_BASE,
216 .config = &gpio_2bit_cfg_noint,
218 .base = S3C64XX_GPJ(0),
219 .ngpio = S3C64XX_GPIO_J_NR,
223 .base = S3C64XX_GPN_BASE,
224 .config = &gpio_2bit_cfg_eint10,
226 .base = S3C64XX_GPN(0),
227 .ngpio = S3C64XX_GPIO_N_NR,
229 .to_irq = s3c64xx_gpio2int_gpn,
232 .base = S3C64XX_GPO_BASE,
233 .config = &gpio_2bit_cfg_eint11,
235 .base = S3C64XX_GPO(0),
236 .ngpio = S3C64XX_GPIO_O_NR,
240 .base = S3C64XX_GPP_BASE,
241 .config = &gpio_2bit_cfg_eint11,
243 .base = S3C64XX_GPP(0),
244 .ngpio = S3C64XX_GPIO_P_NR,
248 .base = S3C64XX_GPQ_BASE,
249 .config = &gpio_2bit_cfg_eint11,
251 .base = S3C64XX_GPQ(0),
252 .ngpio = S3C64XX_GPIO_Q_NR,
258 static __init void s3c64xx_gpiolib_add_2bit(struct s3c_gpio_chip *chip)
260 chip->pm = __gpio_pm(&s3c_gpio_pm_2bit);
263 static __init void s3c64xx_gpiolib_add(struct s3c_gpio_chip *chips,
265 void (*fn)(struct s3c_gpio_chip *))
267 for (; nr_chips > 0; nr_chips--, chips++) {
270 s3c_gpiolib_add(chips);
274 static __init int s3c64xx_gpiolib_init(void)
276 s3c64xx_gpiolib_add(gpio_4bit, ARRAY_SIZE(gpio_4bit),
277 samsung_gpiolib_add_4bit);
279 s3c64xx_gpiolib_add(gpio_4bit2, ARRAY_SIZE(gpio_4bit2),
280 samsung_gpiolib_add_4bit2);
282 s3c64xx_gpiolib_add(gpio_2bit, ARRAY_SIZE(gpio_2bit),
283 s3c64xx_gpiolib_add_2bit);
288 core_initcall(s3c64xx_gpiolib_init);