1 /* linux/arch/arm/plat-s3c64xx/dma.c
3 * Copyright 2009 Openmoko, Inc.
4 * Copyright 2009 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/dmapool.h>
19 #include <linux/sysdev.h>
20 #include <linux/errno.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
23 #include <linux/clk.h>
24 #include <linux/err.h>
29 #include <mach/irqs.h>
31 #include <mach/regs-sys.h>
33 #include <asm/hardware/pl080.h>
35 /* dma channel state information */
38 struct sys_device sysdev;
41 struct s3c2410_dma_chan *channels;
45 /* pool to provide LLI buffers */
46 static struct dma_pool *dma_pool;
48 /* Debug configuration and code */
50 static unsigned char debug_show_buffs = 0;
52 static void dbg_showchan(struct s3c2410_dma_chan *chan)
54 pr_debug("DMA%d: %08x->%08x L %08x C %08x,%08x S %08x\n",
56 readl(chan->regs + PL080_CH_SRC_ADDR),
57 readl(chan->regs + PL080_CH_DST_ADDR),
58 readl(chan->regs + PL080_CH_LLI),
59 readl(chan->regs + PL080_CH_CONTROL),
60 readl(chan->regs + PL080S_CH_CONTROL2),
61 readl(chan->regs + PL080S_CH_CONFIG));
64 static void show_lli(struct pl080s_lli *lli)
66 pr_debug("LLI[%p] %08x->%08x, NL %08x C %08x,%08x\n",
67 lli, lli->src_addr, lli->dst_addr, lli->next_lli,
68 lli->control0, lli->control1);
71 static void dbg_showbuffs(struct s3c2410_dma_chan *chan)
73 struct s3c64xx_dma_buff *ptr;
74 struct s3c64xx_dma_buff *end;
76 pr_debug("DMA%d: buffs next %p, curr %p, end %p\n",
77 chan->number, chan->next, chan->curr, chan->end);
82 if (debug_show_buffs) {
83 for (; ptr != NULL; ptr = ptr->next) {
84 pr_debug("DMA%d: %08x ",
85 chan->number, ptr->lli_dma);
93 static struct s3c2410_dma_chan *s3c64xx_dma_map_channel(unsigned int channel)
95 struct s3c2410_dma_chan *chan;
96 unsigned int start, offs;
100 if (channel >= DMACH_PCM1_TX)
103 for (offs = 0; offs < 8; offs++) {
104 chan = &s3c2410_chans[start + offs];
112 s3c_dma_chan_map[channel] = chan;
116 int s3c2410_dma_config(unsigned int channel, int xferunit)
118 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
134 printk(KERN_ERR "%s: illegal width %d\n", __func__, xferunit);
140 EXPORT_SYMBOL(s3c2410_dma_config);
142 static void s3c64xx_dma_fill_lli(struct s3c2410_dma_chan *chan,
143 struct pl080s_lli *lli,
144 dma_addr_t data, int size)
147 u32 control0, control1;
149 switch (chan->source) {
150 case S3C2410_DMASRC_HW:
151 src = chan->dev_addr;
153 control0 = PL080_CONTROL_SRC_AHB2;
154 control0 |= PL080_CONTROL_DST_INCR;
157 case S3C2410_DMASRC_MEM:
159 dst = chan->dev_addr;
160 control0 = PL080_CONTROL_DST_AHB2;
161 control0 |= PL080_CONTROL_SRC_INCR;
167 /* note, we do not currently setup any of the burst controls */
169 control1 = size >> chan->hw_width; /* size in no of xfers */
170 control0 |= PL080_CONTROL_PROT_SYS; /* always in priv. mode */
171 control0 |= PL080_CONTROL_TC_IRQ_EN; /* always fire IRQ */
172 control0 |= (u32)chan->hw_width << PL080_CONTROL_DWIDTH_SHIFT;
173 control0 |= (u32)chan->hw_width << PL080_CONTROL_SWIDTH_SHIFT;
178 lli->control0 = control0;
179 lli->control1 = control1;
182 static void s3c64xx_lli_to_regs(struct s3c2410_dma_chan *chan,
183 struct pl080s_lli *lli)
185 void __iomem *regs = chan->regs;
187 pr_debug("%s: LLI %p => regs\n", __func__, lli);
190 writel(lli->src_addr, regs + PL080_CH_SRC_ADDR);
191 writel(lli->dst_addr, regs + PL080_CH_DST_ADDR);
192 writel(lli->next_lli, regs + PL080_CH_LLI);
193 writel(lli->control0, regs + PL080_CH_CONTROL);
194 writel(lli->control1, regs + PL080S_CH_CONTROL2);
197 static int s3c64xx_dma_start(struct s3c2410_dma_chan *chan)
199 struct s3c64xx_dmac *dmac = chan->dmac;
205 pr_debug("%s: clearing interrupts\n", __func__);
207 /* clear interrupts */
208 writel(bit, dmac->regs + PL080_TC_CLEAR);
209 writel(bit, dmac->regs + PL080_ERR_CLEAR);
211 pr_debug("%s: starting channel\n", __func__);
213 config = readl(chan->regs + PL080S_CH_CONFIG);
214 config |= PL080_CONFIG_ENABLE;
216 pr_debug("%s: writing config %08x\n", __func__, config);
217 writel(config, chan->regs + PL080S_CH_CONFIG);
222 static int s3c64xx_dma_stop(struct s3c2410_dma_chan *chan)
227 pr_debug("%s: stopping channel\n", __func__);
231 config = readl(chan->regs + PL080S_CH_CONFIG);
232 config |= PL080_CONFIG_HALT;
233 writel(config, chan->regs + PL080S_CH_CONFIG);
237 config = readl(chan->regs + PL080S_CH_CONFIG);
238 pr_debug("%s: %d - config %08x\n", __func__, timeout, config);
239 if (config & PL080_CONFIG_ACTIVE)
243 } while (--timeout > 0);
245 if (config & PL080_CONFIG_ACTIVE) {
246 printk(KERN_ERR "%s: channel still active\n", __func__);
250 config = readl(chan->regs + PL080S_CH_CONFIG);
251 config &= ~PL080_CONFIG_ENABLE;
252 writel(config, chan->regs + PL080S_CH_CONFIG);
257 static inline void s3c64xx_dma_bufffdone(struct s3c2410_dma_chan *chan,
258 struct s3c64xx_dma_buff *buf,
259 enum s3c2410_dma_buffresult result)
261 if (chan->callback_fn != NULL)
262 (chan->callback_fn)(chan, buf->pw, 0, result);
265 static void s3c64xx_dma_freebuff(struct s3c64xx_dma_buff *buff)
267 dma_pool_free(dma_pool, buff->lli, buff->lli_dma);
271 static int s3c64xx_dma_flush(struct s3c2410_dma_chan *chan)
273 struct s3c64xx_dma_buff *buff, *next;
278 pr_debug("%s: flushing channel\n", __func__);
280 config = readl(chan->regs + PL080S_CH_CONFIG);
281 config &= ~PL080_CONFIG_ENABLE;
282 writel(config, chan->regs + PL080S_CH_CONFIG);
284 /* dump all the buffers associated with this channel */
286 for (buff = chan->curr; buff != NULL; buff = next) {
288 pr_debug("%s: buff %p (next %p)\n", __func__, buff, buff->next);
290 s3c64xx_dma_bufffdone(chan, buff, S3C2410_RES_ABORT);
291 s3c64xx_dma_freebuff(buff);
294 chan->curr = chan->next = chan->end = NULL;
299 int s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op)
301 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
308 case S3C2410_DMAOP_START:
309 return s3c64xx_dma_start(chan);
311 case S3C2410_DMAOP_STOP:
312 return s3c64xx_dma_stop(chan);
314 case S3C2410_DMAOP_FLUSH:
315 return s3c64xx_dma_flush(chan);
317 /* belive PAUSE/RESUME are no-ops */
318 case S3C2410_DMAOP_PAUSE:
319 case S3C2410_DMAOP_RESUME:
320 case S3C2410_DMAOP_STARTED:
321 case S3C2410_DMAOP_TIMEOUT:
327 EXPORT_SYMBOL(s3c2410_dma_ctrl);
333 int s3c2410_dma_enqueue(unsigned int channel, void *id,
334 dma_addr_t data, int size)
336 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
337 struct s3c64xx_dma_buff *next;
338 struct s3c64xx_dma_buff *buff;
339 struct pl080s_lli *lli;
347 buff = kzalloc(sizeof(struct s3c64xx_dma_buff), GFP_ATOMIC);
349 printk(KERN_ERR "%s: no memory for buffer\n", __func__);
353 lli = dma_pool_alloc(dma_pool, GFP_ATOMIC, &buff->lli_dma);
355 printk(KERN_ERR "%s: no memory for lli\n", __func__);
360 pr_debug("%s: buff %p, dp %08x lli (%p, %08x) %d\n",
361 __func__, buff, data, lli, (u32)buff->lli_dma, size);
366 s3c64xx_dma_fill_lli(chan, lli, data, size);
368 local_irq_save(flags);
370 if ((next = chan->next) != NULL) {
371 struct s3c64xx_dma_buff *end = chan->end;
372 struct pl080s_lli *endlli = end->lli;
374 pr_debug("enquing onto channel\n");
377 endlli->next_lli = buff->lli_dma;
379 if (chan->flags & S3C2410_DMAF_CIRCULAR) {
380 struct s3c64xx_dma_buff *curr = chan->curr;
381 lli->next_lli = curr->lli_dma;
384 if (next == chan->curr) {
385 writel(buff->lli_dma, chan->regs + PL080_CH_LLI);
392 pr_debug("enquing onto empty channel\n");
398 s3c64xx_lli_to_regs(chan, lli);
401 local_irq_restore(flags);
414 EXPORT_SYMBOL(s3c2410_dma_enqueue);
417 int s3c2410_dma_devconfig(unsigned int channel,
418 enum s3c2410_dmasrc source,
419 unsigned long devaddr)
421 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
425 pr_debug("%s: channel %d, source %d, dev %08lx, chan %p\n",
426 __func__, channel, source, devaddr, chan);
432 peripheral = (chan->peripheral & 0xf);
433 chan->source = source;
434 chan->dev_addr = devaddr;
436 pr_debug("%s: peripheral %d\n", __func__, peripheral);
439 case S3C2410_DMASRC_HW:
440 config = 2 << PL080_CONFIG_FLOW_CONTROL_SHIFT;
441 config |= peripheral << PL080_CONFIG_SRC_SEL_SHIFT;
443 case S3C2410_DMASRC_MEM:
444 config = 1 << PL080_CONFIG_FLOW_CONTROL_SHIFT;
445 config |= peripheral << PL080_CONFIG_DST_SEL_SHIFT;
448 printk(KERN_ERR "%s: bad source\n", __func__);
452 /* allow TC and ERR interrupts */
453 config |= PL080_CONFIG_TC_IRQ_MASK;
454 config |= PL080_CONFIG_ERR_IRQ_MASK;
456 pr_debug("%s: config %08x\n", __func__, config);
458 writel(config, chan->regs + PL080S_CH_CONFIG);
462 EXPORT_SYMBOL(s3c2410_dma_devconfig);
465 int s3c2410_dma_getposition(unsigned int channel,
466 dma_addr_t *src, dma_addr_t *dst)
468 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
475 *src = readl(chan->regs + PL080_CH_SRC_ADDR);
478 *dst = readl(chan->regs + PL080_CH_DST_ADDR);
482 EXPORT_SYMBOL(s3c2410_dma_getposition);
484 /* s3c2410_request_dma
486 * get control of an dma channel
489 int s3c2410_dma_request(unsigned int channel,
490 struct s3c2410_dma_client *client,
493 struct s3c2410_dma_chan *chan;
496 pr_debug("dma%d: s3c2410_request_dma: client=%s, dev=%p\n",
497 channel, client->name, dev);
499 local_irq_save(flags);
501 chan = s3c64xx_dma_map_channel(channel);
503 local_irq_restore(flags);
509 chan->client = client;
511 chan->peripheral = channel;
513 local_irq_restore(flags);
517 pr_debug("%s: channel initialised, %p\n", __func__, chan);
519 return chan->number | DMACH_LOW_LEVEL;
522 EXPORT_SYMBOL(s3c2410_dma_request);
526 * release the given channel back to the system, will stop and flush
527 * any outstanding transfers, and ensure the channel is ready for the
530 * Note, although a warning is currently printed if the freeing client
531 * info is not the same as the registrant's client info, the free is still
532 * allowed to go through.
535 int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *client)
537 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
543 local_irq_save(flags);
545 if (chan->client != client) {
546 printk(KERN_WARNING "dma%d: possible free from different client (channel %p, passed %p)\n",
547 channel, chan->client, client);
550 /* sort out stopping and freeing the channel */
556 if (!(channel & DMACH_LOW_LEVEL))
557 s3c_dma_chan_map[channel] = NULL;
559 local_irq_restore(flags);
564 EXPORT_SYMBOL(s3c2410_dma_free);
566 static irqreturn_t s3c64xx_dma_irq(int irq, void *pw)
568 struct s3c64xx_dmac *dmac = pw;
569 struct s3c2410_dma_chan *chan;
570 enum s3c2410_dma_buffresult res;
575 tcstat = readl(dmac->regs + PL080_TC_STATUS);
576 errstat = readl(dmac->regs + PL080_ERR_STATUS);
578 for (offs = 0, bit = 1; offs < 8; offs++, bit <<= 1) {
579 struct s3c64xx_dma_buff *buff;
581 if (!(errstat & bit) && !(tcstat & bit))
584 chan = dmac->channels + offs;
585 res = S3C2410_RES_ERR;
588 writel(bit, dmac->regs + PL080_TC_CLEAR);
589 res = S3C2410_RES_OK;
593 writel(bit, dmac->regs + PL080_ERR_CLEAR);
595 /* 'next' points to the buffer that is next to the
596 * currently active buffer.
597 * For CIRCULAR queues, 'next' will be same as 'curr'
598 * when 'end' is the active buffer.
601 while (buff && buff != chan->next
602 && buff->next != chan->next)
608 if (buff == chan->next)
611 s3c64xx_dma_bufffdone(chan, buff, res);
613 /* Free the node and update curr, if non-circular queue */
614 if (!(chan->flags & S3C2410_DMAF_CIRCULAR)) {
615 chan->curr = buff->next;
616 s3c64xx_dma_freebuff(buff);
621 if (chan->next == chan->end) {
622 chan->next = chan->curr;
623 if (!(chan->flags & S3C2410_DMAF_CIRCULAR))
626 chan->next = buff->next;
633 static struct sysdev_class dma_sysclass = {
634 .name = "s3c64xx-dma",
637 static int s3c64xx_dma_init1(int chno, enum dma_ch chbase,
638 int irq, unsigned int base)
640 struct s3c2410_dma_chan *chptr = &s3c2410_chans[chno];
641 struct s3c64xx_dmac *dmac;
644 void __iomem *regptr;
647 dmac = kzalloc(sizeof(struct s3c64xx_dmac), GFP_KERNEL);
649 printk(KERN_ERR "%s: failed to alloc mem\n", __func__);
653 dmac->sysdev.id = chno / 8;
654 dmac->sysdev.cls = &dma_sysclass;
656 err = sysdev_register(&dmac->sysdev);
658 printk(KERN_ERR "%s: failed to register sysdevice\n", __func__);
662 regs = ioremap(base, 0x200);
664 printk(KERN_ERR "%s: failed to ioremap()\n", __func__);
669 snprintf(clkname, sizeof(clkname), "dma%d", dmac->sysdev.id);
671 dmac->clk = clk_get(NULL, clkname);
672 if (IS_ERR(dmac->clk)) {
673 printk(KERN_ERR "%s: failed to get clock %s\n", __func__, clkname);
674 err = PTR_ERR(dmac->clk);
678 clk_enable(dmac->clk);
681 dmac->chanbase = chbase;
682 dmac->channels = chptr;
684 err = request_irq(irq, s3c64xx_dma_irq, 0, "DMA", dmac);
686 printk(KERN_ERR "%s: failed to get irq\n", __func__);
690 regptr = regs + PL080_Cx_BASE(0);
692 for (ch = 0; ch < 8; ch++, chno++, chptr++) {
693 printk(KERN_INFO "%s: registering DMA %d (%p)\n",
694 __func__, chno, regptr);
696 chptr->bit = 1 << ch;
697 chptr->number = chno;
699 chptr->regs = regptr;
700 regptr += PL080_Cx_STRIDE;
703 /* for the moment, permanently enable the controller */
704 writel(PL080_CONFIG_ENABLE, regs + PL080_CONFIG);
706 printk(KERN_INFO "PL080: IRQ %d, at %p\n", irq, regs);
711 clk_disable(dmac->clk);
716 sysdev_unregister(&dmac->sysdev);
722 static int __init s3c64xx_dma_init(void)
726 printk(KERN_INFO "%s: Registering DMA channels\n", __func__);
728 dma_pool = dma_pool_create("DMA-LLI", NULL, sizeof(struct pl080s_lli), 16, 0);
730 printk(KERN_ERR "%s: failed to create pool\n", __func__);
734 ret = sysdev_class_register(&dma_sysclass);
736 printk(KERN_ERR "%s: failed to create sysclass\n", __func__);
740 /* Set all DMA configuration to be DMA, not SDMA */
741 writel(0xffffff, S3C_SYSREG(0x110));
743 /* Register standard DMA controllers */
744 s3c64xx_dma_init1(0, DMACH_UART0, IRQ_DMA0, 0x75000000);
745 s3c64xx_dma_init1(8, DMACH_PCM1_TX, IRQ_DMA1, 0x75100000);
750 arch_initcall(s3c64xx_dma_init);