arch/arm/mach-s3c2440/mach-osiris.c

   1 /* linux/arch/arm/mach-s3c2440/mach-osiris.c
   2  *
   3  * Copyright (c) 2005 Simtec Electronics
   4  *      http://armlinux.simtec.co.uk/
   5  *      Ben Dooks <ben@simtec.co.uk>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/types.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/list.h>
  16 #include <linux/timer.h>
  17 #include <linux/init.h>
  18 #include <linux/device.h>
  19 #include <linux/serial_core.h>
  20
  21 #include <asm/mach/arch.h>
  22 #include <asm/mach/map.h>
  23 #include <asm/mach/irq.h>
  24
  25 #include <asm/arch/osiris-map.h>
  26 #include <asm/arch/osiris-cpld.h>
  27
  28 #include <asm/hardware.h>
  29 #include <asm/io.h>
  30 #include <asm/irq.h>
  31 #include <asm/mach-types.h>
  32
  33 #include <asm/arch/regs-serial.h>
  34 #include <asm/arch/regs-gpio.h>
  35 #include <asm/arch/regs-mem.h>
  36 #include <asm/arch/regs-lcd.h>
  37 #include <asm/arch/nand.h>
  38
  39 #include <linux/mtd/mtd.h>
  40 #include <linux/mtd/nand.h>
  41 #include <linux/mtd/nand_ecc.h>
  42 #include <linux/mtd/partitions.h>
  43
  44 #include <asm/plat-s3c24xx/clock.h>
  45 #include <asm/plat-s3c24xx/devs.h>
  46 #include <asm/plat-s3c24xx/cpu.h>
  47
  48 /* onboard perihperal map */
  49
  50 static struct map_desc osiris_iodesc[] __initdata = {
  51   /* ISA IO areas (may be over-written later) */
  52
  53   {
  54           .virtual      = (u32)S3C24XX_VA_ISA_BYTE,
  55           .pfn          = __phys_to_pfn(S3C2410_CS5),
  56           .length       = SZ_16M,
  57           .type         = MT_DEVICE,
  58   }, {
  59           .virtual      = (u32)S3C24XX_VA_ISA_WORD,
  60           .pfn          = __phys_to_pfn(S3C2410_CS5),
  61           .length       = SZ_16M,
  62           .type         = MT_DEVICE,
  63   },
  64
  65   /* CPLD control registers */
  66
  67   {
  68           .virtual      = (u32)OSIRIS_VA_CTRL0,
  69           .pfn          = __phys_to_pfn(OSIRIS_PA_CTRL0),
  70           .length       = SZ_16K,
  71           .type         = MT_DEVICE,
  72   }, {
  73           .virtual      = (u32)OSIRIS_VA_CTRL1,
  74           .pfn          = __phys_to_pfn(OSIRIS_PA_CTRL1),
  75           .length       = SZ_16K,
  76           .type         = MT_DEVICE,
  77   }, {
  78           .virtual      = (u32)OSIRIS_VA_CTRL2,
  79           .pfn          = __phys_to_pfn(OSIRIS_PA_CTRL2),
  80           .length       = SZ_16K,
  81           .type         = MT_DEVICE,
  82   }, {
  83           .virtual      = (u32)OSIRIS_VA_IDREG,
  84           .pfn          = __phys_to_pfn(OSIRIS_PA_IDREG),
  85           .length       = SZ_16K,
  86           .type         = MT_DEVICE,
  87   },
  88 };
  89
  90 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
  91 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
  92 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
  93
  94 static struct s3c24xx_uart_clksrc osiris_serial_clocks[] = {
  95         [0] = {
  96                 .name           = "uclk",
  97                 .divisor        = 1,
  98                 .min_baud       = 0,
  99                 .max_baud       = 0,
 100         },
 101         [1] = {
 102                 .name           = "pclk",
 103                 .divisor        = 1,
 104                 .min_baud       = 0,
 105                 .max_baud       = 0,
 106         }
 107 };
 108
 109 static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
 110         [0] = {
 111                 .hwport      = 0,
 112                 .flags       = 0,
 113                 .ucon        = UCON,
 114                 .ulcon       = ULCON,
 115                 .ufcon       = UFCON,
 116                 .clocks      = osiris_serial_clocks,
 117                 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
 118         },
 119         [1] = {
 120                 .hwport      = 1,
 121                 .flags       = 0,
 122                 .ucon        = UCON,
 123                 .ulcon       = ULCON,
 124                 .ufcon       = UFCON,
 125                 .clocks      = osiris_serial_clocks,
 126                 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
 127         },
 128         [2] = {
 129                 .hwport      = 2,
 130                 .flags       = 0,
 131                 .ucon        = UCON,
 132                 .ulcon       = ULCON,
 133                 .ufcon       = UFCON,
 134                 .clocks      = osiris_serial_clocks,
 135                 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
 136         }
 137 };
 138
 139 /* NAND Flash on Osiris board */
 140
 141 static int external_map[]   = { 2 };
 142 static int chip0_map[]      = { 0 };
 143 static int chip1_map[]      = { 1 };
 144
 145 static struct mtd_partition osiris_default_nand_part[] = {
 146         [0] = {
 147                 .name   = "Boot Agent",
 148                 .size   = SZ_16K,
 149                 .offset = 0,
 150         },
 151         [1] = {
 152                 .name   = "/boot",
 153                 .size   = SZ_4M - SZ_16K,
 154                 .offset = SZ_16K,
 155         },
 156         [2] = {
 157                 .name   = "user1",
 158                 .offset = SZ_4M,
 159                 .size   = SZ_32M - SZ_4M,
 160         },
 161         [3] = {
 162                 .name   = "user2",
 163                 .offset = SZ_32M,
 164                 .size   = MTDPART_SIZ_FULL,
 165         }
 166 };
 167
 168 /* the Osiris has 3 selectable slots for nand-flash, the two
 169  * on-board chip areas, as well as the external slot.
 170  *
 171  * Note, there is no current hot-plug support for the External
 172  * socket.
 173 */
 174
 175 static struct s3c2410_nand_set osiris_nand_sets[] = {
 176         [1] = {
 177                 .name           = "External",
 178                 .nr_chips       = 1,
 179                 .nr_map         = external_map,
 180                 .nr_partitions  = ARRAY_SIZE(osiris_default_nand_part),
 181                 .partitions     = osiris_default_nand_part,
 182         },
 183         [0] = {
 184                 .name           = "chip0",
 185                 .nr_chips       = 1,
 186                 .nr_map         = chip0_map,
 187                 .nr_partitions  = ARRAY_SIZE(osiris_default_nand_part),
 188                 .partitions     = osiris_default_nand_part,
 189         },
 190         [2] = {
 191                 .name           = "chip1",
 192                 .nr_chips       = 1,
 193                 .nr_map         = chip1_map,
 194                 .nr_partitions  = ARRAY_SIZE(osiris_default_nand_part),
 195                 .partitions     = osiris_default_nand_part,
 196         },
 197 };
 198
 199 static void osiris_nand_select(struct s3c2410_nand_set *set, int slot)
 200 {
 201         unsigned int tmp;
 202
 203         slot = set->nr_map[slot] & 3;
 204
 205         pr_debug("osiris_nand: selecting slot %d (set %p,%p)\n",
 206                  slot, set, set->nr_map);
 207
 208         tmp = __raw_readb(OSIRIS_VA_CTRL0);
 209         tmp &= ~OSIRIS_CTRL0_NANDSEL;
 210         tmp |= slot;
 211
 212         pr_debug("osiris_nand: ctrl0 now %02x\n", tmp);
 213
 214         __raw_writeb(tmp, OSIRIS_VA_CTRL0);
 215 }
 216
 217 static struct s3c2410_platform_nand osiris_nand_info = {
 218         .tacls          = 25,
 219         .twrph0         = 60,
 220         .twrph1         = 60,
 221         .nr_sets        = ARRAY_SIZE(osiris_nand_sets),
 222         .sets           = osiris_nand_sets,
 223         .select_chip    = osiris_nand_select,
 224 };
 225
 226 /* PCMCIA control and configuration */
 227
 228 static struct resource osiris_pcmcia_resource[] = {
 229         [0] = {
 230                 .start  = 0x0f000000,
 231                 .end    = 0x0f100000,
 232                 .flags  = IORESOURCE_MEM,
 233         },
 234         [1] = {
 235                 .start  = 0x0c000000,
 236                 .end    = 0x0c100000,
 237                 .flags  = IORESOURCE_MEM,
 238         }
 239 };
 240
 241 static struct platform_device osiris_pcmcia = {
 242         .name           = "osiris-pcmcia",
 243         .id             = -1,
 244         .num_resources  = ARRAY_SIZE(osiris_pcmcia_resource),
 245         .resource       = osiris_pcmcia_resource,
 246 };
 247
 248 /* Standard Osiris devices */
 249
 250 static struct platform_device *osiris_devices[] __initdata = {
 251         &s3c_device_i2c,
 252         &s3c_device_wdt,
 253         &s3c_device_nand,
 254         &osiris_pcmcia,
 255 };
 256
 257 static struct clk *osiris_clocks[] = {
 258         &s3c24xx_dclk0,
 259         &s3c24xx_dclk1,
 260         &s3c24xx_clkout0,
 261         &s3c24xx_clkout1,
 262         &s3c24xx_uclk,
 263 };
 264
 265 static void __init osiris_map_io(void)
 266 {
 267         unsigned long flags;
 268
 269         /* initialise the clocks */
 270
 271         s3c24xx_dclk0.parent = NULL;
 272         s3c24xx_dclk0.rate   = 12*1000*1000;
 273
 274         s3c24xx_dclk1.parent = NULL;
 275         s3c24xx_dclk1.rate   = 24*1000*1000;
 276
 277         s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
 278         s3c24xx_clkout1.parent  = &s3c24xx_dclk1;
 279
 280         s3c24xx_uclk.parent  = &s3c24xx_clkout1;
 281
 282         s3c24xx_register_clocks(osiris_clocks, ARRAY_SIZE(osiris_clocks));
 283
 284         s3c_device_nand.dev.platform_data = &osiris_nand_info;
 285
 286         s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc));
 287         s3c24xx_init_clocks(0);
 288         s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs));
 289
 290         /* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */
 291
 292         local_irq_save(flags);
 293         __raw_writel(__raw_readl(S3C2410_BWSCON) | S3C2410_BWSCON_ST1 | S3C2410_BWSCON_ST2 | S3C2410_BWSCON_ST3 | S3C2410_BWSCON_ST4 | S3C2410_BWSCON_ST5, S3C2410_BWSCON);
 294         local_irq_restore(flags);
 295
 296         /* write-protect line to the NAND */
 297         s3c2410_gpio_setpin(S3C2410_GPA0, 1);
 298 }
 299
 300 static void __init osiris_init(void)
 301 {
 302         platform_add_devices(osiris_devices, ARRAY_SIZE(osiris_devices));
 303 };
 304
 305 MACHINE_START(OSIRIS, "Simtec-OSIRIS")
 306         /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
 307         .phys_io        = S3C2410_PA_UART,
 308         .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
 309         .boot_params    = S3C2410_SDRAM_PA + 0x100,
 310         .map_io         = osiris_map_io,
 311         .init_machine   = osiris_init,
 312         .init_irq       = s3c24xx_init_irq,
 313         .timer          = &s3c24xx_timer,
 314 MACHINE_END