1 /* arch/arm/mach-s3c2410/include/mach/dma.h
3 * Copyright (C) 2003,2004,2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * Samsung S3C24XX DMA support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #ifndef __ASM_ARCH_DMA_H
14 #define __ASM_ARCH_DMA_H __FILE__
17 #include <linux/sysdev.h>
18 #include <mach/hardware.h>
20 #define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */
22 /* We use `virtual` dma channels to hide the fact we have only a limited
23 * number of DMA channels, and not of all of them (dependant on the device)
24 * can be attached to any DMA source. We therefore let the DMA core handle
25 * the allocation of hardware channels to clients.
47 DMACH_UART0_SRC2, /* s3c2412 second uart sources */
50 DMACH_UART3, /* s3c2443 has extra uart */
52 DMACH_MAX, /* the end entry */
55 #define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */
57 /* we have 4 dma channels */
58 #ifndef CONFIG_CPU_S3C2443
59 #define S3C2410_DMA_CHANNELS (4)
61 #define S3C2410_DMA_CHANNELS (6)
66 enum s3c2410_dma_state {
72 /* enum s3c2410_dma_loadst
74 * This represents the state of the DMA engine, wrt to the loaded / running
75 * transfers. Since we don't have any way of knowing exactly the state of
76 * the DMA transfers, we need to know the state to make decisions on wether
81 * There are no buffers loaded (the channel should be inactive)
85 * There is one buffer loaded, however it has not been confirmed to be
86 * loaded by the DMA engine. This may be because the channel is not
87 * yet running, or the DMA driver decided that it was too costly to
88 * sit and wait for it to happen.
90 * S3C2410_DMA_1RUNNING
92 * The buffer has been confirmed running, and not finisged
94 * S3C2410_DMA_1LOADED_1RUNNING
96 * There is a buffer waiting to be loaded by the DMA engine, and one
100 enum s3c2410_dma_loadst {
101 S3C2410_DMALOAD_NONE,
102 S3C2410_DMALOAD_1LOADED,
103 S3C2410_DMALOAD_1RUNNING,
104 S3C2410_DMALOAD_1LOADED_1RUNNING,
110 #define S3C2410_DMAF_SLOW (1<<0) /* slow, so don't worry about
111 * waiting for reloads */
112 #define S3C2410_DMAF_AUTOSTART (1<<1) /* auto-start if buffer queued */
116 struct s3c2410_dma_buf;
120 * internally used buffer structure to describe a queued or running
124 struct s3c2410_dma_buf {
125 struct s3c2410_dma_buf *next;
126 int magic; /* magic */
127 int size; /* buffer size in bytes */
128 dma_addr_t data; /* start of DMA data */
129 dma_addr_t ptr; /* where the DMA got to [1] */
130 void *id; /* client's id */
133 /* [1] is this updated for both recv/send modes? */
135 struct s3c2410_dma_stats {
137 unsigned long timeout_longest;
138 unsigned long timeout_shortest;
139 unsigned long timeout_avg;
140 unsigned long timeout_failed;
143 struct s3c2410_dma_map;
145 /* struct s3c2410_dma_chan
147 * full state information for each DMA channel
150 struct s3c2410_dma_chan {
151 /* channel state flags and information */
152 unsigned char number; /* number of this dma channel */
153 unsigned char in_use; /* channel allocated */
154 unsigned char irq_claimed; /* irq claimed for channel */
155 unsigned char irq_enabled; /* irq enabled for channel */
156 unsigned char xfer_unit; /* size of an transfer */
160 enum s3c2410_dma_state state;
161 enum s3c2410_dma_loadst load_state;
162 struct s3c2410_dma_client *client;
164 /* channel configuration */
165 enum s3c2410_dmasrc source;
167 unsigned long dev_addr;
168 unsigned long load_timeout;
169 unsigned int flags; /* channel flags */
171 struct s3c24xx_dma_map *map; /* channel hw maps */
173 /* channel's hardware position and configuration */
174 void __iomem *regs; /* channels registers */
175 void __iomem *addr_reg; /* data address register */
176 unsigned int irq; /* channel irq */
177 unsigned long dcon; /* default value of DCON */
180 s3c2410_dma_cbfn_t callback_fn; /* buffer done callback */
181 s3c2410_dma_opfn_t op_fn; /* channel op callback */
183 /* stats gathering */
184 struct s3c2410_dma_stats *stats;
185 struct s3c2410_dma_stats stats_store;
187 /* buffer list and information */
188 struct s3c2410_dma_buf *curr; /* current dma buffer */
189 struct s3c2410_dma_buf *next; /* next buffer to load */
190 struct s3c2410_dma_buf *end; /* end of queue */
193 struct sys_device dev;
196 /* the currently allocated channel information */
197 extern struct s3c2410_dma_chan s3c2410_chans[];
199 /* note, we don't really use dma_device_t at the moment */
200 typedef unsigned long dma_device_t;
202 #endif /* __ASM_ARCH_DMA_H */