1 /* linux/arch/arm/mach-s3c2410/clock.c
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * S3C2410 Clock control support
8 * Based on, and code from linux/arch/arm/mach-versatile/clock.c
10 ** Copyright (C) 2004 ARM Limited.
11 ** Written by Deep Blue Solutions Limited.
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29 #include <linux/init.h>
30 #include <linux/module.h>
31 #include <linux/kernel.h>
32 #include <linux/list.h>
33 #include <linux/errno.h>
34 #include <linux/err.h>
35 #include <linux/platform_device.h>
36 #include <linux/sysdev.h>
37 #include <linux/interrupt.h>
38 #include <linux/ioport.h>
39 #include <linux/clk.h>
41 #include <asm/hardware.h>
42 #include <asm/atomic.h>
46 #include <asm/arch/regs-clock.h>
51 /* clock information */
53 static LIST_HEAD(clocks);
54 static DECLARE_MUTEX(clocks_sem);
58 void inline s3c24xx_clk_enable(unsigned int clocks, unsigned int enable)
63 local_irq_save(flags);
65 clkcon = __raw_readl(S3C2410_CLKCON);
71 /* ensure none of the special function bits set */
72 clkcon &= ~(S3C2410_CLKCON_IDLE|S3C2410_CLKCON_POWER);
74 __raw_writel(clkcon, S3C2410_CLKCON);
76 local_irq_restore(flags);
79 /* enable and disable calls for use with the clk struct */
81 static int clk_null_enable(struct clk *clk, int enable)
86 int s3c24xx_clkcon_enable(struct clk *clk, int enable)
88 s3c24xx_clk_enable(clk->ctrlbit, enable);
94 struct clk *clk_get(struct device *dev, const char *id)
97 struct clk *clk = ERR_PTR(-ENOENT);
100 if (dev == NULL || dev->bus != &platform_bus_type)
103 idno = to_platform_device(dev)->id;
107 list_for_each_entry(p, &clocks, list) {
109 strcmp(id, p->name) == 0 &&
110 try_module_get(p->owner)) {
116 /* check for the case where a device was supplied, but the
117 * clock that was being searched for is not device specific */
120 list_for_each_entry(p, &clocks, list) {
121 if (p->id == -1 && strcmp(id, p->name) == 0 &&
122 try_module_get(p->owner)) {
133 void clk_put(struct clk *clk)
135 module_put(clk->owner);
138 int clk_enable(struct clk *clk)
143 return (clk->enable)(clk, 1);
146 void clk_disable(struct clk *clk)
149 (clk->enable)(clk, 0);
153 unsigned long clk_get_rate(struct clk *clk)
161 while (clk->parent != NULL && clk->rate == 0)
167 long clk_round_rate(struct clk *clk, unsigned long rate)
172 int clk_set_rate(struct clk *clk, unsigned long rate)
177 struct clk *clk_get_parent(struct clk *clk)
182 EXPORT_SYMBOL(clk_get);
183 EXPORT_SYMBOL(clk_put);
184 EXPORT_SYMBOL(clk_enable);
185 EXPORT_SYMBOL(clk_disable);
186 EXPORT_SYMBOL(clk_get_rate);
187 EXPORT_SYMBOL(clk_round_rate);
188 EXPORT_SYMBOL(clk_set_rate);
189 EXPORT_SYMBOL(clk_get_parent);
193 static struct clk clk_xtal = {
201 static struct clk clk_f = {
209 static struct clk clk_h = {
217 static struct clk clk_p = {
225 /* clocks that could be registered by external code */
227 struct clk s3c24xx_dclk0 = {
232 struct clk s3c24xx_dclk1 = {
237 struct clk s3c24xx_clkout0 = {
242 struct clk s3c24xx_clkout1 = {
247 struct clk s3c24xx_uclk = {
253 /* clock definitions */
255 static struct clk init_clocks[] = {
259 .enable = s3c24xx_clkcon_enable,
260 .ctrlbit = S3C2410_CLKCON_NAND
265 .enable = s3c24xx_clkcon_enable,
266 .ctrlbit = S3C2410_CLKCON_LCDC
268 { .name = "usb-host",
271 .enable = s3c24xx_clkcon_enable,
272 .ctrlbit = S3C2410_CLKCON_USBH
274 { .name = "usb-device",
277 .enable = s3c24xx_clkcon_enable,
278 .ctrlbit = S3C2410_CLKCON_USBD
283 .enable = s3c24xx_clkcon_enable,
284 .ctrlbit = S3C2410_CLKCON_PWMT
289 .enable = s3c24xx_clkcon_enable,
290 .ctrlbit = S3C2410_CLKCON_SDI
295 .enable = s3c24xx_clkcon_enable,
296 .ctrlbit = S3C2410_CLKCON_UART0
301 .enable = s3c24xx_clkcon_enable,
302 .ctrlbit = S3C2410_CLKCON_UART1
307 .enable = s3c24xx_clkcon_enable,
308 .ctrlbit = S3C2410_CLKCON_UART2
313 .enable = s3c24xx_clkcon_enable,
314 .ctrlbit = S3C2410_CLKCON_GPIO
319 .enable = s3c24xx_clkcon_enable,
320 .ctrlbit = S3C2410_CLKCON_RTC
325 .enable = s3c24xx_clkcon_enable,
326 .ctrlbit = S3C2410_CLKCON_ADC
331 .enable = s3c24xx_clkcon_enable,
332 .ctrlbit = S3C2410_CLKCON_IIC
337 .enable = s3c24xx_clkcon_enable,
338 .ctrlbit = S3C2410_CLKCON_IIS
343 .enable = s3c24xx_clkcon_enable,
344 .ctrlbit = S3C2410_CLKCON_SPI
346 { .name = "watchdog",
353 /* initialise the clock system */
355 int s3c24xx_register_clock(struct clk *clk)
357 clk->owner = THIS_MODULE;
359 if (clk->enable == NULL)
360 clk->enable = clk_null_enable;
362 /* add to the list of available clocks */
365 list_add(&clk->list, &clocks);
371 /* initalise all the clocks */
373 int __init s3c24xx_setup_clocks(unsigned long xtal,
378 unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
379 struct clk *clkp = init_clocks;
383 printk(KERN_INFO "S3C2410 Clocks, (c) 2004 Simtec Electronics\n");
385 /* initialise the main system clocks */
387 clk_xtal.rate = xtal;
393 /* it looks like just setting the register here is not good
394 * enough, and causes the odd hang at initial boot time, so
395 * do all of them indivdually.
397 * I think disabling the LCD clock if the LCD is active is
398 * very dangerous, and therefore the bootloader should be
399 * careful to not enable the LCD clock if it is not needed.
401 * and of course, this looks neater
404 s3c24xx_clk_enable(S3C2410_CLKCON_NAND, 0);
405 s3c24xx_clk_enable(S3C2410_CLKCON_USBH, 0);
406 s3c24xx_clk_enable(S3C2410_CLKCON_USBD, 0);
407 s3c24xx_clk_enable(S3C2410_CLKCON_ADC, 0);
408 s3c24xx_clk_enable(S3C2410_CLKCON_IIC, 0);
409 s3c24xx_clk_enable(S3C2410_CLKCON_SPI, 0);
411 /* assume uart clocks are correctly setup */
413 /* register our clocks */
415 if (s3c24xx_register_clock(&clk_xtal) < 0)
416 printk(KERN_ERR "failed to register master xtal\n");
418 if (s3c24xx_register_clock(&clk_f) < 0)
419 printk(KERN_ERR "failed to register cpu fclk\n");
421 if (s3c24xx_register_clock(&clk_h) < 0)
422 printk(KERN_ERR "failed to register cpu hclk\n");
424 if (s3c24xx_register_clock(&clk_p) < 0)
425 printk(KERN_ERR "failed to register cpu pclk\n");
427 /* register clocks from clock array */
429 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
430 ret = s3c24xx_register_clock(clkp);
432 printk(KERN_ERR "Failed to register clock %s (%d)\n",
437 /* show the clock-slow value */
439 printk("CLOCK: Slow mode (%ld.%ld MHz), %s, MPLL %s, UPLL %s\n",
440 print_mhz(xtal / ( 2 * S3C2410_CLKSLOW_GET_SLOWVAL(clkslow))),
441 (clkslow & S3C2410_CLKSLOW_SLOW) ? "slow" : "fast",
442 (clkslow & S3C2410_CLKSLOW_MPLL_OFF) ? "off" : "on",
443 (clkslow & S3C2410_CLKSLOW_UCLK_OFF) ? "off" : "on");