1 /* linux/arch/arm/mach-s3c2410/clock.c
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * S3C2410,S3C2440,S3C2442 Clock control support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #include <linux/init.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/list.h>
27 #include <linux/errno.h>
28 #include <linux/err.h>
29 #include <linux/sysdev.h>
30 #include <linux/clk.h>
31 #include <linux/mutex.h>
32 #include <linux/delay.h>
33 #include <linux/serial_core.h>
36 #include <asm/mach/map.h>
38 #include <mach/hardware.h>
40 #include <plat/regs-serial.h>
41 #include <mach/regs-clock.h>
42 #include <mach/regs-gpio.h>
44 #include <plat/s3c2410.h>
45 #include <plat/clock.h>
48 int s3c2410_clkcon_enable(struct clk *clk, int enable)
50 unsigned int clocks = clk->ctrlbit;
53 clkcon = __raw_readl(S3C2410_CLKCON);
60 /* ensure none of the special function bits set */
61 clkcon &= ~(S3C2410_CLKCON_IDLE|S3C2410_CLKCON_POWER);
63 __raw_writel(clkcon, S3C2410_CLKCON);
68 static int s3c2410_upll_enable(struct clk *clk, int enable)
70 unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
71 unsigned long orig = clkslow;
74 clkslow &= ~S3C2410_CLKSLOW_UCLK_OFF;
76 clkslow |= S3C2410_CLKSLOW_UCLK_OFF;
78 __raw_writel(clkslow, S3C2410_CLKSLOW);
80 /* if we started the UPLL, then allow to settle */
82 if (enable && (orig & S3C2410_CLKSLOW_UCLK_OFF))
88 /* standard clock definitions */
90 static struct clk init_clocks_disable[] = {
95 .enable = s3c2410_clkcon_enable,
96 .ctrlbit = S3C2410_CLKCON_NAND,
101 .enable = s3c2410_clkcon_enable,
102 .ctrlbit = S3C2410_CLKCON_SDI,
107 .enable = s3c2410_clkcon_enable,
108 .ctrlbit = S3C2410_CLKCON_ADC,
113 .enable = s3c2410_clkcon_enable,
114 .ctrlbit = S3C2410_CLKCON_IIC,
119 .enable = s3c2410_clkcon_enable,
120 .ctrlbit = S3C2410_CLKCON_IIS,
125 .enable = s3c2410_clkcon_enable,
126 .ctrlbit = S3C2410_CLKCON_SPI,
130 static struct clk init_clocks[] = {
135 .enable = s3c2410_clkcon_enable,
136 .ctrlbit = S3C2410_CLKCON_LCDC,
141 .enable = s3c2410_clkcon_enable,
142 .ctrlbit = S3C2410_CLKCON_GPIO,
147 .enable = s3c2410_clkcon_enable,
148 .ctrlbit = S3C2410_CLKCON_USBH,
150 .name = "usb-device",
153 .enable = s3c2410_clkcon_enable,
154 .ctrlbit = S3C2410_CLKCON_USBD,
159 .enable = s3c2410_clkcon_enable,
160 .ctrlbit = S3C2410_CLKCON_PWMT,
165 .enable = s3c2410_clkcon_enable,
166 .ctrlbit = S3C2410_CLKCON_UART0,
171 .enable = s3c2410_clkcon_enable,
172 .ctrlbit = S3C2410_CLKCON_UART1,
177 .enable = s3c2410_clkcon_enable,
178 .ctrlbit = S3C2410_CLKCON_UART2,
183 .enable = s3c2410_clkcon_enable,
184 .ctrlbit = S3C2410_CLKCON_RTC,
191 .name = "usb-bus-host",
193 .parent = &clk_usb_bus,
195 .name = "usb-bus-gadget",
197 .parent = &clk_usb_bus,
201 /* s3c2410_baseclk_add()
203 * Add all the clocks used by the s3c2410 or compatible CPUs
204 * such as the S3C2440 and S3C2442.
206 * We cannot use a system device as we are needed before any
207 * of the init-calls that initialise the devices are actually
211 int __init s3c2410_baseclk_add(void)
213 unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
214 unsigned long clkcon = __raw_readl(S3C2410_CLKCON);
220 clk_upll.enable = s3c2410_upll_enable;
222 if (s3c24xx_register_clock(&clk_usb_bus) < 0)
223 printk(KERN_ERR "failed to register usb bus clock\n");
225 /* register clocks from clock array */
228 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
229 /* ensure that we note the clock state */
231 clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0;
233 ret = s3c24xx_register_clock(clkp);
235 printk(KERN_ERR "Failed to register clock %s (%d)\n",
240 /* We must be careful disabling the clocks we are not intending to
241 * be using at boot time, as subsystems such as the LCD which do
242 * their own DMA requests to the bus can cause the system to lockup
243 * if they where in the middle of requesting bus access.
245 * Disabling the LCD clock if the LCD is active is very dangerous,
246 * and therefore the bootloader should be careful to not enable
247 * the LCD clock if it is not needed.
250 /* install (and disable) the clocks we do not need immediately */
252 clkp = init_clocks_disable;
253 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
255 ret = s3c24xx_register_clock(clkp);
257 printk(KERN_ERR "Failed to register clock %s (%d)\n",
261 s3c2410_clkcon_enable(clkp, 0);
264 /* show the clock-slow value */
266 xtal = clk_get(NULL, "xtal");
268 printk("CLOCK: Slow mode (%ld.%ld MHz), %s, MPLL %s, UPLL %s\n",
269 print_mhz(clk_get_rate(xtal) /
270 ( 2 * S3C2410_CLKSLOW_GET_SLOWVAL(clkslow))),
271 (clkslow & S3C2410_CLKSLOW_SLOW) ? "slow" : "fast",
272 (clkslow & S3C2410_CLKSLOW_MPLL_OFF) ? "off" : "on",
273 (clkslow & S3C2410_CLKSLOW_UCLK_OFF) ? "off" : "on");