arch/arm/mach-rockchip/rk3308/rk3308.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *Copyright (c) 2018 Rockchip Electronics Co., Ltd
   4  */
   5 #include <common.h>
   6 #include <init.h>
   7 #include <malloc.h>
   8 #include <asm/io.h>
   9 #include <asm/arch/grf_rk3308.h>
  10 #include <asm/arch-rockchip/hardware.h>
  11 #include <asm/gpio.h>
  12 #include <debug_uart.h>
  13
  14 DECLARE_GLOBAL_DATA_PTR;
  15
  16 #include <asm/armv8/mmu.h>
  17 static struct mm_region rk3308_mem_map[] = {
  18         {
  19                 .virt = 0x0UL,
  20                 .phys = 0x0UL,
  21                 .size = 0xff000000UL,
  22                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  23                          PTE_BLOCK_INNER_SHARE
  24         }, {
  25                 .virt = 0xff000000UL,
  26                 .phys = 0xff000000UL,
  27                 .size = 0x01000000UL,
  28                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  29                          PTE_BLOCK_NON_SHARE |
  30                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  31         }, {
  32                 /* List terminator */
  33                 0,
  34         }
  35 };
  36
  37 struct mm_region *mem_map = rk3308_mem_map;
  38
  39 #define GRF_BASE        0xff000000
  40 #define SGRF_BASE       0xff2b0000
  41
  42 enum {
  43         GPIO1C7_SHIFT           = 8,
  44         GPIO1C7_MASK            = GENMASK(11, 8),
  45         GPIO1C7_GPIO            = 0,
  46         GPIO1C7_UART1_RTSN,
  47         GPIO1C7_UART2_TX_M0,
  48         GPIO1C7_SPI2_MOSI,
  49         GPIO1C7_JTAG_TMS,
  50
  51         GPIO1C6_SHIFT           = 4,
  52         GPIO1C6_MASK            = GENMASK(7, 4),
  53         GPIO1C6_GPIO            = 0,
  54         GPIO1C6_UART1_CTSN,
  55         GPIO1C6_UART2_RX_M0,
  56         GPIO1C6_SPI2_MISO,
  57         GPIO1C6_JTAG_TCLK,
  58
  59         GPIO4D3_SHIFT           = 6,
  60         GPIO4D3_MASK            = GENMASK(7, 6),
  61         GPIO4D3_GPIO            = 0,
  62         GPIO4D3_SDMMC_D3,
  63         GPIO4D3_UART2_TX_M1,
  64
  65         GPIO4D2_SHIFT           = 4,
  66         GPIO4D2_MASK            = GENMASK(5, 4),
  67         GPIO4D2_GPIO            = 0,
  68         GPIO4D2_SDMMC_D2,
  69         GPIO4D2_UART2_RX_M1,
  70
  71         UART2_IO_SEL_SHIFT      = 2,
  72         UART2_IO_SEL_MASK       = GENMASK(3, 2),
  73         UART2_IO_SEL_M0         = 0,
  74         UART2_IO_SEL_M1,
  75         UART2_IO_SEL_USB,
  76
  77         GPIO2C0_SEL_SRC_CTRL_SHIFT      = 11,
  78         GPIO2C0_SEL_SRC_CTRL_MASK       = BIT(11),
  79         GPIO2C0_SEL_SRC_CTRL_IOMUX      = 0,
  80         GPIO2C0_SEL_SRC_CTRL_SEL_PLUS,
  81
  82         GPIO3B3_SEL_SRC_CTRL_SHIFT      = 7,
  83         GPIO3B3_SEL_SRC_CTRL_MASK       = BIT(7),
  84         GPIO3B3_SEL_SRC_CTRL_IOMUX      = 0,
  85         GPIO3B3_SEL_SRC_CTRL_SEL_PLUS,
  86
  87         GPIO3B3_SEL_PLUS_SHIFT          = 4,
  88         GPIO3B3_SEL_PLUS_MASK           = GENMASK(6, 4),
  89         GPIO3B3_SEL_PLUS_GPIO3_B3       = 0,
  90         GPIO3B3_SEL_PLUS_FLASH_ALE,
  91         GPIO3B3_SEL_PLUS_EMMC_PWREN,
  92         GPIO3B3_SEL_PLUS_SPI1_CLK,
  93         GPIO3B3_SEL_PLUS_LCDC_D23_M1,
  94
  95         GPIO3B2_SEL_SRC_CTRL_SHIFT      = 3,
  96         GPIO3B2_SEL_SRC_CTRL_MASK       = BIT(3),
  97         GPIO3B2_SEL_SRC_CTRL_IOMUX      = 0,
  98         GPIO3B2_SEL_SRC_CTRL_SEL_PLUS,
  99
 100         GPIO3B2_SEL_PLUS_SHIFT          = 0,
 101         GPIO3B2_SEL_PLUS_MASK           = GENMASK(2, 0),
 102         GPIO3B2_SEL_PLUS_GPIO3_B2       = 0,
 103         GPIO3B2_SEL_PLUS_FLASH_RDN,
 104         GPIO3B2_SEL_PLUS_EMMC_RSTN,
 105         GPIO3B2_SEL_PLUS_SPI1_MISO,
 106         GPIO3B2_SEL_PLUS_LCDC_D22_M1,
 107
 108         I2C3_IOFUNC_SRC_CTRL_SHIFT      = 10,
 109         I2C3_IOFUNC_SRC_CTRL_MASK       = BIT(10),
 110         I2C3_IOFUNC_SRC_CTRL_SEL_PLUS   = 1,
 111
 112         GPIO2A3_SEL_SRC_CTRL_SHIFT      = 7,
 113         GPIO2A3_SEL_SRC_CTRL_MASK       = BIT(7),
 114         GPIO2A3_SEL_SRC_CTRL_SEL_PLUS   = 1,
 115
 116         GPIO2A2_SEL_SRC_CTRL_SHIFT      = 3,
 117         GPIO2A2_SEL_SRC_CTRL_MASK       = BIT(3),
 118         GPIO2A2_SEL_SRC_CTRL_SEL_PLUS   = 1,
 119 };
 120
 121 enum {
 122         IOVSEL3_CTRL_SHIFT      = 8,
 123         IOVSEL3_CTRL_MASK       = BIT(8),
 124         VCCIO3_SEL_BY_GPIO      = 0,
 125         VCCIO3_SEL_BY_IOVSEL3,
 126
 127         IOVSEL3_SHIFT           = 3,
 128         IOVSEL3_MASK            = BIT(3),
 129         VCCIO3_3V3              = 0,
 130         VCCIO3_1V8,
 131 };
 132
 133 /*
 134  * The voltage of VCCIO3(which is the voltage domain of emmc/flash/sfc
 135  * interface) can indicated by GPIO0_A4 or io_vsel3. The SOC defaults
 136  * use GPIO0_A4 to indicate power supply voltage for VCCIO3 by hardware,
 137  * then we can switch to io_vsel3 after system power on, and release GPIO0_A4
 138  * for other usage.
 139  */
 140
 141 #define GPIO0_A4        4
 142
 143 int rk_board_init(void)
 144 {
 145         static struct rk3308_grf * const grf = (void *)GRF_BASE;
 146         u32 val;
 147         int ret;
 148
 149         ret = gpio_request(GPIO0_A4, "gpio0_a4");
 150         if (ret < 0) {
 151                 printf("request for gpio0_a4 failed:%d\n", ret);
 152                 return 0;
 153         }
 154
 155         gpio_direction_input(GPIO0_A4);
 156
 157         if (gpio_get_value(GPIO0_A4))
 158                 val = VCCIO3_SEL_BY_IOVSEL3 << IOVSEL3_CTRL_SHIFT |
 159                       VCCIO3_1V8 << IOVSEL3_SHIFT;
 160         else
 161                 val = VCCIO3_SEL_BY_IOVSEL3 << IOVSEL3_CTRL_SHIFT |
 162                       VCCIO3_3V3 << IOVSEL3_SHIFT;
 163         rk_clrsetreg(&grf->soc_con0, IOVSEL3_CTRL_MASK | IOVSEL3_MASK, val);
 164
 165         gpio_free(GPIO0_A4);
 166         return 0;
 167 }
 168
 169 #if defined(CONFIG_DEBUG_UART)
 170 __weak void board_debug_uart_init(void)
 171 {
 172         static struct rk3308_grf * const grf = (void *)GRF_BASE;
 173
 174         /* Enable early UART2 channel m1 on the rk3308 */
 175         rk_clrsetreg(&grf->soc_con5, UART2_IO_SEL_MASK,
 176                      UART2_IO_SEL_M1 << UART2_IO_SEL_SHIFT);
 177         rk_clrsetreg(&grf->gpio4d_iomux,
 178                      GPIO4D3_MASK | GPIO4D2_MASK,
 179                      GPIO4D2_UART2_RX_M1 << GPIO4D2_SHIFT |
 180                      GPIO4D3_UART2_TX_M1 << GPIO4D3_SHIFT);
 181 }
 182 #endif
 183
 184 #if defined(CONFIG_SPL_BUILD)
 185 int arch_cpu_init(void)
 186 {
 187         static struct rk3308_sgrf * const sgrf = (void *)SGRF_BASE;
 188         static struct rk3308_grf * const grf = (void *)GRF_BASE;
 189
 190         /* Set CRYPTO SDMMC EMMC NAND SFC USB master bus to be secure access */
 191         rk_clrreg(&sgrf->con_secure0, 0x2b83);
 192
 193         /*
 194          * Enable plus options to use more pinctrl functions, including
 195          * GPIO2A2_PLUS, GPIO2A3_PLUS and I2C3_MULTI_SRC_PLUS.
 196          */
 197         rk_clrsetreg(&grf->soc_con13,
 198                      I2C3_IOFUNC_SRC_CTRL_MASK | GPIO2A3_SEL_SRC_CTRL_MASK |
 199                      GPIO2A2_SEL_SRC_CTRL_MASK,
 200                      I2C3_IOFUNC_SRC_CTRL_SEL_PLUS << I2C3_IOFUNC_SRC_CTRL_SHIFT |
 201                      GPIO2A3_SEL_SRC_CTRL_SEL_PLUS << GPIO2A3_SEL_SRC_CTRL_SHIFT |
 202                      GPIO2A2_SEL_SRC_CTRL_SEL_PLUS << GPIO2A2_SEL_SRC_CTRL_SHIFT);
 203
 204         /* Plus options about GPIO3B2_PLUS, GPIO3B3_PLUS and GPIO2C0_PLUS. */
 205         rk_clrsetreg(&grf->soc_con15,
 206                      GPIO2C0_SEL_SRC_CTRL_MASK | GPIO3B3_SEL_SRC_CTRL_MASK |
 207                      GPIO3B2_SEL_SRC_CTRL_MASK,
 208                      GPIO2C0_SEL_SRC_CTRL_SEL_PLUS << GPIO2C0_SEL_SRC_CTRL_SHIFT |
 209                      GPIO3B3_SEL_SRC_CTRL_SEL_PLUS << GPIO3B3_SEL_SRC_CTRL_SHIFT |
 210                      GPIO3B2_SEL_SRC_CTRL_SEL_PLUS << GPIO3B2_SEL_SRC_CTRL_SHIFT);
 211
 212         return 0;
 213 }
 214 #endif