1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * ./arch/arm/mach-renesas/include/mach/rcar-gen4-base.h
5 * Copyright (C) 2021 Renesas Electronics Corp.
8 #ifndef __ASM_ARCH_RCAR_GEN4_BASE_H
9 #define __ASM_ARCH_RCAR_GEN4_BASE_H
12 * R-Car (R8A779F0) I/O Addresses
14 #define RWDT_BASE 0xE6020000
15 #define SWDT_BASE 0xE6030000
16 #define TMU_BASE 0xE61E0000
19 #define SCIF0_BASE 0xE6E60000
20 #define SCIF1_BASE 0xE6E68000
21 #define SCIF2_BASE 0xE6E88000
22 #define SCIF3_BASE 0xE6C50000
23 #define SCIF4_BASE 0xE6C40000
24 #define SCIF5_BASE 0xE6F30000
27 #define CPGWPR 0xE6150000
28 #define CPGWPCR 0xE6150004
31 #define RST_BASE 0xE6160000 /* Domain0 */
32 #define RST_SRESCR0 (RST_BASE + 0x18)
33 #define RST_SPRES 0x5AA58000
35 /* Arm Generic Timer */
36 #define CNTCR_BASE 0xE6080000
37 #define CNTFID0 (CNTCR_BASE + 0x020)
38 #define CNTCR_EN BIT(0)
41 /* Distributor Registers */
42 #define GICD_BASE 0xF1000000
43 #define GICR_BASE (GICR_LPI_BASE)
45 /* ReDistributor Registers for Control and Physical LPIs */
46 #define GICR_LPI_BASE 0xF1060000
47 #define GICR_WAKER 0x0014
48 #define GICR_PWRR 0x0024
49 #define GICR_LPI_WAKER (GICR_LPI_BASE + GICR_WAKER)
50 #define GICR_LPI_PWRR (GICR_LPI_BASE + GICR_PWRR)
52 /* ReDistributor Registers for SGIs and PPIs */
53 #define GICR_SGI_BASE 0xF1070000
54 #define GICR_IGROUPR0 0x0080
57 #include <asm/types.h>
58 #include <linux/bitops.h>
75 #endif /* __ASM_ARCH_RCAR_GEN4_BASE_H */