2 * linux/arch/arm/mach-pxa/irq.c
4 * Generic PXA IRQ handling, GPIO IRQ demultiplexing, etc.
6 * Author: Nicolas Pitre
7 * Created: Jun 15, 2001
8 * Copyright: MontaVista Software Inc.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/sysdev.h>
20 #include <asm/hardware.h>
22 #include <asm/mach/irq.h>
23 #include <asm/arch/pxa-regs.h>
29 * This is for peripheral IRQs internal to the PXA chip.
32 static void pxa_mask_low_irq(unsigned int irq)
37 static void pxa_unmask_low_irq(unsigned int irq)
42 static struct irq_chip pxa_internal_chip_low = {
44 .ack = pxa_mask_low_irq,
45 .mask = pxa_mask_low_irq,
46 .unmask = pxa_unmask_low_irq,
49 void __init pxa_init_irq_low(void)
53 /* disable all IRQs */
56 /* all IRQs are IRQ, not FIQ */
59 /* only unmasked interrupts kick us out of idle */
62 for (irq = PXA_IRQ(0); irq <= PXA_IRQ(31); irq++) {
63 set_irq_chip(irq, &pxa_internal_chip_low);
64 set_irq_handler(irq, handle_level_irq);
65 set_irq_flags(irq, IRQF_VALID);
69 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
72 * This is for the second set of internal IRQs as found on the PXA27x.
75 static void pxa_mask_high_irq(unsigned int irq)
77 ICMR2 &= ~(1 << (irq - 32));
80 static void pxa_unmask_high_irq(unsigned int irq)
82 ICMR2 |= (1 << (irq - 32));
85 static struct irq_chip pxa_internal_chip_high = {
87 .ack = pxa_mask_high_irq,
88 .mask = pxa_mask_high_irq,
89 .unmask = pxa_unmask_high_irq,
92 void __init pxa_init_irq_high(void)
99 for (irq = PXA_IRQ(32); irq < PXA_IRQ(64); irq++) {
100 set_irq_chip(irq, &pxa_internal_chip_high);
101 set_irq_handler(irq, handle_level_irq);
102 set_irq_flags(irq, IRQF_VALID);
108 * PXA GPIO edge detection for IRQs:
109 * IRQs are generated on Falling-Edge, Rising-Edge, or both.
110 * Use this instead of directly setting GRER/GFER.
113 static long GPIO_IRQ_rising_edge[4];
114 static long GPIO_IRQ_falling_edge[4];
115 static long GPIO_IRQ_mask[4];
117 static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
121 gpio = IRQ_TO_GPIO(irq);
124 if (type == IRQT_PROBE) {
125 /* Don't mess with enabled GPIOs using preconfigured edges or
126 GPIOs set to alternate function or to output during probe */
127 if ((GPIO_IRQ_rising_edge[idx] | GPIO_IRQ_falling_edge[idx] | GPDR(gpio)) &
130 if (GAFR(gpio) & (0x3 << (((gpio) & 0xf)*2)))
132 type = __IRQT_RISEDGE | __IRQT_FALEDGE;
135 /* printk(KERN_DEBUG "IRQ%d (GPIO%d): ", irq, gpio); */
137 pxa_gpio_mode(gpio | GPIO_IN);
139 if (type & __IRQT_RISEDGE) {
140 /* printk("rising "); */
141 __set_bit (gpio, GPIO_IRQ_rising_edge);
143 __clear_bit (gpio, GPIO_IRQ_rising_edge);
146 if (type & __IRQT_FALEDGE) {
147 /* printk("falling "); */
148 __set_bit (gpio, GPIO_IRQ_falling_edge);
150 __clear_bit (gpio, GPIO_IRQ_falling_edge);
153 /* printk("edges\n"); */
155 GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
156 GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];
161 * GPIO IRQs must be acknowledged. This is for GPIO 0 and 1.
164 static void pxa_ack_low_gpio(unsigned int irq)
166 GEDR0 = (1 << (irq - IRQ_GPIO0));
169 static void pxa_mask_low_gpio(unsigned int irq)
171 ICMR &= ~(1 << (irq - PXA_IRQ(0)));
174 static void pxa_unmask_low_gpio(unsigned int irq)
176 ICMR |= 1 << (irq - PXA_IRQ(0));
179 static struct irq_chip pxa_low_gpio_chip = {
181 .ack = pxa_ack_low_gpio,
182 .mask = pxa_mask_low_gpio,
183 .unmask = pxa_unmask_low_gpio,
184 .set_type = pxa_gpio_irq_type,
188 * Demux handler for GPIO>=2 edge detect interrupts
191 #define GEDR_BITS (sizeof(gedr) * BITS_PER_BYTE)
193 static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
196 unsigned long gedr[4];
199 gedr[0] = GEDR0 & GPIO_IRQ_mask[0] & ~3;
200 gedr[1] = GEDR1 & GPIO_IRQ_mask[1];
201 gedr[2] = GEDR2 & GPIO_IRQ_mask[2];
202 gedr[3] = GEDR3 & GPIO_IRQ_mask[3];
204 GEDR0 = gedr[0]; GEDR1 = gedr[1];
205 GEDR2 = gedr[2]; GEDR3 = gedr[3];
208 bit = find_first_bit(gedr, GEDR_BITS);
209 while (bit < GEDR_BITS) {
212 n = PXA_GPIO_IRQ_BASE + bit;
213 desc_handle_irq(n, irq_desc + n);
215 bit = find_next_bit(gedr, GEDR_BITS, bit + 1);
220 static void pxa_ack_muxed_gpio(unsigned int irq)
222 int gpio = irq - IRQ_GPIO(2) + 2;
223 GEDR(gpio) = GPIO_bit(gpio);
226 static void pxa_mask_muxed_gpio(unsigned int irq)
228 int gpio = irq - IRQ_GPIO(2) + 2;
229 __clear_bit(gpio, GPIO_IRQ_mask);
230 GRER(gpio) &= ~GPIO_bit(gpio);
231 GFER(gpio) &= ~GPIO_bit(gpio);
234 static void pxa_unmask_muxed_gpio(unsigned int irq)
236 int gpio = irq - IRQ_GPIO(2) + 2;
238 __set_bit(gpio, GPIO_IRQ_mask);
239 GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
240 GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];
243 static struct irq_chip pxa_muxed_gpio_chip = {
245 .ack = pxa_ack_muxed_gpio,
246 .mask = pxa_mask_muxed_gpio,
247 .unmask = pxa_unmask_muxed_gpio,
248 .set_type = pxa_gpio_irq_type,
251 void __init pxa_init_irq_gpio(int gpio_nr)
255 pxa_last_gpio = gpio_nr - 1;
257 /* clear all GPIO edge detects */
258 for (i = 0; i < gpio_nr; i += 32) {
264 /* GPIO 0 and 1 must have their mask bit always set */
265 GPIO_IRQ_mask[0] = 3;
267 for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) {
268 set_irq_chip(irq, &pxa_low_gpio_chip);
269 set_irq_handler(irq, handle_edge_irq);
270 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
273 for (irq = IRQ_GPIO(2); irq < IRQ_GPIO(gpio_nr); irq++) {
274 set_irq_chip(irq, &pxa_muxed_gpio_chip);
275 set_irq_handler(irq, handle_edge_irq);
276 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
279 /* Install handler for GPIO>=2 edge detect interrupts */
280 set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler);
282 pxa_init_gpio(gpio_nr);
285 void __init pxa_init_gpio_set_wake(int (*set_wake)(unsigned int, unsigned int))
287 pxa_low_gpio_chip.set_wake = set_wake;
288 pxa_muxed_gpio_chip.set_wake = set_wake;
291 void __init pxa_init_irq_set_wake(int (*set_wake)(unsigned int, unsigned int))
293 pxa_internal_chip_low.set_wake = set_wake;
295 pxa_internal_chip_high.set_wake = set_wake;
297 pxa_init_gpio_set_wake(set_wake);
301 static unsigned long saved_icmr[2];
303 static int pxa_irq_suspend(struct sys_device *dev, pm_message_t state)
307 saved_icmr[0] = ICMR;
310 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
312 saved_icmr[1] = ICMR2;
323 static int pxa_irq_resume(struct sys_device *dev)
327 ICMR = saved_icmr[0];
331 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
333 ICMR2 = saved_icmr[1];
344 #define pxa_irq_suspend NULL
345 #define pxa_irq_resume NULL
348 struct sysdev_class pxa_irq_sysclass = {
350 .suspend = pxa_irq_suspend,
351 .resume = pxa_irq_resume,
354 static int __init pxa_irq_init(void)
356 return sysdev_class_register(&pxa_irq_sysclass);
359 core_initcall(pxa_irq_init);