2 * linux/arch/arm/mach-pxa/irq.c
4 * Generic PXA IRQ handling
6 * Author: Nicolas Pitre
7 * Created: Jun 15, 2001
8 * Copyright: MontaVista Software Inc.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/syscore_ops.h>
20 #include <linux/irq.h>
22 #include <asm/exception.h>
24 #include <mach/hardware.h>
25 #include <mach/irqs.h>
26 #include <mach/gpio.h>
30 #define IRQ_BASE (void __iomem *)io_p2v(0x40d00000)
39 #define IPR(i) (((i) < 32) ? (0x01c + ((i) << 2)) : \
40 ((i) < 64) ? (0x0b0 + (((i) - 32) << 2)) : \
41 (0x144 + (((i) - 64) << 2)))
42 #define ICHP_VAL_IRQ (1 << 31)
43 #define ICHP_IRQ(i) (((i) >> 16) & 0x7fff)
44 #define IPR_VALID (1 << 31)
45 #define IRQ_BIT(n) (((n) - PXA_IRQ(0)) & 0x1f)
47 #define MAX_INTERNAL_IRQS 128
50 * This is for peripheral IRQs internal to the PXA chip.
53 static int pxa_internal_irq_nr;
55 static inline int cpu_has_ipr(void)
57 return !cpu_is_pxa25x();
60 static inline void __iomem *irq_base(int i)
62 static unsigned long phys_base[] = {
68 return (void __iomem *)io_p2v(phys_base[i]);
71 void pxa_mask_irq(struct irq_data *d)
73 void __iomem *base = irq_data_get_irq_chip_data(d);
74 uint32_t icmr = __raw_readl(base + ICMR);
76 icmr &= ~(1 << IRQ_BIT(d->irq));
77 __raw_writel(icmr, base + ICMR);
80 void pxa_unmask_irq(struct irq_data *d)
82 void __iomem *base = irq_data_get_irq_chip_data(d);
83 uint32_t icmr = __raw_readl(base + ICMR);
85 icmr |= 1 << IRQ_BIT(d->irq);
86 __raw_writel(icmr, base + ICMR);
89 static struct irq_chip pxa_internal_irq_chip = {
91 .irq_ack = pxa_mask_irq,
92 .irq_mask = pxa_mask_irq,
93 .irq_unmask = pxa_unmask_irq,
97 * GPIO IRQs for GPIO 0 and 1
99 static int pxa_set_low_gpio_type(struct irq_data *d, unsigned int type)
101 int gpio = d->irq - IRQ_GPIO0;
103 if (__gpio_is_occupied(gpio)) {
104 pr_err("%s failed: GPIO is configured\n", __func__);
108 if (type & IRQ_TYPE_EDGE_RISING)
109 GRER0 |= GPIO_bit(gpio);
111 GRER0 &= ~GPIO_bit(gpio);
113 if (type & IRQ_TYPE_EDGE_FALLING)
114 GFER0 |= GPIO_bit(gpio);
116 GFER0 &= ~GPIO_bit(gpio);
121 static void pxa_ack_low_gpio(struct irq_data *d)
123 GEDR0 = (1 << (d->irq - IRQ_GPIO0));
126 static struct irq_chip pxa_low_gpio_chip = {
128 .irq_ack = pxa_ack_low_gpio,
129 .irq_mask = pxa_mask_irq,
130 .irq_unmask = pxa_unmask_irq,
131 .irq_set_type = pxa_set_low_gpio_type,
134 asmlinkage void __exception_irq_entry icip_handle_irq(struct pt_regs *regs)
136 uint32_t icip, icmr, mask;
139 icip = __raw_readl(IRQ_BASE + ICIP);
140 icmr = __raw_readl(IRQ_BASE + ICMR);
146 handle_IRQ(PXA_IRQ(fls(mask) - 1), regs);
150 asmlinkage void __exception_irq_entry ichp_handle_irq(struct pt_regs *regs)
155 __asm__ __volatile__("mrc p6, 0, %0, c5, c0, 0\n": "=r"(ichp));
157 if ((ichp & ICHP_VAL_IRQ) == 0)
160 handle_IRQ(PXA_IRQ(ICHP_IRQ(ichp)), regs);
164 static void __init pxa_init_low_gpio_irq(set_wake_t fn)
168 /* clear edge detection on GPIO 0 and 1 */
173 for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) {
174 irq_set_chip_and_handler(irq, &pxa_low_gpio_chip,
176 irq_set_chip_data(irq, irq_base(0));
177 set_irq_flags(irq, IRQF_VALID);
180 pxa_low_gpio_chip.irq_set_wake = fn;
183 void __init pxa_init_irq(int irq_nr, set_wake_t fn)
187 BUG_ON(irq_nr > MAX_INTERNAL_IRQS);
189 pxa_internal_irq_nr = irq_nr;
191 for (n = 0; n < irq_nr; n += 32) {
192 void __iomem *base = irq_base(n >> 5);
194 __raw_writel(0, base + ICMR); /* disable all IRQs */
195 __raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */
196 for (i = n; (i < (n + 32)) && (i < irq_nr); i++) {
197 /* initialize interrupt priority */
199 __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i));
202 irq_set_chip_and_handler(irq, &pxa_internal_irq_chip,
204 irq_set_chip_data(irq, base);
205 set_irq_flags(irq, IRQF_VALID);
209 /* only unmasked interrupts kick us out of idle */
210 __raw_writel(1, irq_base(0) + ICCR);
212 pxa_internal_irq_chip.irq_set_wake = fn;
213 pxa_init_low_gpio_irq(fn);
217 static unsigned long saved_icmr[MAX_INTERNAL_IRQS/32];
218 static unsigned long saved_ipr[MAX_INTERNAL_IRQS];
220 static int pxa_irq_suspend(void)
224 for (i = 0; i < pxa_internal_irq_nr / 32; i++) {
225 void __iomem *base = irq_base(i);
227 saved_icmr[i] = __raw_readl(base + ICMR);
228 __raw_writel(0, base + ICMR);
232 for (i = 0; i < pxa_internal_irq_nr; i++)
233 saved_ipr[i] = __raw_readl(IRQ_BASE + IPR(i));
239 static void pxa_irq_resume(void)
243 for (i = 0; i < pxa_internal_irq_nr / 32; i++) {
244 void __iomem *base = irq_base(i);
246 __raw_writel(saved_icmr[i], base + ICMR);
247 __raw_writel(0, base + ICLR);
251 for (i = 0; i < pxa_internal_irq_nr; i++)
252 __raw_writel(saved_ipr[i], IRQ_BASE + IPR(i));
254 __raw_writel(1, IRQ_BASE + ICCR);
257 #define pxa_irq_suspend NULL
258 #define pxa_irq_resume NULL
261 struct syscore_ops pxa_irq_syscore_ops = {
262 .suspend = pxa_irq_suspend,
263 .resume = pxa_irq_resume,