2 * linux/arch/arm/mach-pxa/irq.c
4 * Generic PXA IRQ handling, GPIO IRQ demultiplexing, etc.
6 * Author: Nicolas Pitre
7 * Created: Jun 15, 2001
8 * Copyright: MontaVista Software Inc.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
19 #include <asm/hardware.h>
21 #include <asm/mach/irq.h>
22 #include <asm/arch/pxa-regs.h>
28 * This is for peripheral IRQs internal to the PXA chip.
31 static void pxa_mask_low_irq(unsigned int irq)
33 ICMR &= ~(1 << (irq + PXA_IRQ_SKIP));
36 static void pxa_unmask_low_irq(unsigned int irq)
38 ICMR |= (1 << (irq + PXA_IRQ_SKIP));
41 static struct irq_chip pxa_internal_chip_low = {
43 .ack = pxa_mask_low_irq,
44 .mask = pxa_mask_low_irq,
45 .unmask = pxa_unmask_low_irq,
48 #if PXA_INTERNAL_IRQS > 32
51 * This is for the second set of internal IRQs as found on the PXA27x.
54 static void pxa_mask_high_irq(unsigned int irq)
56 ICMR2 &= ~(1 << (irq - 32 + PXA_IRQ_SKIP));
59 static void pxa_unmask_high_irq(unsigned int irq)
61 ICMR2 |= (1 << (irq - 32 + PXA_IRQ_SKIP));
64 static struct irq_chip pxa_internal_chip_high = {
66 .ack = pxa_mask_high_irq,
67 .mask = pxa_mask_high_irq,
68 .unmask = pxa_unmask_high_irq,
74 * PXA GPIO edge detection for IRQs:
75 * IRQs are generated on Falling-Edge, Rising-Edge, or both.
76 * Use this instead of directly setting GRER/GFER.
79 static long GPIO_IRQ_rising_edge[4];
80 static long GPIO_IRQ_falling_edge[4];
81 static long GPIO_IRQ_mask[4];
83 static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
87 gpio = IRQ_TO_GPIO(irq);
90 if (type == IRQT_PROBE) {
91 /* Don't mess with enabled GPIOs using preconfigured edges or
92 GPIOs set to alternate function or to output during probe */
93 if ((GPIO_IRQ_rising_edge[idx] | GPIO_IRQ_falling_edge[idx] | GPDR(gpio)) &
96 if (GAFR(gpio) & (0x3 << (((gpio) & 0xf)*2)))
98 type = __IRQT_RISEDGE | __IRQT_FALEDGE;
101 /* printk(KERN_DEBUG "IRQ%d (GPIO%d): ", irq, gpio); */
103 pxa_gpio_mode(gpio | GPIO_IN);
105 if (type & __IRQT_RISEDGE) {
106 /* printk("rising "); */
107 __set_bit (gpio, GPIO_IRQ_rising_edge);
109 __clear_bit (gpio, GPIO_IRQ_rising_edge);
111 if (type & __IRQT_FALEDGE) {
112 /* printk("falling "); */
113 __set_bit (gpio, GPIO_IRQ_falling_edge);
115 __clear_bit (gpio, GPIO_IRQ_falling_edge);
117 /* printk("edges\n"); */
119 GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
120 GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];
125 * GPIO IRQs must be acknowledged. This is for GPIO 0 and 1.
128 static void pxa_ack_low_gpio(unsigned int irq)
130 GEDR0 = (1 << (irq - IRQ_GPIO0));
133 static struct irq_chip pxa_low_gpio_chip = {
135 .ack = pxa_ack_low_gpio,
136 .mask = pxa_mask_low_irq,
137 .unmask = pxa_unmask_low_irq,
138 .set_type = pxa_gpio_irq_type,
142 * Demux handler for GPIO>=2 edge detect interrupts
145 static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
157 desc = irq_desc + irq;
161 desc_handle_irq(irq, desc);
173 desc = irq_desc + irq;
176 desc_handle_irq(irq, desc);
188 desc = irq_desc + irq;
191 desc_handle_irq(irq, desc);
199 #if PXA_LAST_GPIO >= 96
204 desc = irq_desc + irq;
207 desc_handle_irq(irq, desc);
218 static void pxa_ack_muxed_gpio(unsigned int irq)
220 int gpio = irq - IRQ_GPIO(2) + 2;
221 GEDR(gpio) = GPIO_bit(gpio);
224 static void pxa_mask_muxed_gpio(unsigned int irq)
226 int gpio = irq - IRQ_GPIO(2) + 2;
227 __clear_bit(gpio, GPIO_IRQ_mask);
228 GRER(gpio) &= ~GPIO_bit(gpio);
229 GFER(gpio) &= ~GPIO_bit(gpio);
232 static void pxa_unmask_muxed_gpio(unsigned int irq)
234 int gpio = irq - IRQ_GPIO(2) + 2;
236 __set_bit(gpio, GPIO_IRQ_mask);
237 GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
238 GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];
241 static struct irq_chip pxa_muxed_gpio_chip = {
243 .ack = pxa_ack_muxed_gpio,
244 .mask = pxa_mask_muxed_gpio,
245 .unmask = pxa_unmask_muxed_gpio,
246 .set_type = pxa_gpio_irq_type,
250 void __init pxa_init_irq(void)
254 /* disable all IRQs */
257 /* all IRQs are IRQ, not FIQ */
260 /* clear all GPIO edge detects */
272 /* And similarly for the extra regs on the PXA27x */
280 /* only unmasked interrupts kick us out of idle */
283 /* GPIO 0 and 1 must have their mask bit always set */
284 GPIO_IRQ_mask[0] = 3;
286 for (irq = PXA_IRQ(PXA_IRQ_SKIP); irq <= PXA_IRQ(31); irq++) {
287 set_irq_chip(irq, &pxa_internal_chip_low);
288 set_irq_handler(irq, handle_level_irq);
289 set_irq_flags(irq, IRQF_VALID);
292 #if PXA_INTERNAL_IRQS > 32
293 for (irq = PXA_IRQ(32); irq < PXA_IRQ(PXA_INTERNAL_IRQS); irq++) {
294 set_irq_chip(irq, &pxa_internal_chip_high);
295 set_irq_handler(irq, handle_level_irq);
296 set_irq_flags(irq, IRQF_VALID);
300 for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) {
301 set_irq_chip(irq, &pxa_low_gpio_chip);
302 set_irq_handler(irq, handle_edge_irq);
303 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
306 for (irq = IRQ_GPIO(2); irq <= IRQ_GPIO(PXA_LAST_GPIO); irq++) {
307 set_irq_chip(irq, &pxa_muxed_gpio_chip);
308 set_irq_handler(irq, handle_edge_irq);
309 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
312 /* Install handler for GPIO>=2 edge detect interrupts */
313 set_irq_chip(IRQ_GPIO_2_x, &pxa_internal_chip_low);
314 set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler);